KR100562312B1 - Fabrication method of semiconductor device - Google Patents

Fabrication method of semiconductor device Download PDF

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KR100562312B1
KR100562312B1 KR1020030069181A KR20030069181A KR100562312B1 KR 100562312 B1 KR100562312 B1 KR 100562312B1 KR 1020030069181 A KR1020030069181 A KR 1020030069181A KR 20030069181 A KR20030069181 A KR 20030069181A KR 100562312 B1 KR100562312 B1 KR 100562312B1
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etching
reflection film
film
antireflection film
metal wiring
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KR20050033212A (en
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김중규
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동부아남반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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Abstract

금속배선의 식각된 측면 프로파일을 개선하기 위해, 본 발명에서는, 반도체 기판 상에 금속배선층을 형성하는 단계; 금속배선층 상에 제1반사방지막 및 제2반사방지막을 순차 형성하는 단계; 제2반사방지막 상에 감광막 패턴을 형성하는 단계; 및 감광막 패턴을 마스크로 하여 제2반사방지막, 제1반사방지막, 및 금속배선층을 각각 서로 다른 식각조건으로 식각하는 단계를 포함하여 반도체 소자를 제조한다.In order to improve the etched side profile of the metallization, the present invention includes the steps of forming a metallization layer on a semiconductor substrate; Sequentially forming a first antireflection film and a second antireflection film on the metal wiring layer; Forming a photoresist pattern on the second anti-reflection film; And etching the second antireflection film, the first antireflection film, and the metal wiring layer under different etching conditions using the photoresist pattern as a mask.

배선, 반사방지막, 식각 Wiring, anti-reflection film, etching

Description

반도체 소자 제조 방법 {Fabrication method of semiconductor device} Fabrication method of semiconductor device

도 1a 내지 1e는 종래 반도체 소자 제조 방법을 그 공정 순서에 따라 도시한 단면도이고,1A to 1E are cross-sectional views illustrating a conventional semiconductor device manufacturing method in accordance with a process sequence thereof;

도 2a는 종래 제2반사방지막과 제1반사방지막까지 식각한 것을 보여주는 현미경 사진이며, 도 2b는 종래 제2반사방지막, 제1반사방지막, 및 금속배선층 모두를 식각한 것을 보여주는 현미경사진이고,Figure 2a is a micrograph showing a conventional second antireflection film and the first antireflection film etched, Figure 2b is a photomicrograph showing the etching of the conventional second antireflection film, the first antireflection film, and the metal wiring layer,

도 3은 종래 층간절연막 내에 보이드가 형성된 것을 보여주는 현미경 사진이며,3 is a micrograph showing that voids are formed in a conventional interlayer insulating film.

도 4a 내지 4e는 본 발명의 일 실시예에 따른 반도체 소자 제조 방법을 그 공정 순서에 따라 도시한 단면도이며,4A through 4E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention according to a process sequence thereof;

도 5a는 본 발명에 따라 제2반사방지막과 제1반사방지막까지 식각한 것을 보여주는 현미경 사진이고, 도 5b는 본 발명에 따라 제2반사방지막, 제1반사방지막, 및 금속배선층 모두를 식각한 것을 보여주는 현미경사진이며,Figure 5a is a micrograph showing the etching of the second antireflection film and the first antireflection film in accordance with the present invention, Figure 5b is an etching of both the second antireflection film, the first antireflection film, and the metal wiring layer in accordance with the present invention Showing micrograph,

도 6은 본 발명에 따라 층간절연막이 보이드 없이 형성된 것을 보여주는 현미경 사진이다. 6 is a micrograph showing that an interlayer insulating film is formed without voids according to the present invention.

본 발명은 반도체 소자 제조방법에 관한 것으로 더욱 상세하게는 금속배선층을 패터닝하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for patterning a metal wiring layer.

반도체 소자의 고집적화 추세에 따라 금속배선의 폭 치수 및 금속배선 간 간격이 갈수록 감소하고 있다. 따라서, 금속배선의 측면 프로파일이 매우 중요해진다.In accordance with the trend of higher integration of semiconductor devices, the width dimension of the metal wiring and the spacing between the metal wirings are gradually decreasing. Therefore, the side profile of the metallization becomes very important.

한편, 비아홀 형성을 위한 층간절연막 식각 시 Al 금속배선 상에서 식각을 종료하는 경우, Al이 상부로 돌출되는 문제, 비아 내벽에 형성하는 베리어메탈 공정의 불안정, 발생된 Polymer 에 의한 비아 저항이 증가하는 문제 등이 발생하였다. On the other hand, when the etching is terminated on the Al metal wiring during the interlayer insulating layer etching to form the via hole, Al protrudes to the top, instability of the barrier metal process to be formed on the inner wall of the via, and increase in the resistance of the via due to the polymer generated. And so on.

이러한 문제들를 개선하기 위해, 비아홀 형성을 위한 층간절연막 식각 시 TiN 상에서 식각을 종료하는 방법을 사용하고 있으며, 이에 따라 금속배선 상부에 형성하는 반사방지막인 Ti/TiN 또는 TiN의 두께가 증가하게 되었다.In order to improve these problems, a method of terminating etching on TiN is used when etching an interlayer insulating layer for forming a via hole, thereby increasing the thickness of Ti / TiN or TiN, which is an anti-reflective layer formed on the metal wiring.

또한, 보다 정밀한 패턴 형성을 위하 보다 더 짧은 파장의 광원을 사용하게 되는데, 이에 따라 심자외선(deep ultra violet : DUV)를 광원으로 사용한 노광공정을 수행하고 있다. 그런데 DUV를 광원으로 이용한 사진식각공정에서는 공정 상 마진 증대를 위해 추가적인 반사방지막으로서 SiON + SiO2 (SiON + SiO2의 복합물)을 요구한다.In addition, a shorter wavelength light source is used to form a more precise pattern. Accordingly, an exposure process using deep ultra violet (DUV) as a light source is performed. However, in the photolithography process using DUV as a light source, SiON + SiO 2 (composite of SiON + SiO 2 ) is required as an additional anti-reflection film to increase the margin in the process.

이러한 SiON + SiO2 반사방지막을 제거하기 위해 종래에는 Cl2, BCl3, 및 CHF3 를 식각가스로 사용하여 왔으나, 식각과정에서 폴리머가 발생되어 식각된 반사방지막의 측면이 수직으로 깨끗하게 식각되지 못하고 경사를 가져 결과적으로 Al 금속에 비해 상부의 반사방지막의 폭 치수가 증가하는 문제점이 있다.In order to remove the SiON + SiO 2 anti-reflection film, Cl 2 , BCl 3 , and CHF 3 have been conventionally used as an etching gas, but polymers are generated during the etching process, and thus the side of the etched anti-reflection film cannot be etched cleanly vertically. As a result, there is a problem that the width of the upper anti-reflection film is increased as compared to Al metal.

즉, 이는 금속배선 간 간격을 줄이는 결과를 가져오므로 후속공정에서 층간절연막을 형성할 때 금속배선 간 간격을 완전히 매립하지 못하고 보이드를 발생시키는 문제점이 있다.That is, since this results in a reduction in the spacing between the metal wirings, there is a problem that voids are generated without filling the gaps between the metal wirings completely when forming the interlayer insulating film in a subsequent process.

이러한 보이드는 웨이퍼에서의 알씨 지연(RC delay) 현상을 유발할 수 있으며, 또한 열 전도도(thermal conductivity)를 저하시켜 궁극적으로 수율 감소의 원인이 된다.These voids can cause RC delay in the wafer and also degrade the thermal conductivity, ultimately causing a decrease in yield.

그러면, 종래 금속배선층을 패터닝 하는 방법에 대해 첨부된 도면을 참조하여 간략하게 설명하면 다음과 같다.Then, with reference to the accompanying drawings for a conventional method for patterning a metal wiring layer will be described briefly as follows.

먼저, 도 1a에 도시된 바와 같이, 반도체 기판의 구조물(10) 상에 베리어막(Ti)(11), 금속배선층(Al)(12), 제1반사방지막(Ti/TiN)(13, 14), 및 제2반사방지막(SiON + SiO2)(15)을 순차 형성한다. 여기서, 반도체 기판의 구조물(100) 최상면에는 하부 절연막이 형성되어 있는 것으로 생각할 수 있다.First, as shown in FIG. 1A, the barrier layer (Ti) 11, the metallization layer (Al) 12, and the first antireflection layer (Ti / TiN) 13 and 14 are formed on the structure 10 of the semiconductor substrate. ) And a second antireflection film (SiON + SiO 2 ) 15 are sequentially formed. Here, it can be considered that the lower insulating film is formed on the uppermost surface of the structure 100 of the semiconductor substrate.

다음, 제2반사방지막(15) 상에 목적하는 디자인을 가지는 감광막 패턴(16)을 형성한다. Next, a photosensitive film pattern 16 having a desired design is formed on the second antireflection film 15.

다음, 도 1b에 도시된 바와 같이, 감광막 패턴(16)을 마스크로 하여 제2반사방지막(15) 및 제1반사방지막(14, 13)을 식각한다. 이 때 제2반사방지막(15)은 Cl2 및 CHF3 를 식각가스로 사용하고 제1반사방지막(14, 13)은 Cl2, BCl3, 및 CHF3를 식각가스로 사용한다. Next, as shown in FIG. 1B, the second antireflection film 15 and the first antireflection films 14 and 13 are etched using the photoresist pattern 16 as a mask. In this case, the second antireflection film 15 uses Cl 2 and CHF 3 as an etching gas, and the first antireflection films 14 and 13 use Cl 2 , BCl 3 , and CHF 3 as etching gas.

그런데 제2반사방지막(SiON + SiO2)(15)의 식각 과정에서 폴리머가 발생하여 식각된 측면이 수직면이 되지 못하고 경사면이 되며, 결과적으로 제1반사방지막(13, 14) 및 제2반사방지막(15)의 폭 치수가 증가하게 된다.However, in the etching process of the second anti-reflection film (SiON + SiO 2 ) 15, the polymer is generated and the etched side surface is not a vertical surface but becomes an inclined surface, and as a result, the first anti-reflection film 13 and 14 and the second anti-reflection film The width dimension of 15 is increased.

다음, 도 1c에 도시된 바와 같이, 감광막 패턴(160)을 마스크로 하여 금배선층(12)을 식각하는데 이 때 베리어막(11)에서 식각을 종료한 후 오버에치하여 하부절연막을 노출시키고, 이로써 이웃하는 금속배선층을 서로 분리시킨다.Next, as shown in FIG. 1C, the gold wiring layer 12 is etched using the photoresist pattern 160 as a mask. At this time, the barrier layer 11 is etched to overetch and expose the lower insulating layer. This separates adjacent metal wiring layers from each other.

식각공정이 완료된 후에는 감광막 패턴(16)을 제거하고 세정공정을 수행한다.After the etching process is completed, the photoresist pattern 16 is removed and a cleaning process is performed.

다음, 도 1d에 도시된 바와 같이, 반도체 기판의 구조물(100) 상부 전면에 층간절연막(17)을 형성하여 이웃하는 금속배선 간 공간을 모두 매립한다. 이 때 반사방지막의 측면이 경사면을 가져 결과적으로 금속배선 간 간격이 목적하는 디자인에서 예상했던 값보다 작아졌기 때문에, 층간절연막이 금속배선 간 공간을 완지 매립하지 못하고 보이드가 형성된다.Next, as shown in FIG. 1D, the interlayer insulating layer 17 is formed on the entire upper surface of the structure 100 of the semiconductor substrate to fill all the spaces between neighboring metal lines. At this time, since the side surface of the antireflection film has an inclined surface, and as a result, the spacing between the metal wirings is smaller than the value expected in the desired design, the interlayer insulating film does not completely fill the space between the metal wirings and voids are formed.

도 2a는 이러한 종래 기술에 따라 제2반사방지막과 제1반사방지막까지 식각한 것을 보여주는 현미경 사진이고, 도 2b은 종래 기술에 따라 제2반사방지막, 제1반사방지막, 및 금속배선층 모두를 식각한 것을 보여주는 현미경사진이다. 이들 사진에서 원으로 그려진 부분에 식각된 측면이 경사진 것을 확인할 수 있다.Figure 2a is a micrograph showing the etching of the second antireflection film and the first antireflection film in accordance with the prior art, Figure 2b is an etching of both the second antireflection film, the first antireflection film, and the metal wiring layer in accordance with the prior art It is a micrograph showing that. In these photographs, it can be seen that the etched side is inclined to the circled portion.

또한, 도 3은 층간절연막 내에 보이드가 형성된 것을 보여주는 현미경 사진으로서, 원으로 그려진 부분에서 보이드를 확인할 수 있다.In addition, FIG. 3 is a micrograph showing that voids are formed in the interlayer insulating film, and the voids may be confirmed in a portion drawn by a circle.

본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 금속배선의 측면 프로파일을 개선하는 것이다.The present invention is to solve the above problems, the object is to improve the side profile of the metal wiring.

본 발명의 다른 목적은 금속배선의 측면을 수직면으로 깨끗하게 식각하는 것이다.Another object of the present invention is to cleanly etch the side of the metal wiring in a vertical plane.

본 발명의 또 다른 목적은 금속배선 간 간격이 목적하는 디자인에 비해 줄어드는 것을 방지하는 것이다.Another object of the present invention is to prevent the spacing between metal lines from being reduced compared to the desired design.

본 발명의 또 다른 목적은 층간절연막을 보이드 없이 매립하는 것이다.It is another object of the present invention to bury the interlayer insulating film without voids.

본 발명의 또 다른 목적은 소자의 전기적 특성을 향상시키고 수율을 향상시키는 것이다.Another object of the present invention is to improve the electrical properties of the device and to improve the yield.

상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는, 반도체 기판 상에 금속배선층을 형성하는 단계; 금속배선층 상에 제1반사방지막 및 제2반사방지막을 순차 형성하는 단계; 제2반사방지막 상에 감광막 패턴을 형성하는 단계; 및 감광막 패턴을 마스크로 하여 제2반사방지막, 제1반사방지막, 및 금속배선층을 각각 서로 다른 식각조건으로 식각하는 단계를 포함하여 반도체 소자를 제조한다.In order to achieve the above object, in the present invention, forming a metal wiring layer on a semiconductor substrate; Sequentially forming a first antireflection film and a second antireflection film on the metal wiring layer; Forming a photoresist pattern on the second anti-reflection film; And etching the second antireflection film, the first antireflection film, and the metal wiring layer under different etching conditions using the photoresist pattern as a mask.

이 때 제2반사방지막은 DUV를 광원으로 사용하는 사진식각 공정에서 사용되 는 반사방지막으로서, SiON 및 SiO2 의 복합물이 300-400Å 두께로 형성된 것이 바람직하다. In this case, the second anti-reflection film is an anti-reflection film used in a photolithography process using DUV as a light source, and a composite of SiON and SiO 2 is preferably formed to have a thickness of 300-400 μs.

제2반사방지막의 식각조건에서는 Ar 및 CHF3를 식각가스로 사용하며, 보다 구체적으로는, 식각챔버 내에 Ar을 40-80sccm, CHF3를 5-15sccm 공급하고 상부전극에 800-1000W를 인가하고 하부전극에 70-120W를 인가하며 압력을 8-10mTorr로 하여 25-35초동안 식각을 진행하는 것이 바람직하다.In the etching conditions of the second anti-reflection film, Ar and CHF 3 are used as an etching gas. More specifically, 40-80 sccm of Ar and 5-15 sccm of CHF 3 are supplied into the etching chamber, and 800-1000 W is applied to the upper electrode. It is preferable to apply 70-120W to the lower electrode and to perform etching for 25-35 seconds at a pressure of 8-10mTorr.

제1반사방지막은 Ti와 TiN의 적층구조인 것이 바람직하고, 이 때 Ti는 50-100Å 두께이고, TiN은 450-800Å 두께인 것이 바람직하다.The first antireflection film is preferably a laminated structure of Ti and TiN, wherein Ti is preferably 50-100 GPa thick and TiN is 450-800 GPa thick.

제1반사방지막의 식각은 식각챔버 내에 Cl2를 50-80sccm, CHF3를 5-15sccm, BCl3를 40-60sccm의 유량으로 공급하고 상부전극에 700-1700W를 인가하고 하부전극에 40-120W를 인가하며 압력을 8-10mTorr로 하여 진행하는 것이 바람직하다.The etching of the first anti-reflection film was performed by supplying Cl 2 at 50-80 sccm, CHF 3 at 5-15 sccm, BCl 3 at 40-60 sccm, applying 700-1700 W to the upper electrode, and 40-120 W to the lower electrode. It is preferable to proceed with the pressure of 8-10 mTorr while applying.

금속배선층은 알루미늄 또는 알루미늄 합금으로 형성된 것이 바람직하며, 금속배선층의 하부에는 베리어막을 더 포함하는 것이 바람직하다.The metal wiring layer is preferably formed of aluminum or an aluminum alloy, and preferably further includes a barrier film under the metal wiring layer.

금속배선층의 식각은 식각챔버 내에 Cl2를 40-80sccm, BCl3를 40-60sccm 공급하고 상부전극에 700-1200W를 인가하고 하부전극에 80-170W를 인가하며 압력을 8-10mTorr로 하여 진행하는 것이 바람직하다.The etching of the metal wiring layer is performed by supplying 40-80sccm of Cl 2 and 40-60sccm of BCl 3 in the etching chamber, applying 700-1200W to the upper electrode, applying 80-170W to the lower electrode, and setting the pressure to 8-10mTorr. It is preferable.

금속배선층의 식각 후 이웃하는 금속배선 간 거리는 0.4-0.5㎛인 것이 바람직하다.After etching the metal wiring layer, the distance between neighboring metal wirings is preferably 0.4-0.5 μm.

이하, 본 발명에 대해 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings for the present invention will be described in detail.

본 발명에서는 금속물질로 이루어진 제1반사방지막(예를 들면 Ti/TiN)과 DUV용 감광막과 조합하여 반사방지 기능이 우수한 제2반사방지막(예를 들면 SiON과 SiO2의 복합물)으로 이루어진 두꺼운 반사방지막을 수직적으로 식각함으로써 금속 라인간의 간격이 점차 감소하는 보다 더 소형화된 소자 제작 시에도 수직적인 금속배선을 형성함으로써 후속 층간절연막 증착시 금속배선 간 공간에 보이드가 발생하는 것을 방지하고자 한다.In the present invention, a thick reflection composed of a first antireflection film (for example, Ti / TiN) made of a metal material and a second antireflection film (for example, a composite of SiON and SiO 2 ) having excellent antireflection in combination with a photosensitive film for DUV. By vertically etching the barrier layer, vertical metal lines are formed even when the device is manufactured to be smaller in size, and voids are generated in the spaces between the metal lines during the subsequent deposition of the interlayer dielectric layer.

도 4a 내지 4e는 본 발명의 일 실시예에 따른 반도체 소자 제조 방법을 그 공정 순서에 따라 도시한 단면도이다.4A through 4E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention according to a process sequence thereof.

먼저, 도 4a에 도시된 바와 같이, 반도체 기판의 구조물(100) 상에 베리어막(110), 금속배선층(120), 제1반사방지막(130, 140), 및 제2반사방지막(150)을 순차 형성한다.First, as shown in FIG. 4A, the barrier film 110, the metallization layer 120, the first antireflection films 130 and 140, and the second antireflection film 150 are formed on the structure 100 of the semiconductor substrate. Form sequentially.

여기서, 반도체 기판의 구조물(100) 최상면에는 하부 절연막이 형성되어 있는 것으로 생각할 수 있다.Here, it can be considered that the lower insulating film is formed on the uppermost surface of the structure 100 of the semiconductor substrate.

베리어막(110)은 금속배선과 하부 절연막과의 접착성 향상 및 금속배선의 확산 등을 목적으로 하여 선택적으로 형성되는 것으로서, 보통 Ti를 형성한다.The barrier film 110 is selectively formed for the purpose of improving adhesion between the metal wiring and the lower insulating film, diffusion of the metal wiring, and the like, and usually forms Ti.

금속배선층(120)은 알루미늄 또는 알루미늄 합금으로 이루어질 수 있으나, 반드시 이들로 한정되는 것은 아니고 도전성이면서 식각이 용이한 물질이면 모두 사용가능하다.The metal wiring layer 120 may be made of aluminum or an aluminum alloy, but is not necessarily limited thereto, and any metal wiring layer 120 may be used as long as it is conductive and easy to etch.

제1반사방지막(130, 140)은 금속물질로 이루어진 통상적인 반사방지막으로서, Ti 및 TiN 적층구조를 많이 사용한다. 이 때 Ti(130)는 50-100Å 두께로, TiN(140)은 450-800Å 두께로 형성하는 것이 바람직하다.The first anti-reflection films 130 and 140 are conventional anti-reflection films made of a metal material, and a plurality of Ti and TiN stacked structures are used. At this time, Ti (130) is preferably 50-100 kPa thick, TiN (140) is preferably formed to 450-800 kPa thick.

제2반사방지막(150)은 DUV를 광원으로 사용하는 사진식각공정에서 요구하는 반사방지막으로서 일반적으로 SiON 및 SiO2의 복합물을 사용하여 300-400Å 두께로형성한다.The second anti-reflection film 150 is an anti-reflection film required in a photolithography process using DUV as a light source, and is generally formed to have a thickness of 300-400 μs using a composite of SiON and SiO 2 .

다음, 제2반사방지막(150) 상에 목적하는 디자인을 가지는 감광막 패턴(160)을 형성한다. 감광막 패턴(160)을 형성할 때에는 전면 도포된 감광막 위에 목적하는 디자인을 가지는 마스크를 둔 상태에서 DUV를 조사하여 노광한 후, 현상한다.Next, a photoresist pattern 160 having a desired design is formed on the second antireflection film 150. When the photoresist pattern 160 is formed, the photoresist film is exposed to light after being irradiated with DUV in a state where a mask having a desired design is placed on the entire photoresist film.

다음, 도 4b에 도시된 바와 같이, 감광막 패턴(160)을 마스크로 하고 Ar 및 CHF3를 식각가스로 사용하는 식각조건에서 제2반사방지막(150)을 식각한다. Next, as shown in FIG. 4B, the second anti-reflection film 150 is etched under the etching conditions using the photoresist pattern 160 as a mask and Ar and CHF 3 as an etching gas.

이 때 식각 과정에서 폴리머가 발생되지 않도록 하는 것이 중요하며, 이를 위해 Ar 및 CHF3를 식각가스로 사용하는 것이다.At this time, it is important to prevent the polymer from being generated during the etching process. For this, Ar and CHF 3 are used as the etching gas.

제2반사방지막(150)의 식각조건을 좀 더 구체적으로 설명하면, 식각챔버 내에 Ar을 40-80sccm, CHF3를 5-15sccm 의 유량으로 공급하고 상부전극에 800-1000W를 인가하고 하부전극에 70-120W를 인가하며, 압력을 8-10mTorr로 한 상태에서 25-35초동안 진행하는 것이다.The etching conditions of the second anti-reflection film 150 will be described in more detail. In the etching chamber, Ar is supplied at a flow rate of 40-80 sccm and CHF 3 at a flow rate of 5-15 sccm, 800-1000 W is applied to the upper electrode, and the lower electrode is applied to the lower electrode. Apply 70-120W and run for 25-35 seconds with the pressure at 8-10mTorr.

상술한 식각조건에서 제2반사방지막(150)을 식각하면 폴리머가 발생하지 않아 식각된 제2반사방지막(150)의 측면이 수직면이 된다.If the second anti-reflection film 150 is etched under the above etching conditions, no polymer is generated, and thus the side surface of the etched second anti-reflection film 150 becomes a vertical plane.

다음, 도 4c에 도시된 바와 같이, 감광막 패턴(160)을 마스크로 하고 앞의 제2반사방지막(150)의 식각조건과는 다른 조건으로 이번에는 제1반사방지막(140, 130)을 식각한다. Next, as shown in FIG. 4C, the photoresist pattern 160 is used as a mask, and the first antireflection films 140 and 130 are etched this time under conditions different from those of the previous second antireflection film 150. .

제1반사방지막(140, 130)의 식각은 식각챔버 내에 Cl2를 50-80sccm, CHF3를 5-15sccm, BCl3를 40-60sccm의 유량으로 공급하고 상부전극에 700-1700W를 인가하고 하부전극에 40-120W를 인가하며 압력을 8-10mTorr로 한 상태에서 진행하는 것이 바람직하다.The etching of the first anti-reflection films 140 and 130 is performed by supplying Cl 2 at 50-80 sccm, CHF 3 at 5-15 sccm, BCl 3 at 40-60 sccm, and applying 700-1700 W to the upper electrode. It is preferable to apply 40-120W to the electrode and to proceed with the pressure of 8-10 mTorr.

상술한 식각조건에서 제1반사방지막(140, 130)을 식각한 결과, 제1반사방지막(140, 130)의 측면 역시 수직면이다.As a result of etching the first antireflection films 140 and 130 under the above etching conditions, the side surfaces of the first antireflection films 140 and 130 are also vertical.

다음, 도 4d에 도시된 바와 같이, 감광막 패턴(160)을 마스크로 하고 앞의 제2반사방지막(150) 및 제1반사방지막(140, 130)의 식각조건과는 또 다른 조건으로 이번에는 금속배선층(120)을 식각하는데 이 때 베리어막(110)에서 식각을 종료한 후 오버에치하여 하부절연막을 노출시키고, 이로써 이웃하는 금속배선층을 서로 분리시킨다.Next, as shown in FIG. 4D, the photoresist pattern 160 is used as a mask, and this time is different from the etching conditions of the second antireflection film 150 and the first antireflection films 140 and 130. At this time, the barrier layer 110 is etched, and the barrier layer 110 is etched and then overetched to expose the lower insulating layer, thereby separating neighboring metal interconnect layers from each other.

식각공정이 완료된 후에는 감광막 패턴(160)을 제거하고 세정공정을 수행한다.After the etching process is completed, the photoresist pattern 160 is removed and a cleaning process is performed.

이와 같이 본 발명에서 제시한 각각의 식각조건에 따라 제2반사방지막, 제1반사방지막, 및 금속배선층을 각각 식각하면 이들의 식각면이 모두 수직면으로 깨끗하게 식각되므로, 목적하는 디자인에 비해 분리된 금속배선 간 간격이 더 좁아지 는 일이 없다.As described above, when the second antireflection film, the first antireflection film, and the metal wiring layer are etched according to the etching conditions of the present invention, all of the etching surfaces are etched cleanly in the vertical plane, so that the metal is separated from the desired design. There is no narrower gap between wirings.

다음, 도 4e에 도시된 바와 같이, 반도체 기판의 구조물(100) 상부 전면에 층간절연막(170)을 형성하여 이웃하는 금속배선 간 공간을 모두 매립한다. 이 때 금속배선 간 간격이 목적하는 디자인에서 예상했던 값을 그대로 유지하고 있으므로 보이드가 없이 금속배선 간 공간을 완전히 매립할 수 있다.Next, as shown in FIG. 4E, the interlayer insulating layer 170 is formed on the entire upper surface of the structure 100 of the semiconductor substrate to fill all the spaces between neighboring metal wirings. At this time, the spacing between the metal lines maintains the value expected in the desired design, so that the space between the metal lines can be completely filled without voids.

도 5는 본 발명에 따라 제2반사방지막과 제1반사방지막까지 식각한 것을 보여주는 현미경 사진이고, 도 6은 본 발명에 따라 제2반사방지막, 제1반사방지막, 및 금속배선층 모두를 식각한 것을 보여주는 현미경사진이다.5 is a micrograph showing etching to the second antireflection film and the first antireflection film in accordance with the present invention, Figure 6 is an etching of both the second antireflection film, the first antireflection film, and the metal wiring layer in accordance with the present invention. Showing micrograph.

이들 사진에서 원으로 그려진 부분에 식각된 측면이 수직면인 것을 확인할 수 있다. In these photographs, it can be seen that the side etched in the circled portion is a vertical plane.

또한, 도 6은 본 발명에 따라 층간절연막이 보이드 없이 형성된 것을 보여주는 현미경 사진이다.6 is a micrograph showing that an interlayer insulating film is formed without voids according to the present invention.

상술한 바와 같이, 본 발명에서는 제2반사방지막을 특정 식각조건에서 식각하여 폴리머 발생을 막고 따라서 금속배선 및 반사방지막의 식각된 측면이 수직면을 갖도록 하는 효과가 있다.As described above, in the present invention, the second anti-reflection film is etched under specific etching conditions to prevent polymer generation, and thus the etched side surfaces of the metal wiring and the anti-reflection film have a vertical plane.

따라서, 금속배선 간 간격이 목적하는 디자인에 비해 줄어드는 것을 방지하고 이로써 층간절연막을 보이드 없이 매립하는 효과가 있다.Therefore, the gap between the metal wirings is prevented from being reduced as compared with the desired design, thereby having the effect of filling the interlayer insulating film without voids.

이로 인해 소자의 전기적 특성이 향상되고 수율이 향상되는 효과가 있다.This improves the electrical characteristics of the device and has the effect of improving the yield.

Claims (8)

반도체 기판의 구조물 상에 금속배선층을 형성하는 단계;Forming a metallization layer on the structure of the semiconductor substrate; 상기 금속배선층 상에 Ti와 TiN 적층구조의 제1반사방지막과 SiON 및SiO2의 복합물로 형성된 제2반사방지막을 순차 형성하는 단계;Sequentially forming a second anti-reflection film formed of a composite of Ti and TiN stacked structures and a composite of SiON and SiO 2 on the metal wiring layer; 상기 제2반사방지막 상에 감광막 패턴을 형성하는 단계; 및Forming a photoresist pattern on the second anti-reflection film; And 상기 감광막 패턴을 마스크로 하여 Ar 및 CHF3을 식각 가스로 상기 제2반사방지막을 식각하는 단계, Etching the second anti-reflection film by using Ar and CHF 3 as an etching gas using the photoresist pattern as a mask; 상기 감광막 패턴을 마스크로 하여 Cl2, CHF3 및BCl3를 식각가스로 상기 제1반사방지막을 식각하는 단계; 및Etching the first anti-reflection film by using Cl 2, CHF 3 and BCl 3 as an etching gas using the photoresist pattern as a mask; And 상기 감광막 패턴을 마스크로 하여 Cl2 및 BCl3를 식각가스로 상기 금속배선층을 식각하는 단계;Etching the metallization layer by using Cl2 and BCl3 as an etching gas using the photoresist pattern as a mask; 를 포함하는 반도체 소자 제조 방법.Semiconductor device manufacturing method comprising a. 제 1 항에 있어서,The method of claim 1, 상기 제2반사방지막은 300-400Å 두께로 형성된 반도체 소자 제조 방법.The second anti-reflection film is a semiconductor device manufacturing method formed to a thickness of 300-400Å. 삭제delete 제 1 항에 있어서,The method of claim 1, 상기 제2반사방지막의 식각은 식각챔버 내에 Ar을 40-80sccm, CHF3를 5-15sccm 공급하고 상부전극에 800-1000W를 인가하고 하부전극에 70-120W를 인가하며 압력을 8-10mTorr로 하여 25-35초동안 진행하는 반도체 소자 제조 방법.The second anti-reflection film is etched by supplying 40-80sccm of Ar and 5-15sccm of CHF 3 in the etching chamber, applying 800-1000W to the upper electrode, applying 70-120W to the lower electrode, and setting the pressure to 8-10mTorr. A method for manufacturing a semiconductor device that lasts 25-35 seconds. 제 1 항에 있어서,The method of claim 1, 상기 제1반사방지막에서 상기 Ti는 50-100Å 두께로 형성하며 상기 TiN은 450-800Å 두께로 형성하는 반도체 소자 제조 방법.In the first anti-reflection film, the Ti is formed in a thickness of 50-100 Å and the TiN is formed in a 450-800 Å thickness. 제 1 항에 있어서,The method of claim 1, 상기 제1반사방지막의 식각은 식각챔버 내에 Cl2를 50-80sccm, CHF3를 5-15sccm, BCl3를 40-60sccm 공급하고 상부전극에 700-1700W를 인가하고 하부전극에 40-120W를 인가하며 압력을 8-10mTorr로 하여 진행하는 반도체 소자 제조 방법. The first anti-reflection film is etched by supplying Cl 2 to 50-80sccm, CHF 3 to 5-15sccm, BCl 3 to 40-60sccm and applying 700-1700W to the upper electrode and 40-120W to the lower electrode. And proceed with a pressure of 8-10mTorr. 제 1 항에 있어서,The method of claim 1, 상기 금속배선층은 알루미늄 또는 알루미늄 합금으로 형성된 반도체 소자 제조 방법.The metal wiring layer is a semiconductor device manufacturing method formed of aluminum or aluminum alloy. 제 1 항에 있어서,The method of claim 1, 상기 금속배선층의 식각은 식각챔버 내에 Cl2를 40-80sccm, BCl3를 40- 60sccm 공급하고 상부전극에 700-1200W를 인가하고 하부전극에 80-170W를 인가하며 압력을 8-10mTorr로 하여 진행하는 반도체 소자 제조 방법.The etching of the metallization layer is performed by supplying 40-80sccm of Cl 2 and 40-60sccm of BCl 3 in the etching chamber, applying 700-1200W to the upper electrode, applying 80-170W to the lower electrode, and setting the pressure to 8-10mTorr. A semiconductor device manufacturing method.
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