KR100543201B1 - Capacitor Manufacturing Method of Semiconductor Memory Device - Google Patents
Capacitor Manufacturing Method of Semiconductor Memory Device Download PDFInfo
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- KR100543201B1 KR100543201B1 KR1019980042793A KR19980042793A KR100543201B1 KR 100543201 B1 KR100543201 B1 KR 100543201B1 KR 1019980042793 A KR1019980042793 A KR 1019980042793A KR 19980042793 A KR19980042793 A KR 19980042793A KR 100543201 B1 KR100543201 B1 KR 100543201B1
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- capacitor
- forming
- oxide film
- cell region
- polysilicon
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- 239000003990 capacitor Substances 0.000 title claims abstract description 105
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 36
- 229920005591 polysilicon Polymers 0.000 claims abstract description 36
- 230000002093 peripheral effect Effects 0.000 claims abstract description 24
- 238000005498 polishing Methods 0.000 claims abstract description 24
- 239000000126 substance Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 150000004767 nitrides Chemical class 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 8
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 6
- 125000006850 spacer group Chemical class 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- -1 spacer nitride Chemical class 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
- H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
반도체 메모리소자의 커패시터 제조방법에 있어서, 커패시터 산화막의 두께를 최종 남기고자 하는 두께와 셀과 주변회로와의 단차의 합보다 두껍게 증착한 다음, 커패시터 하부전극으로 사용될 폴리실리콘을 증착하고 화학적 기계적 연마를 이용하여 폴리실리콘과 커패시터 형성용 산화막의 연마 속도가 동일한 조건에서 동시에 연마하여 필요 없는 폴리실리콘 부분을 제거함과 동시에 평탄화를 구현한다.In the capacitor manufacturing method of a semiconductor memory device, the thickness of the capacitor oxide film is deposited thicker than the sum of the thickness of the final thickness and the step between the cell and the peripheral circuit, and then the polysilicon to be used as the capacitor lower electrode is deposited and chemical mechanical polishing is performed. By using the polishing rate of the polysilicon and the oxide film for forming the capacitor at the same time at the same time polishing to remove the unnecessary polysilicon portion and at the same time implements the planarization.
Description
본 발명은 반도체 메모리소자의 커패시터 형성방법에 관한 것으로, 특히 화학적 기계적 연마를 이용하여 커패시터 하부전극 형성용 폴리실리콘과 커패시터 형성용 산화막의 연마 속도가 동일한 조건에서 동시에 연마하여 필요 없는 폴리실리콘 부분을 제거함과 동시에 평탄화를 구현하는 반도체 소자의 커패시터 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a capacitor of a semiconductor memory device. In particular, by using mechanical mechanical polishing, the polysilicon for forming a lower electrode of a capacitor and an oxide film for forming a capacitor are simultaneously polished under the same polishing rate to remove unnecessary polysilicon portions. In addition, the present invention relates to a method of forming a capacitor of a semiconductor device for implementing planarization.
종래기술에 의한 반도체소자의 커패시터를 형성방법을 도 1a 및 도 1b를 참조하여 설명하면 다음과 같다. 먼저, 도 1a를 참조하면, 반도체기판 소정영역에 게이트(11) 및 스페이서 산화막(12)을 형성하고, 그 전면에 제1평탄화막(13)을 형성한 후 이를 선택적으로 식각하여 비트라인용 콘택홀을 형성한 다음, 비트라인 형성용 도전층과 마스크 산화막(15)을 차례로 형성하고 소정패턴으로 패터닝하여 비트라인(14)을 형성한다. 이어서 기판 전면에 식각정지막(16)으로서 질화막을 형성하고, 이위에 커패시터를 형성하기 위한 산화막(17)을 증착한 후 셀영역(A)상의 산화막(17)을 소정패턴으로 패터닝하여 커패시터가 형성될 부분을 정의한다. 계속해서 상기 산화막(17)상에 커패시터 하부전극용 폴리실리콘(18)을 증착한 후, 상기 커패시터가 형성될 부분의 갭을 매립하기 위한 산화막(19)을 기판 전면에 형성한다.A method of forming a capacitor of a semiconductor device according to the prior art will be described with reference to FIGS. 1A and 1B. First, referring to FIG. 1A, a gate 11 and a spacer oxide layer 12 are formed in a predetermined region of a semiconductor substrate, and a first planarization layer 13 is formed on the entire surface thereof, and then selectively etched to form a contact for a bit line. After the hole is formed, the bit line forming conductive layer and the mask oxide film 15 are sequentially formed and patterned in a predetermined pattern to form the bit line 14. Subsequently, a nitride film is formed as an etch stop film 16 on the entire surface of the substrate, and an oxide film 17 for forming a capacitor is deposited thereon, and then the oxide film 17 on the cell region A is patterned in a predetermined pattern to form a capacitor. Define the part to be Subsequently, after depositing the polysilicon 18 for the capacitor lower electrode on the oxide film 17, an oxide film 19 for filling the gap of the portion where the capacitor is to be formed is formed on the entire substrate.
다음에 도 1b에 나타낸 바와 같이 전면 건식 식각에 의해 산화막(19)을 식각하고, 다시 전면 건식 식각에 의해 커패시터 하부 전극으로 사용될 부분만 남기고 폴리실리콘층(18)을 모두 제거한다. 도시한 바와 같이 셀어레이(A) 상부에서는 폴리실리콘층(18)이 원하는 부위에서 완전히 제거되었으나 주변회로영역(B)에는 갭매립용 산화막(19')이 남아 있다. 이는 주변회로영역(B)의 비트라인(14)간 간격이 커패시터 형성용 산화막(17), 폴리실리콘층(18), 갭매립용 산화막(19)의 전체 두께의 2배보다 약간 작을 경우, 그곳에 증착되는 갭매립용 산화막(19)의 두께(T12)가 다른 부위의 두께(T11)보다 두껍게 되는 경우에 발생한다. 이와 같은 상황에서 전면 건식 식각에 의해 커패시터 하부전극 형성용 폴리실리콘(18)을 부분적으로 제거하고자 할 때 갭매립용 산화막(18)이 식각 방지막 역할을 하게 되어 원하지 않는 폴리실리콘 부분이 남게 되고, 후속공정인 커패시터 형성용 산화막을 습식식각에 의해 제거할때 결함(particle)원으로 작용하게 된다. 만일 주변 회로의 갭매립용 산화막을 완전히 제거하고자 과도한 식각을 할 경우에는 셀어레이 영역의 커패시터 형성부위에서 갭매립용 산화막(18)이 식각되면서 보이드(void)가 노출되고 측면 산화막이 식각된다. 이와 같은 상황에서 전면 건식 식각에 의해 커패시터 하부 전극을 식각하게 되면 측면의 폴리실리콘이 제거되어 결국 커패시터의 높이가 감소하고 커패시터 용량이 감소하는 문제가 발생한다.Next, as shown in FIG. 1B, the oxide film 19 is etched by dry etching on the entire surface, and the polysilicon layer 18 is removed while leaving only the portion to be used as the capacitor lower electrode by dry etching on the entire surface. As shown in the figure, the polysilicon layer 18 is completely removed from the desired region on the cell array A, but the gap filling oxide film 19 'remains in the peripheral circuit region B. This is because when the distance between the bit lines 14 in the peripheral circuit region B is slightly smaller than twice the total thickness of the capacitor forming oxide film 17, the polysilicon layer 18, and the gap filling oxide film 19, This occurs when the thickness T12 of the gap-filling oxide film 19 to be deposited becomes thicker than the thickness T11 of other portions. In such a situation, when the polysilicon 18 for forming the capacitor lower electrode is partially removed by dry etching, the gap filling oxide film 18 serves as an etch stop layer, thereby leaving an undesired polysilicon portion. When the oxide film for capacitor formation, which is a process, is removed by wet etching, it acts as a particle source. If excessive etching is performed to completely remove the gap filling oxide film of the peripheral circuit, the gap filling oxide film 18 is etched at the capacitor formation portion of the cell array region to expose voids and the side oxide film is etched. In such a situation, when the lower electrode of the capacitor is etched by dry etching, the polysilicon on the side is removed, resulting in a decrease in the height of the capacitor and a decrease in the capacitor capacity.
본 발명은 상술한 문제를 해결하기 위한 것으로, 커패시터 산화막의 두께를 최종 남기고자 하는 두께와 셀과 주변회로와의 단차의 합보다 두껍게 증착한 다음, 커패시터 하부전극으로 사용될 폴리실리콘을 증착하고 화학적 기계적 연마를 이용하여 폴리실리콘과 커패시터 형성용 산화막의 연마 속도가 동일한 조건에서 동시에 연마하여 필요 없는 폴리실리콘 부분을 제거함과 동시에 평탄화를 구현하는 반도체 소자의 커패시터 형성방법을 제공하는 것을 그 목적으로 한다.The present invention is to solve the above-described problems, the thickness of the capacitor oxide film is deposited thicker than the sum of the thickness of the final step and the difference between the cell and the peripheral circuit, and then deposited polysilicon to be used as the capacitor lower electrode and chemical mechanical It is an object of the present invention to provide a method for forming a capacitor of a semiconductor device in which polysilicon and a capacitor forming oxide film are simultaneously polished under the same polishing rate to remove unnecessary polysilicon portions while simultaneously polishing.
상기 목적을 달성하기 위한 본 발명의 반도체소자의 커패시터 형성방법은 셀영역과 주변회로영역을 포함하는 반도체기판 전면에 커패시터 형성용 산화막으로서 P가 1-4wt%인 저농도 오존테오스계 산화막을 형성하는 단계; 상기 커패시터 형성용 산화막을 선택적으로 제거하여 커패시터가 형성될 공간을 만드는 단계; 상기 커패시터 형성 공간을 포함한 상기 반도체 기판 전면에 커패시터 하부전극 형성용 폴리실리콘을 증착하는 단계; 화학적 기계적 연마를 이용하여 커패시터 하부전극으로 사용하지 않을 부위의 상기 폴리실리콘과 커패시터 형성용 산화막을 동시에 제거하여 상기 커패시터 형성공간내에 커패시터 하부전극을 형성하는 단계; 및 상기 셀영역상에 형성된 커패시터 형성용 산화막 부분만을 선택적으로 제거하는 단계를 포함하여 구성된다.The capacitor forming method of the semiconductor device of the present invention for achieving the above object is a step of forming a low concentration ozone-based oxide film having a P concentration of 1-4wt% as an oxide film for forming a capacitor on the front surface of the semiconductor substrate including a cell region and a peripheral circuit region. ; Selectively removing the capacitor forming oxide film to form a space where a capacitor is to be formed; Depositing polysilicon for forming a capacitor lower electrode on an entire surface of the semiconductor substrate including the capacitor formation space; Forming a capacitor lower electrode in the capacitor formation space by simultaneously removing the polysilicon and the capacitor forming oxide film at a portion not to be used as the capacitor lower electrode by chemical mechanical polishing; And selectively removing only a portion of the oxide film for forming a capacitor formed on the cell region.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2a 내지 도 2d에 본 발명에 의한 반도체소자의 커패시터 형성방법을 공정순서에 따라 도시하였다.2A to 2D illustrate a method of forming a capacitor of a semiconductor device according to the present invention in accordance with a process sequence.
먼저, 도 2a를 참조하면, 반도체기판 소정영역에 게이트(21) 및 스페이서 산화막(22)을 형성하고, 그 전면에 제1평탄화막(23)을 형성한 후 이를 선택적으로 식각하여 비트라인용 콘택홀을 형성한 다음, 비트라인 형성용 도전층과 마스크 산화막(25)을 차례로 형성하고 소정패턴으로 패터닝하여 비트라인(14)을 형성한다. 이어서 기판 전면에 식각정지막(26)으로서 질화막을 형성한 후, 주변회로영역(B)의 질화막만을 선택적으로 제거하여 후속 공정인 금속 콘택 형성이 용이하도록 한다. 주변회로영역에서 질화막(26)이 건식 식각될 때 스페이서 질화막(26')이 남게되어 커패시터 산화막의 갭 매립을 향상시키는 효과도 있다. 상기 질화막은 500-1000Å 두께로 형성하는 것이 바람직하며, 응력을 완화시키기 위하여 질화막 하부에 100Å 정도의 산화막을 형성할 수도 있다.First, referring to FIG. 2A, a gate 21 and a spacer oxide layer 22 are formed on a predetermined region of a semiconductor substrate, and a first planarization layer 23 is formed on the entire surface thereof, and then selectively etched to form a contact for a bit line. After the hole is formed, the bit line forming conductive layer and the mask oxide film 25 are sequentially formed and patterned in a predetermined pattern to form the bit line 14. Subsequently, after forming the nitride film as the etch stop layer 26 on the entire surface of the substrate, only the nitride film of the peripheral circuit region (B) is selectively removed to facilitate metal contact formation, which is a subsequent process. When the nitride layer 26 is dry etched in the peripheral circuit region, the spacer nitride layer 26 ′ remains to improve the gap filling of the capacitor oxide layer. The nitride film is preferably formed to have a thickness of 500-1000 GPa, and an oxide film of about 100 GPa may be formed under the nitride film to relieve stress.
다음에 커패시터 형성용 산화막(27)을 기판 전면에 형성하는바, 그 두께를 최종적으로 남기고자 하는 두께와 비트 라인의 높이를 합한 두께 이상(T21)으로 증착한 다음, 이 산화막(27)을 패터닝하여 커패시터가 형성될 영역을 만들고 커패시터 하부전극 형성용 폴리실리콘(28)을 기판 전면에 증착한다. 상기 커패시터 형성용 산화막(27)으로는 P(phosphorus)가 1-4wt% 인 저농도 오존테오스계 산화막을 사용하는 것이 바람직하다.Next, an oxide film 27 for forming a capacitor is formed on the entire surface of the substrate. The oxide film 27 is deposited to a thickness T21 that is equal to the thickness of the final thickness and the height of the bit line, and then the oxide film 27 is patterned. By making a region where the capacitor is to be formed, polysilicon 28 for capacitor lower electrode formation is deposited on the entire surface of the substrate. As the capacitor forming oxide film 27, it is preferable to use a low concentration ozone-based oxide film having a P (phosphorus) of 1-4 wt%.
도 2b를 참조하면, 상기 구조에서 화학적 기계적 연마를 이용하여 커패시터 하부전극으로 사용되지 않는 부위의 폴리실리콘(28)과 커패시터 형성용 산화막(27)을 동시에 제거한다. 이때 중요한 변수는 폴리실리콘과 커패시터 산화막의 연마 속도를 동일하게 설정하는 것으로, 연마 조건이나 커패시터 산화막으로 사용되는 오존테오스계 PSG막의 P 농도를 변화시킴으로 인해 즉 오존테오스계 PSG막의 P(phosphorus)를 1-4wt% 인 조건으로 함에 따라 폴리실리콘과 커패시터 산화막의 연마 속도를 동일하게 설정하는 적정조건을 얻을 수 있다. 이와 같은 방법을 사용하면 필요없는 폴리실리콘 제거와 동시에 셀영역(A)과 주변회로영역(B)간의 단차를 감소 시킬 수 있게 된다.Referring to FIG. 2B, the polysilicon 28 and the oxide forming layer 27 for forming the capacitor are simultaneously removed using the chemical mechanical polishing in the above structure. At this time, an important variable is to set the polishing rate of polysilicon and the capacitor oxide film to be the same. The P (phosphorus) of the ozone theose PSG film is changed to 1 by changing the polishing conditions or the P concentration of the ozone-based PSG film used as the capacitor oxide film. By setting it as -4wt%, appropriate conditions for setting the polishing rate of polysilicon and the capacitor oxide film to the same can be obtained. Using this method, it is possible to reduce the step difference between the cell region A and the peripheral circuit region B while removing unnecessary polysilicon.
도 2c를 참조하면, 주변회로영역(B)을 마스크(도시하지 않음)로 덮고, 셀영역(A)의 커패시터 형성용 산화막만을 HF나 BOE를 이용한 전면 습식식각에 의해 선택적으로 제거한 후, 계속해서 셀영역의 질화막을 전면 건식식각에 의해 제거한다. 이때, 주변회로영역과 마찬가지로 셀영역에서도 비트라인(25) 측면에 질화막스페이서(26')가 생성된다.Referring to FIG. 2C, the peripheral circuit region B is covered with a mask (not shown), and only the oxide formation film for forming the capacitor of the cell region A is selectively removed by wet etching using HF or BOE, followed by continued removal. The nitride film of the cell region is removed by dry etching. In this case, the nitride film spacer 26 ′ is formed on the side of the bit line 25 in the cell region as in the peripheral circuit region.
도 2d를 참조하면, 커패시터 용량 증대를 위해 커패시터 표면적을 증가시키기 위하여 선택 증착형 준안정 폴리실리콘(MPS;metastable polysilicon)(29)을 커패시터 하부전극 표면에 증착하고, 산화막/질화막 또는 탄탈륨산화막 같은 커패시터 유전막(30)을 상기 준안정 폴리실리콘층(29)상에 증착한 후, 그 전면에 커패시터 상부전극 형성용 도전층(31)을 형성한 다음, 마스크 및 식각작업을 통해 주변회로영역의 커패시터 상부전극 형성용 도전층을 제거함으로써 셀영역(A)상에 커패시터를 완성한다. 본 발명은 상술한 바와 같이 기존의 방법에 비해 셀과 주변회로간 단차를 크게 낮출수 있다는 장점이 있다.Referring to FIG. 2D, a selective deposition metastable polysilicon (MPS) 29 is deposited on the surface of the capacitor lower electrode to increase the capacitor surface area to increase the capacitor capacity, and a capacitor such as an oxide film / nitride film or tantalum oxide film. After depositing the dielectric film 30 on the metastable polysilicon layer 29, the conductive layer 31 for forming a capacitor upper electrode is formed on the front surface thereof, and then the upper part of the capacitor in the peripheral circuit region through masking and etching. The capacitor is completed on the cell region A by removing the electrode forming conductive layer. The present invention has the advantage that the step between the cell and the peripheral circuit can be significantly lowered as described above.
본 발명에 의하면, 커패시터 형성용 산화막을 최종적으로 남기고자 하는 두께보다 두껍게 증착한 다음 커패시터 하부전극 형성을 위한 폴리실리콘을 증착하고 화학적 기계적 연마에 의해 커패시터가 형성될 부위만 폴리실리콘을 남기고 나머지를 제거하면 주변회로영역에서 잔존하는 폴리실리콘이 없게 되고, 후속 공정에서 주변회로 부위의 커패시터 형성용 산화막을 제거하지 않고 남겨두게 되면 셀과 주변회로간 단차를 줄일 수 있는 장점이 있어 후속 공정에서 평탄화를 쉽게 할 수 있게 된다.According to the present invention, the oxide film for forming a capacitor is deposited thicker than the thickness to be finally left, and then polysilicon is deposited for forming a capacitor lower electrode, and the polysilicon is removed leaving only the portion where the capacitor is formed by chemical mechanical polishing. If there is no remaining polysilicon in the peripheral circuit area, and if it is left without removing the capacitor forming oxide film in the peripheral circuit part in the subsequent process, there is an advantage that the step between the cell and the peripheral circuit can be reduced, so that the planarization can be easily performed in the subsequent process. You can do it.
도 1a 및 도 1b는 종래기술에 의한 반도체 메모리소자의 커패시터 제조방법을 도시한 공정순서도,1A and 1B are process flowcharts illustrating a method of manufacturing a capacitor of a semiconductor memory device according to the prior art;
도 2a 내지 도 2d는 본 발명에 의한 반도체 메모리소자의 커패시터 제조방법을 도시한 공정순서도.2A to 2D are process flowcharts showing a capacitor manufacturing method of a semiconductor memory device according to the present invention;
*도면의 주요부분에 대한 부호의 설명** Explanation of symbols for main parts of drawings *
11,21 ; 게이트 12,22 ; 스페이서 산화막11,21; Gate 12,22; Spacer oxide
13,23 ; 제 1평탄화막 14,24 ; 비트 라인13,23; First planarization film 14,24; Bit line
15,25 ; 마스크 산화막 16,26 ; 식각 정지용 질화막15,25; Mask oxide films 16, 26; Nitride for Etch Stopping
17,27 ; 커패시터 형성용 산화막 18,28 ; 커패시터 하부 전극17,27; Oxide films for forming capacitors 18,28; Capacitor Bottom Electrode
19 ; 갭매립용 산화막 29 ; 준안정폴리실리콘층19; An oxide film for gap filling 29; Metastable polysilicon layer
30 ; 커패시터 유전막 31 ; 커패시터 상부전극30; Capacitor dielectric film 31; Capacitor Upper Electrode
19' ; 식각후의 잔존 갭매립용 산화막19 '; Residual gap buried oxide film after etching
26' ; 식각후의 스페이서 질화막 A ; DRAM 셀영역26 '; Spacer nitride film A after etching; DRAM cell area
B ; DRAM 주변회로영역 V11 ; 보이드B; DRAM peripheral circuit area V11; Boyd
T11,T12 ; 갭매립용 산화막 두께 (T11 < T 12)T11, T12; Oxide thickness for gap filling (T11 <T 12)
T21,T22 ; 커패시터 형성용 산화막 두께 (T21 > T22)T21, T22; Oxide thickness for capacitor formation (T21> T22)
Claims (15)
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| JPH05243518A (en) * | 1992-02-27 | 1993-09-21 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| KR960003864A (en) * | 1994-07-19 | 1996-02-23 | 한승준 | Vehicle Cam Using Metal Base Composite |
| JPH10150168A (en) * | 1996-11-14 | 1998-06-02 | Texas Instr Inc <Ti> | Manufacture of storage integrated circuit |
| KR100304946B1 (en) * | 1994-07-08 | 2001-11-30 | 김영환 | Method for manufacturing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH05243518A (en) * | 1992-02-27 | 1993-09-21 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| KR100304946B1 (en) * | 1994-07-08 | 2001-11-30 | 김영환 | Method for manufacturing semiconductor device |
| KR960003864A (en) * | 1994-07-19 | 1996-02-23 | 한승준 | Vehicle Cam Using Metal Base Composite |
| JPH10150168A (en) * | 1996-11-14 | 1998-06-02 | Texas Instr Inc <Ti> | Manufacture of storage integrated circuit |
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