KR100538293B1 - Method of manufacturing flat drive liquid crystal display - Google Patents
Method of manufacturing flat drive liquid crystal display Download PDFInfo
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- KR100538293B1 KR100538293B1 KR1019980011775A KR19980011775A KR100538293B1 KR 100538293 B1 KR100538293 B1 KR 100538293B1 KR 1019980011775 A KR1019980011775 A KR 1019980011775A KR 19980011775 A KR19980011775 A KR 19980011775A KR 100538293 B1 KR100538293 B1 KR 100538293B1
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- 239000004973 liquid crystal related substance Substances 0.000 title claims description 29
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 46
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims description 76
- 238000000059 patterning Methods 0.000 claims description 25
- MGRWKWACZDFZJT-UHFFFAOYSA-N molybdenum tungsten Chemical compound [Mo].[W] MGRWKWACZDFZJT-UHFFFAOYSA-N 0.000 claims description 21
- 230000001681 protective effect Effects 0.000 claims description 20
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- 239000011651 chromium Substances 0.000 claims description 6
- 239000002356 single layer Substances 0.000 claims description 6
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052804 chromium Inorganic materials 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 239000010408 film Substances 0.000 description 37
- 238000000034 method Methods 0.000 description 11
- 230000005684 electric field Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13458—Terminal pads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
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- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
투명 절연 기판 위에 제1 금속막을 증착하고 제1 마스크를 이용하여 패터닝하여 게이트선, 게이트 전극 및 게이트 패드 등의 게이트 배선과 공통 전극선 및 공통 전극 등의 공통 전극 배선을 형성하고, 게이트 절연막, 비정질 규소층, 도핑된 비정질 규소층, 제2 금속막을 차례로 적층한 다음, 제2 마스크를 이용하여 패터닝하여 데이터선, 소스 및 드레인 전극, 데이터 패드 등의 데이터 배선과 화소 전극선 및 화소 전극 등을 형성한다. 그 후, 데이터 배선 및 화소 전극 배선을 마스크로 사용하여 비정질 규소층 및 도핑된 비정질 규소층을 패터닝한다.A first metal film is deposited on the transparent insulating substrate and patterned using a first mask to form gate wirings such as gate lines, gate electrodes, and gate pads, and common electrode wirings such as common electrode lines and common electrodes, and to form gate insulating films and amorphous silicon. A layer, a doped amorphous silicon layer, and a second metal film are sequentially stacked, and then patterned using a second mask to form data wires such as data lines, source and drain electrodes, and data pads, pixel electrode lines, and pixel electrodes. Thereafter, the amorphous silicon layer and the doped amorphous silicon layer are patterned using the data wiring and the pixel electrode wiring as masks.
Description
본 발명은 평면 구동 방식 액정 표시 장치의 제조 방법에 관한 것으로서, 특히 3매 마스크(mask)를 이용한 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing method of a flat drive type liquid crystal display device, and more particularly to a manufacturing method using three masks.
일반적으로 액정 표시 장치는 두 장의 기판 사이에 액정을 주입하고, 여기에 가하는 전장의 세기를 조절하여 광 투과량을 조절하는 구조로 되어 있다.In general, a liquid crystal display device has a structure in which a liquid crystal is injected between two substrates, and the amount of light transmitted is controlled by adjusting the intensity of the electric field applied thereto.
두 기판 사이에서 액정 분자의 장축의 방향이 연속적으로 변화하는 구조를 가지고 있는 비틀린 네마틱(twisted nematic:TN) 방식의 액정 표시 장치에서는, 노멀리 블랙 모드(normally black mode)인 경우 전기장이 인가되지 않은 상태에서 입사한 빛이 완전히 차단되지 않기 때문에 대비비가 좋지 않다.In a twisted nematic (TN) type liquid crystal display having a structure in which the direction of the major axis of the liquid crystal molecules is continuously changed between two substrates, an electric field is not applied in the normally black mode. The contrast ratio is not good because the incident light is not completely blocked.
이와는 달리, 평면 구동 방식(in-plane switching) 액정 표시 장치는 한 기판 위에 대향 전극과 화소 전극이 모두 형성되어 있는 방식의 액정 표시 장치로서, 전압이 인가되면 기판에 대해 수평한 방향의 전계가 형성되고 액정 분자들은 수평 전계에 따라 기판과 평행한 면 내에서 회전한다. 따라서, 거시적으로 관찰되는 액정의 굴절율이 다른 방식의 표시 장치에 비해 작게되어 향상된 대비비 및 넓은 시야각을 구현할 수 있다.In contrast, an in-plane switching liquid crystal display device is a liquid crystal display device in which both the counter electrode and the pixel electrode are formed on one substrate. When a voltage is applied, an electric field in a horizontal direction with respect to the substrate is formed. The liquid crystal molecules rotate in a plane parallel to the substrate according to the horizontal electric field. Therefore, the refractive index of the liquid crystal that is observed macroscopically is smaller than that of other display devices, thereby achieving an improved contrast ratio and a wide viewing angle.
이러한 종래의 평면 구동 방식 액정 표시 장치에 대하여 다음에서 설명한다.The conventional flat drive type liquid crystal display device will be described below.
기판 위에 게이트 배선과 대향 전극을 형성하기 위한 금속을 증착하고, 그 위에 고농도 비정질 실리콘층을 연속적으로 증착한 후, 마스크를 씌워 게이트 배선과 화소 전극 패턴을 형성한다.A metal for forming the gate wiring and the counter electrode is deposited on the substrate, and a high concentration of amorphous silicon layer is continuously deposited thereon, and then the mask is covered to form the gate wiring and the pixel electrode pattern.
그 위에 비정질 실리콘층과 질화 실리콘층을 연속 증착하고 마스크를 씌워 패터닝함으로써 반도체층을 형성하며, 금속을 증착하고 마스크를 씌워 패터닝하여 화소 전극 및 데이터 배선을 형성한다.A semiconductor layer is formed by successively depositing an amorphous silicon layer and a silicon nitride layer, and masking and patterning the semiconductor layer, and depositing and patterning a metal to form a pixel electrode and data wiring.
다음, 보호막을 형성하고 마스크를 이용하여 패터닝한다.Next, a protective film is formed and patterned using a mask.
이처럼, 비틀린 네마틱 방식에 비하여 ITO 화소 전극층을 적층하고 패터닝하는 공정이 생략되었음에도 불구하고 최소한 4매의 마스크를 사용하여야 하므로, 생산성 및 원가 절감 측면에서 큰 이점이 없다.As such, at least four masks must be used, although the process of stacking and patterning the ITO pixel electrode layer is omitted compared to the twisted nematic method, and thus there is no great advantage in terms of productivity and cost reduction.
본 발명은 공정 단순화를 통해 마스크 수를 줄여 비용을 절감하고 생산성을 향상시키는 것이 그 과제이다.The object of the present invention is to reduce the number of masks through process simplification to reduce cost and improve productivity.
이러한 과제를 해결하기 위한 본 발명의 실시예에 따른 평면 구동 방식 액정 표시 장치의 제조 방법에서는 제1 마스크를 이용하여 게이트선 및 게이트 전극 등의 게이트 배선 및 공통 전극을 형성하고, 그 위에 게이트 절연막, 비정질 규소층, 도핑된 비정질 규소층, 금속막을 차례로 적층한 후, 제2 마스크를 이용하여 금속막을 패터닝하여 데이터선, 소스 및 드레인 전극 등의 데이터 배선 및 화소 전극을 형성한 다음, 데이터 배선 및 화소 전극을 마스크로 하여 도핑된 비정질 규소층 및 비정질 규소층 및 게이트 절연막을 패터닝한다.In the manufacturing method of the planar driving type liquid crystal display device according to the embodiment of the present invention for solving this problem, a gate wiring and a common electrode such as a gate line and a gate electrode are formed using a first mask, and a gate insulating film, After laminating an amorphous silicon layer, a doped amorphous silicon layer, and a metal film, the metal film is patterned using a second mask to form data lines and pixel electrodes such as data lines, source and drain electrodes, and then data lines and pixels. The doped amorphous silicon layer, the amorphous silicon layer, and the gate insulating film are patterned using the electrode as a mask.
또한, 본 발명의 다른 실시예에 따른 평면 구동 액정 표시 장치의 제조 방법에서는 제1 마스크를 이용하여 데이터 배선 및 공통 전극 및 화소 전극을 먼저 형성한 후, 도핑된 비정질 규소층, 비정질 규소층, 게이트 절연막, 금속막을 차례로 적층하고, 제2 마스크를 이용하여 금속막을 패터닝하여 게이트 배선을 형성한 다음, 게이트 배선을 마스크로 하여 게이트 절연막 및 비정질 규소층 및 도핑된 비정질 규소층을 패터닝한다.In addition, in the manufacturing method of the planar driving liquid crystal display according to another exemplary embodiment of the present invention, the data line, the common electrode, and the pixel electrode are first formed using a first mask, and then the doped amorphous silicon layer, the amorphous silicon layer, and the gate are formed. The insulating film and the metal film are stacked in this order, the metal film is patterned using a second mask to form a gate wiring, and then the gate insulating film, the amorphous silicon layer, and the doped amorphous silicon layer are patterned using the gate wiring as a mask.
여기에서, 보호 절연막 및 평탄화를 위한 유기 절연막을 적층할 수 있으며, 제3 마스크를 이용하여 유기 절연막 패턴을 형성하고, 이 패턴을 마스크로 하여 보호 절연막을 패터닝하는 것이 바람직하다.Here, it is preferable to form a protective insulating film and an organic insulating film for planarization, to form an organic insulating film pattern using a third mask, and to pattern the protective insulating film using this pattern as a mask.
이처럼, 비정질 규소층 및 도핑된 비정질 규소층을 게이트 배선 또는 데이터 배선을 마스크로 패터닝하기 때문에 마스크 공정을 한 단계 줄일 수 있다.As such, the mask process can be reduced by one step because the amorphous silicon layer and the doped amorphous silicon layer are patterned with a gate wiring or a data wiring as a mask.
그러면, 첨부한 도면을 참고로 하여 본 발명에 따른 평면 구동 방식 액정 표시 장치에 대하여 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 상세하게 설명한다.Next, the planar driving liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings so that a person skilled in the art can easily implement the present invention.
먼저, 본 발명에 따른 평면 구동 방식 액정 표시 장치의 구조에 대하여 설명한다.First, the structure of the flat drive type liquid crystal display device according to the present invention will be described.
도 1은 본 발명에 따른 평면 구동 방식의 액정 표시 장치의 배치도이고, 도 2는 도 1의 II-II'선에 대한 단면도이다.FIG. 1 is a layout view of a flat panel liquid crystal display device according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II-II 'of FIG. 1.
도 1 및 도 2에 도시한 바와 같이, 기판(100) 위에 한 방향으로 게이트선(200)이 형성되어 있고, 그 일부가 연장되어 게이트 전극(210)을 이룬다. 게이트선(200)과 평행하게 공통 전극선(310)이 형성되어 있고, 공통 전극선(310)으로부터 다수의 공통 전극(300)이 게이트선(200) 쪽으로 연장되어 있다.As shown in FIGS. 1 and 2, the gate line 200 is formed in one direction on the substrate 100, and a part thereof extends to form the gate electrode 210. The common electrode line 310 is formed in parallel with the gate line 200, and a plurality of common electrodes 300 extend from the common electrode line 310 toward the gate line 200.
게이트선(200) 및 게이트 전극(210), 공통 전극선(310) 및 공통 전극(300) 위를 게이트 절연막(400)이 덮고 있다.The gate insulating layer 400 covers the gate line 200, the gate electrode 210, the common electrode line 310, and the common electrode 300.
게이트 절연막(400) 위에는 게이트선(200)과 수직하게 데이터선(600)이 형성되어 있고, 소스 전극(610)이 데이터선(600)으로부터 연장되어 게이트 전극(210)의 한쪽 가장자리와 중첩되며, 드레인 전극(620)이 게이트 전극(210)의 반대쪽 가장자리와 중첩되어 있다. 드레인 전극(620)이 연장되어 화소 전극선(701)을 이루며, 화소 전극선(701)으로부터 다수의 화소 전극(700)이 공통 전극선(310)쪽으로 연장되어 있다. 이때, 화소 전극(700)과 공통 전극(300)은 서로 엇갈리는 형태로 평행하게 형성되어 있다.The data line 600 is formed on the gate insulating layer 400 to be perpendicular to the gate line 200, the source electrode 610 extends from the data line 600 to overlap one edge of the gate electrode 210. The drain electrode 620 overlaps the opposite edge of the gate electrode 210. The drain electrode 620 extends to form the pixel electrode line 701, and the plurality of pixel electrodes 700 extend from the pixel electrode line 701 toward the common electrode line 310. In this case, the pixel electrode 700 and the common electrode 300 are formed parallel to each other in a staggered form.
데이터선(600), 소스 및 드레인 전극(601, 620), 화소 전극선(701) 및 화소 전극(700)의 패턴을 따라 그 하부에 도핑된 비정질 규소층(501) 및 비정질 규소층(510)이 형성되어 있고, 소스 및 드레인 전극(610, 620) 사이의 도핑된 비정질 규소층(501)은 제거되어 있다. 여기에서, 게이트 전극(210) 상부 게이트 절연막(400) 위에 위치한 비정질 규소층(510) 영역이 반도체 활성층의 역할을 한다.The amorphous silicon layer 501 and the amorphous silicon layer 510 doped under the pattern of the data line 600, the source and drain electrodes 601 and 620, the pixel electrode line 701, and the pixel electrode 700 may be formed. And the doped amorphous silicon layer 501 between the source and drain electrodes 610 and 620 is removed. Here, the region of the amorphous silicon layer 510 positioned on the upper gate insulating layer 400 of the gate electrode 210 serves as the semiconductor active layer.
배선 위에 보호 절연막(800)이 덮여 있으며, 그 위에는 단차를 없애기 위한 유기 절연막(900)이 덮여 있다.The protective insulating film 800 is covered on the wiring, and the organic insulating film 900 for removing the step is covered thereon.
도 3에는 본 발명의 다른 실시예에 따른 층상 구조가 도시되어 있다.3 shows a layered structure according to another embodiment of the present invention.
앞선 실시예와 마찬가지의 형태로 배선이 배치되어 있으나, 층상 구조에 차이가 있다. 특히, 소스 및 드레인 전극(610, 620), 화소 전극선(701) 및 화소 전극(700)과 공통 전극선(310) 및 공통 전극(300)이 기판(100) 위에 형성되어 있으며, 게이트선(200) 및 게이트 전극(210)은 소스 및 드레인 전극(610, 620)의 위쪽에 위치한다. 게이트 전극(210)은 소스 및 드레인 전극(610, 620)과 일정 폭 중첩되어 있으며, 게이트 전극(210) 및 게이트선(200)과 동일한 패턴으로 그 하부에는 게이트 절연막(400), 비정질 규소층(510), 도핑된 비정질 규소층(501)이 형성되어 있다. 결국, 소스 및 드레인 전극(610, 620)은 비정질 규소층(510)의 양쪽 가장자리와 도핑된 비정질 규소층(501)을 매개로 중첩하며 비정질 규소층(510)과 게이트 전극(210)은 게이트 절연막(400)을 사이에 두고 겹쳐있는 탑 게이트 방식의 박막 트랜지스터가 형성되어 있다. 게이트선(200) 및 게이트 전극(210)을 보호 절연막(800)이 덮고 있으며, 보호 절연막(800) 위에는 유기 절연막(900)이 덮여 있다.The wiring is arranged in the same manner as in the previous embodiment, but there is a difference in the layer structure. In particular, the source and drain electrodes 610 and 620, the pixel electrode line 701, the pixel electrode 700, the common electrode line 310, and the common electrode 300 are formed on the substrate 100 and the gate line 200. The gate electrode 210 is positioned above the source and drain electrodes 610 and 620. The gate electrode 210 overlaps the source and drain electrodes 610 and 620 by a predetermined width, and has the same pattern as the gate electrode 210 and the gate line 200, and has a gate insulating layer 400 and an amorphous silicon layer under the gate electrode 210. 510, a doped amorphous silicon layer 501 is formed. As a result, the source and drain electrodes 610 and 620 overlap both edges of the amorphous silicon layer 510 and the doped amorphous silicon layer 501, and the amorphous silicon layer 510 and the gate electrode 210 are formed of a gate insulating film. A top gate thin film transistor overlapping with the 400 is formed. The protective insulating film 800 covers the gate line 200 and the gate electrode 210, and the organic insulating film 900 is covered on the protective insulating film 800.
앞서 설명한 바와 같이, 비정질 규소층 및 도핑된 비정질 규소층이, 데이터 배선 및 공통 전극 배선과 동일한 패턴으로 형성되어 있거나 게이트 배선과 동일한 패턴으로 형성되어 있다.As described above, the amorphous silicon layer and the doped amorphous silicon layer are formed in the same pattern as the data wiring and the common electrode wiring or in the same pattern as the gate wiring.
이러한 구조를 가지는 평면 구동 방식 액정 표시 장치는 마스크 3매 만을 이용하여 제작할 수 있다.The planar drive type liquid crystal display device having such a structure can be manufactured using only three masks.
그러면, 본 발명에 따른 평면 구동 액정 표시 장치의 제조 방법에 대하여 첨부한 도면을 참고로 하여 다음에서 설명한다.Next, a method of manufacturing the flat panel liquid crystal display according to the present invention will be described below with reference to the accompanying drawings.
도 4a 내지 도 4d는 제1 실시예에 따른 평면 구동 액정 표시 장치의 제조 방법을 공정 순서에 따라 차례로 나타낸 단면도로서, 버텀 게이트 방식 박막 트랜지스터 액정 표시 장치의 제조 방법을 나타낸다.4A to 4D are cross-sectional views sequentially illustrating a method of manufacturing the planar driving liquid crystal display according to the first embodiment, according to a process sequence, and a method of manufacturing the bottom gate type thin film transistor liquid crystal display.
투명 절연 기판(100) 위에 몰리브덴-텅스텐(MoW) 단일막 또는 알루미늄과 몰리브덴-텅스텐(Al/MoW)의 이중막 구조의 제1 금속막을 증착하고 제1 마스크를 이용하여 패터닝하여 게이트선(200), 게이트 전극(210) 및 게이트 패드 등의 게이트 배선과 공통 전극선 및 공통 전극(300) 등의 공통 전극 배선을 형성한다(도 4a 참조).A first metal film having a single layer of molybdenum-tungsten (MoW) or a double layer structure of aluminum and molybdenum-tungsten (Al / MoW) is deposited on the transparent insulating substrate 100, and patterned using a first mask to form a gate line 200. The gate wirings such as the gate electrode 210 and the gate pad and the common electrode wirings such as the common electrode line and the common electrode 300 are formed (see FIG. 4A).
그 위에 게이트 절연막(400), 비정질 규소층(500), 도핑된 비정질 규소층(501), 제2 금속막(600)을 차례로 적층한다. 이때, 제2 금속막(600)은 크롬(Cr) 또는 몰리브덴-텅스텐(MoW) 단일막 또는 알루미늄 및 몰리브덴-텅스텐(Al/MoW) 이중막 구조를 가진다(도 4b 참조).The gate insulating film 400, the amorphous silicon layer 500, the doped amorphous silicon layer 501, and the second metal film 600 are sequentially stacked thereon. In this case, the second metal film 600 has a chromium (Cr) or molybdenum-tungsten (MoW) single layer or an aluminum and molybdenum-tungsten (Al / MoW) double layer structure (see FIG. 4B).
다음, 제2 마스크를 이용하여 패터닝하여 데이터선(600), 소스 및 드레인 전극(610, 620), 데이터 패드 등의 데이터 배선과 화소 전극선(710) 및 화소 전극(700) 등의 화소 전극 배선을 형성한다. 다음, 데이터 배선 및 화소 전극 배선을 마스크로 사용하여 비정질 규소층(500) 및 도핑된 비정질 규소층(501)을 패터닝한다(도 4c 참조).Next, patterning is performed using a second mask to form data wires such as the data line 600, the source and drain electrodes 610 and 620, a data pad, and pixel electrode wires such as the pixel electrode line 710 and the pixel electrode 700. Form. Next, the amorphous silicon layer 500 and the doped amorphous silicon layer 501 are patterned using the data wirings and the pixel electrode wirings as masks (see FIG. 4C).
보호 절연막(800) 및 단차부를 평탄화하기 위한 유기 절연막(900)을 적층한 후, 제3 마스크를 사용하여 유기 절연막(900)을 패터닝하고 유기 절연막(900) 패턴을 마스크로 하여 보호 절연막(800)을 패터닝한다. 이 과정에서, 게이트 패드 및 데이터 패드가 보호 절연막(800) 외부로 드러난다(도 4d 참조).After stacking the protective insulating film 800 and the organic insulating film 900 to planarize the stepped portion, the organic insulating film 900 is patterned using a third mask, and the protective insulating film 800 is formed using the organic insulating film 900 pattern as a mask. Pattern. In this process, the gate pad and the data pad are exposed to the outside of the protective insulating layer 800 (see FIG. 4D).
이처럼, 별도의 마스크를 사용하지 않고 데이터 배선(600, 610, 620) 및 화소 전극 배선(700, 701)을 마스크로 하여 비정질 규소층(500) 및 도핑된 비정질 규소층(501)을 패터닝하므로 3매의 마스크만으로 공정을 진행할 수 있다.As such, the amorphous silicon layer 500 and the doped amorphous silicon layer 501 are patterned using the data wirings 600, 610, and 620 and the pixel electrode wirings 700 and 701 as masks without using a separate mask. The process can be carried out only with the mask of the sheet.
다음, 도 5a 내지 도 5d는 본 발명의 제2 실시예에 따른 평면 구동 액정 표시 장치의 제조 방법을 공정 순서에 따라 나타낸 단면도로서, 탑 게이트 방식 박막 트랜지스터 액정 표시 장치의 제조 방법에 관한 것이다.Next, FIGS. 5A to 5D are cross-sectional views illustrating a manufacturing method of a planar driving liquid crystal display device according to a second exemplary embodiment of the present invention, in order of manufacturing a top gate type thin film transistor liquid crystal display device.
투명 절연 기판(100) 위에 크롬(Cr) 또는 몰리브덴-텅스텐(MoW) 단일막 또는 알루미늄 및 몰리브덴-텅스텐(MoW) 이중막 구조의 제1 금속막을 증착하고, 제1 마스크를 사용한 패터닝으로 데이터선(600), 소스 및 드레인 전극(610, 620), 데이터 패드 등의 데이터 배선, 화소 전극(700) 및 화소 전극선(701) 등의 화소 전극 배선, 공통 전극(300) 및 공통 전극선(310) 등의 공통 전극 배선을 형성한다(도 5a 참조).A first metal film having a chromium (Cr) or molybdenum-tungsten (MoW) single layer or an aluminum and molybdenum-tungsten (MoW) double-layer structure is deposited on the transparent insulating substrate 100, and the data line is patterned by patterning using the first mask. 600, data wires such as source and drain electrodes 610 and 620, data pads, pixel electrode wires such as pixel electrode 700 and pixel electrode line 701, common electrode 300 and common electrode line 310, and the like. The common electrode wirings are formed (see FIG. 5A).
그 위에 도핑된 비정질 규소층(501), 비정질 규소층(500), 게이트 절연막(400), 몰리브덴-텅스텐(MoW) 단일막 또는 알루미늄 및 몰리브덴-텅스텐(Al/MoW) 이중막 구조의 제2 금속막(200)을 차례대로 적층한 후(도 5b 참조), 제2 마스크를 사용하여 패터닝하여 게이트선(200), 게이트 전극(210), 게이트 패드 등의 게이트 배선을 형성한다. 다음, 게이트 배선을 마스크로 하여 게이트 절연막(400), 비정질 규소층(500), 도핑된 비정질 규소층(501)을 패터닝한다(도 5c 참조).A doped amorphous silicon layer 501, an amorphous silicon layer 500, a gate insulating film 400, a molybdenum-tungsten (MoW) single layer or a second metal of aluminum and molybdenum-tungsten (Al / MoW) bilayer structure thereon After the films 200 are sequentially stacked (see FIG. 5B), patterning is performed using a second mask to form gate lines such as the gate line 200, the gate electrode 210, and the gate pad. Next, the gate insulating film 400, the amorphous silicon layer 500, and the doped amorphous silicon layer 501 are patterned using the gate wiring as a mask (see FIG. 5C).
보호 절연막(800) 및 유기 절연막(900)을 차례로 적층하고, 유기 절연막(900)을 패터닝한 후, 이를 마스크로 하여 보호 절연막(800)을 패터닝한다. 앞선 실시예와 마찬가지로, 이 과정에서 게이트 패드 및 데이터 패드가 보호 절연막(800) 외부로 드러난다(도 5d 참조).The protective insulating film 800 and the organic insulating film 900 are sequentially stacked, the organic insulating film 900 is patterned, and the protective insulating film 800 is patterned using the mask. As in the previous embodiment, the gate pad and the data pad are exposed to the outside of the protective insulating film 800 in this process (see FIG. 5D).
이처럼, 별도의 마스크를 사용하지 않고 게이트 배선(200, 210)을 마스크로 하여 비정질 규소층(500), 도핑된 비정질 규소층(501) 및 게이트 절연막(400)을 패터닝하므로 3매의 마스크만으로 공정을 진행할 수 있다.As such, the amorphous silicon layer 500, the doped amorphous silicon layer 501, and the gate insulating layer 400 are patterned using the gate wirings 200 and 210 as masks without using a separate mask, so that only three masks are used. You can proceed.
또한, 도면에는 도시되어 있지 않지만 공정 중 발생하는 정전기를 방전시키기 위한 게이트 쇼팅 바(gate shorting bar) 및 데이터 쇼팅 바(data shorting bar)가 게이트 배선 및 데이터 배선을 패터닝하는 단계에서 형성되는데, 두 쇼팅 바는 서로 중첩되도록 형성하며, 필요한 경우 레이저를 이용하여 단락시킬 수 있으므로 마스크를 이용해 별도의 접촉구를 형성할 필요가 없다.In addition, although not shown in the drawings, a gate shorting bar and a data shorting bar for discharging static electricity generated during the process are formed in the patterning of the gate wiring and the data wiring. The bars are formed to overlap each other and can be short-circuited with a laser if necessary, so there is no need to form a separate contact hole using a mask.
이상에서와 같이, 3매 마스크를 사용하여 액정 표시 장치를 제조함으로써, 원가가 절감되고 생산성이 향상된다.As described above, by manufacturing the liquid crystal display using the three masks, the cost is reduced and the productivity is improved.
도 1은 본 발명에 따른 평면 구동 방식의 액정 표시 장치의 배치도이고,1 is a layout view of a flat panel liquid crystal display device according to an exemplary embodiment of the present invention.
도 2 및 도 3은 도 1의 II-II' 선에 대한 단면도로서, 버텀(bottom) 및 탑(top) 게이트 방식 박막 트랜지스터의 단면도이고,2 and 3 are cross-sectional views taken along the line II-II ′ of FIG. 1 and are cross-sectional views of bottom and top gate thin film transistors.
도 4a 내지 도 4d는 제1 실시예에 따른 평면 구동 방식 액정 표시 장치의 제조 방법을 공정 순서에 따라 나타낸 단면도이고,4A to 4D are cross-sectional views illustrating a method of manufacturing a flat panel type liquid crystal display device according to a first embodiment according to a process sequence;
도 5a 내지 도 5d는 제2 실시예에 따른 평면 구동 방식 액정 표시 장치의 제조 방법을 공정 순서에 따라 나타낸 단면도이다.5A to 5D are cross-sectional views illustrating a method of manufacturing a flat panel type liquid crystal display device according to a second embodiment according to a process sequence.
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| KR100476048B1 (en) * | 2001-05-31 | 2005-03-10 | 비오이 하이디스 테크놀로지 주식회사 | Method for manufacturing tft-lcd |
| KR100499371B1 (en) * | 2002-04-17 | 2005-07-04 | 엘지.필립스 엘시디 주식회사 | Thin film transistor array substrate and method of manufacturing the same |
| JP2004302466A (en) | 2003-03-29 | 2004-10-28 | Lg Philips Lcd Co Ltd | Level electrical field applicator version liquid crystal display device and its manufacturing method |
| KR100598737B1 (en) | 2003-05-06 | 2006-07-10 | 엘지.필립스 엘시디 주식회사 | Thin film transistor array substrate and fabricating method thereof |
| KR101054819B1 (en) | 2003-06-24 | 2011-08-05 | 엘지디스플레이 주식회사 | Array board for transverse electric field type liquid crystal display device and manufacturing method thereof |
| KR101106556B1 (en) * | 2004-11-26 | 2012-01-19 | 엘지디스플레이 주식회사 | Array substrate for IPS-LC0 and Method for fabricating of the same |
| KR101137861B1 (en) * | 2005-06-20 | 2012-04-20 | 엘지디스플레이 주식회사 | Thin film transister of fringe field switching type and fabricating method thereof |
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| JPH09139503A (en) * | 1995-11-14 | 1997-05-27 | Sharp Corp | Reverse stagger type thin film transistor, its manufacture, and liquid crystal display using the it |
| JPH09269497A (en) * | 1996-01-31 | 1997-10-14 | Hosiden Corp | Liquid crystal display element |
| JPH1039331A (en) * | 1996-04-09 | 1998-02-13 | Lg Electron Inc | Production of active matrix type liquid crystal display device and active matrix type liquid crystal display device produced by this process |
| JPH1079514A (en) * | 1996-09-05 | 1998-03-24 | Toshiba Corp | Method for manufacturing active matrix board |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09139503A (en) * | 1995-11-14 | 1997-05-27 | Sharp Corp | Reverse stagger type thin film transistor, its manufacture, and liquid crystal display using the it |
| JPH09269497A (en) * | 1996-01-31 | 1997-10-14 | Hosiden Corp | Liquid crystal display element |
| JPH1039331A (en) * | 1996-04-09 | 1998-02-13 | Lg Electron Inc | Production of active matrix type liquid crystal display device and active matrix type liquid crystal display device produced by this process |
| JPH1079514A (en) * | 1996-09-05 | 1998-03-24 | Toshiba Corp | Method for manufacturing active matrix board |
Also Published As
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|---|---|
| KR19990079262A (en) | 1999-11-05 |
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