KR100524905B1 - Method for forming anchored via contact - Google Patents
Method for forming anchored via contact Download PDFInfo
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- KR100524905B1 KR100524905B1 KR10-1998-0028414A KR19980028414A KR100524905B1 KR 100524905 B1 KR100524905 B1 KR 100524905B1 KR 19980028414 A KR19980028414 A KR 19980028414A KR 100524905 B1 KR100524905 B1 KR 100524905B1
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- barrier layer
- forming
- layer pattern
- via hole
- wiring layer
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000010410 layer Substances 0.000 claims abstract description 126
- 230000004888 barrier function Effects 0.000 claims abstract description 69
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 239000011229 interlayer Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 11
- 229910052721 tungsten Inorganic materials 0.000 claims description 11
- 239000010937 tungsten Substances 0.000 claims description 11
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- 239000010936 titanium Substances 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 5
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 239000011259 mixed solution Substances 0.000 claims description 2
- 239000002356 single layer Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- -1 for example Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
금속 배선층 사이에 형성되는 앵커 형상의 비아 콘택(via contact) 형성 방법에 관하여 개시한다. 본 발명에 따른 반도체 소자의 비아 콘택 형성 방법은 반도체 기판상에 배선층을 형성하는 단계와, 상기 배선층 위에 배리어층을 형성하는 단계와, 상기 배리어층 및 배선층을 패터닝하여 배선층 패턴 및 배리어층 패턴을 형성하는 단계와, 상기 결과물을 덮는 금속 층간 절연막을 형성하는 단계와, 상기 금속 층간 절연막을 이방성 식각하여 상기 배리어층 패턴을 노출시키는 비아 홀을 형성하는 단계와, 상기 배리어층 패턴의 노출된 부분을 등방성 식각하여, 상기 비아 홀로부터 연속적으로 상기 비아 홀보다 큰 폭으로 상기 배리어층 패턴 내로 연장되는 앵커 홀(anchor hole)을 형성하는 단계를 포함한다. A method of forming an anchor-shaped via contact formed between metal wiring layers is disclosed. A method for forming a via contact of a semiconductor device according to the present invention includes forming a wiring layer on a semiconductor substrate, forming a barrier layer on the wiring layer, and patterning the barrier layer and the wiring layer to form a wiring layer pattern and a barrier layer pattern. Forming an interlayer insulating film covering the resultant; forming an via hole for exposing the barrier layer pattern by anisotropically etching the interlayer insulating film; and isotropically exposing the exposed portion of the barrier layer pattern. Etching to form an anchor hole extending from the via hole continuously into the barrier layer pattern with a width greater than that of the via hole.
Description
본 발명은 반도체 소자 형성 방법에 관한 것으로, 특히 금속 배선층 사이에 형성되는 비아 콘택(via contact) 형성 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and more particularly to a method of forming a via contact formed between metal wiring layers.
반도체 소자의 제조 공정에 있어서, 통상적으로는 금속 배선층 사이에 비아 콘택을 형성하기 위하여, 먼저 금속 배선층 사이의 금속 층간 절연막을 관통하도록 실린더 형상의 콘택홀을 건식 식각 공정에 의하여 형성하고, 세정 공정을 통하여 건식 식각시 발생된 잔류물을 제거하는 공정을 거친 후, 상기 콘택홀 내에 텅스텐과 같은 금속 플러그를 형성하여 비아 콘택을 형성한다. In the semiconductor device manufacturing process, in order to form a via contact between the metal wiring layers, a cylindrical contact hole is first formed by a dry etching process so as to penetrate the metal interlayer insulating film between the metal wiring layers, and then the cleaning process is performed. After passing through the process of removing the residue generated during the dry etching through, a metal plug such as tungsten is formed in the contact hole to form a via contact.
그러나, 상기한 바와 같은 통상적인 방법에서는 텅스텐 플러그에 대하여 CMP(Chemical Mechanical Polishing) 공정 또는 세정 공정과 같은 후속 공정을 진행할 때 물리적 또는 화학적으로 손상을 입을 수 있으며, 이와 같은 경우에 콘택과 금속 배선과의 접촉면이 불안정하게 되고, 이와 같은 현상이 심회되면 텅스텐 플러그가 하부의 금속 배선층으로부터 리프팅(lifting)되어 빠져 나오는 문제가 발생된다. However, in the conventional method as described above, the tungsten plug may be physically or chemically damaged during a subsequent process such as a chemical mechanical polishing (CMP) process or a cleaning process, in which case the contact and metal wiring and Contact surface becomes unstable, and when such a phenomenon occurs, a problem occurs in that the tungsten plug is lifted out of the lower metal wiring layer.
본 발명의 목적은 상기한 종래의 문제점을 해결하고자 하는 것으로서, 금속 배선층을 상호 연결시키기 위한 콘택 플러그의 리프팅 현상을 방지할 수 있는 구조를 가지는 반도체 소자의 비아 콘택을 형성하는 방법을 제공하는 것이다. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a via contact of a semiconductor device having a structure capable of preventing a lifting phenomenon of a contact plug for interconnecting metal wiring layers.
상기 목적을 달성하기 위하여, 본 발명에 따른 반도체 소자의 비아 콘택 형성 방법에서는 (a) 반도체 기판상에 배선층을 형성하는 단계와, (b) 상기 배선층 위에 배리어층을 형성하는 단계와, (c) 상기 배리어층 및 배선층을 패터닝하여 배선층 패턴 및 배리어층 패턴을 형성하는 단계와, (d) 상기 (c)의 결과물을 덮는 금속 층간 절연막을 형성하는 단계와, (e) 상기 금속 층간 절연막을 이방성 식각하여 상기 배리어층 패턴을 노출시키는 비아 홀을 형성하는 단계와, (f) 상기 배리어층 패턴의 노출된 부분을 등방성 식각하여, 상기 비아 홀로부터 연속적으로 상기 비아 홀보다 큰 폭으로 상기 배리어층 패턴 내로 연장되는 앵커 홀(anchor hole)을 형성하는 단계를 포함한다. In order to achieve the above object, in the method for forming a via contact of a semiconductor device according to the present invention, (a) forming a wiring layer on a semiconductor substrate, (b) forming a barrier layer on the wiring layer, and (c) Patterning the barrier layer and the wiring layer to form a wiring layer pattern and a barrier layer pattern, (d) forming a metal interlayer insulating film covering the resultant of (c), and (e) anisotropically etching the metal interlayer insulating film. Forming a via hole exposing the barrier layer pattern, and (f) isotropically etching the exposed portion of the barrier layer pattern into the barrier layer pattern with a width greater than that of the via hole continuously from the via hole. Forming an anchor hole that extends.
상기 단계 (a)에서 상기 배선층은 알루미늄, 텅스텐, 티타늄, 구리 및 이들의 합금으로 이루어지는 군에서 선택되는 어느 하나로 형성된다. In the step (a), the wiring layer is formed of any one selected from the group consisting of aluminum, tungsten, titanium, copper and alloys thereof.
상기 단계 (b)에서 상기 배리어층은 TiN으로 이루어지는 단일층으로 형성될 수 있다. 또는, Ti로 이루어지는 제1 배리어층과 TiN으로 이루어지는 제2 배리어층이 차례로 적층된 이중층으로 형성될 수 있다. 이 때, 상기 배리어층이 이중층으로 형성되는 경우에는 상기 단계 (f)에서 상기 앵커 홀은 상기 제1 배리어층의 상면을 노출시키도록 형성된다. In the step (b), the barrier layer may be formed of a single layer made of TiN. Alternatively, the first barrier layer made of Ti and the second barrier layer made of TiN may be formed as a double layer sequentially stacked. In this case, when the barrier layer is formed of a double layer, in the step (f), the anchor hole is formed to expose the top surface of the first barrier layer.
상기 단계 (d)에서 상기 금속 층간 절연막은 PE-TEOS, USG, BPSG, FOx 및 PE-SiH4로 이루어지는 군에서 선택되는 어느 하나로 형성된다.In the step (d), the metal interlayer insulating film is formed of any one selected from the group consisting of PE-TEOS, USG, BPSG, FO x and PE-SiH 4 .
상기 단계 (f)에서 상기 배리어층 패턴의 식각은 희석 과산화수소수 용액을 식각액으로 사용하는 습식 식각 방법, 또는 희석 과산화수소수 용액과 암모니아수의 혼합액을 식각액으로 사용하는 습식 식각 방법에 의하여 행한다. In the step (f), the barrier layer pattern is etched by a wet etching method using a dilute hydrogen peroxide solution as an etchant, or a wet etching method using a mixed solution of dilute hydrogen peroxide solution and ammonia water as an etchant.
본 발명에 따른 비아 콘택 형성 방법은 상기 비아 홀 및 앵커 홀 내부를 도전 물질, 바람직하게는 텅스텐으로 채워서 단면이 앵커 형상을 갖는 콘택 플러그를 형성하는 단계를 더 포함할 수 있다. The via contact forming method according to the present invention may further include filling the via hole and the anchor hole with a conductive material, preferably tungsten, to form a contact plug having an anchor shape in cross section.
본 발명에 의하면, 비아 콘택을 형성하는 콘택 플러그의 단면이 앵커 형상이 되도록 저면에 측방향 돌출부를 형성함으로써, 상기 콘택 플러그가 상기 금속 배선층으로부터 리프팅되는 것을 물리적으로 방지할 수 있다. According to the present invention, it is possible to physically prevent the contact plug from being lifted from the metal wiring layer by forming a lateral protrusion on the bottom surface such that the cross section of the contact plug forming the via contact is anchored.
다음에, 본 발명의 바람직한 실시예에 대하여 첨부 도면을 참조하여 상세히 설명한다. Next, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1f는 본 발명의 제1 실시예에 따른 반도체 소자의 비아 콘택 형성 방법을 설명하기 위하여 공정 순서에 따라 도시한 단면도들이다. 1A to 1F are cross-sectional views illustrating a method of forming a via contact in a semiconductor device according to a first embodiment of the present invention in a process sequence.
도 1a를 참조하면, 트랜지스터 등과 같은 소자들이 층간 절연막에 의하여 덮여 있는 반도체 기판(10)상에 배선층(20), 예를 들면 알루미늄층을 형성한다. 상기 배선층(20)은 알루미늄 외에 텅스텐, 티타늄, 구리, 또는 이들의 합금으로 형성될 수도 있다. 상기 배선층(20) 위에 TiN으로 이루어지는 배리어층(22)을 형성한다. 본 실시예에서는 상기 배리어층(22)이 TiN 단일층으로 이루어진다. Referring to FIG. 1A, a wiring layer 20, for example, an aluminum layer is formed on a semiconductor substrate 10 on which elements such as transistors and the like are covered by an interlayer insulating film. The wiring layer 20 may be formed of tungsten, titanium, copper, or an alloy thereof in addition to aluminum. A barrier layer 22 made of TiN is formed on the wiring layer 20. In this embodiment, the barrier layer 22 is made of a single TiN layer.
도 1b를 참조하면, 상기 배리어층(22) 및 배선층(20)을 패터닝하여 배선층 패턴(20a) 및 배리어층 패턴(22a)을 형성한다. Referring to FIG. 1B, the barrier layer 22 and the wiring layer 20 are patterned to form the wiring layer pattern 20a and the barrier layer pattern 22a.
도 1c를 참조하면, 상기 배선층 패턴(20a) 및 배리어층 패턴(22a)이 형성된 결과물을 덮는 금속 층간 절연막(30)을 형성한다. Referring to FIG. 1C, the metal interlayer insulating layer 30 covering the resultant formed with the wiring layer pattern 20a and the barrier layer pattern 22a is formed.
상기 금속 층간 절연막(30)은 PE-TEOS, USG, BPSG, FOx 또는 PE-SiH4로 형성된다.The metal interlayer insulating film 30 is formed of PE-TEOS, USG, BPSG, FO x or PE-SiH 4 .
도 1d를 참조하면, 상기 금속 층간 절연막(30)을 이방성 식각하여 상기 배리어층 패턴(22a)을 일부 노출시키는 비아 홀(32)을 형성한다. 상기 식각 공정중에 상기 비아 홀(32)의 저면에서 배리어층 패턴(22a)이 남아 있을 때 식각을 중단함으로써, 상기 비아 홀(32)의 저면에서 상기 배리어층 패턴(22a)이 노출되도록 한다. Referring to FIG. 1D, the metal interlayer insulating layer 30 is anisotropically etched to form via holes 32 exposing the barrier layer pattern 22a. The etching stops when the barrier layer pattern 22a remains on the bottom surface of the via hole 32 during the etching process, thereby exposing the barrier layer pattern 22a on the bottom surface of the via hole 32.
도 1e를 참조하면, 상기 비아 홀(32)을 통하여 노출된 상기 배리어층 패턴(22a)을 등방성 식각하여, 상기 비아 홀(32)로부터 연속적으로 상기 비아 홀(32)보다 큰 폭으로 상기 배리어층 패턴(22a) 내로 연장되는 앵커 홀(anchor hole)(34)을 형성한다. Referring to FIG. 1E, the barrier layer pattern 22a exposed through the via hole 32 isotropically etched so that the barrier layer has a width greater than that of the via hole 32 continuously from the via hole 32. An anchor hole 34 is formed extending into the pattern 22a.
이 때, 상기 배리어층 패턴(22a)을 식각할 때에는 상기 배선층 패턴(20a)에 대하여 식각 선택비가 큰 조건으로 식각을 행하여 상기 배선층 패턴(20a)은 식각되지 않도록 한다. At this time, when the barrier layer pattern 22a is etched, the barrier layer pattern 20a is etched under a condition where the etching selectivity is large, so that the wiring layer pattern 20a is not etched.
바람직하게는, 상기 배리어층 패턴(22a)을 등방성 식각하기 위하여 희석 과산화수소수 용액 또는 희석 과산화수소수 용액과 암모니아수의 혼합액을 식각액으로 사용하는 습식 식각 방법에 의하여 행한다. Preferably, in order to isotropically etch the barrier layer pattern 22a, a wet etching method using a dilute hydrogen peroxide solution or a mixture of dilute hydrogen peroxide solution and ammonia water as an etching solution is performed.
상기와 같이 상기 배리어층 패턴(22a)을 습식 식각함으로써 상기 배리어층 패턴(22a)은 상기 비아 홀(32)의 연장 방향 및 수직 방향으로 식각되어, 상기 비아 홀(32)의 저면 근방에 언더컷 영역(34a)을 포함하는 앵커 홀(34)이 형성된다. By wet etching the barrier layer pattern 22a as described above, the barrier layer pattern 22a is etched in an extension direction and a vertical direction of the via hole 32, and thus an undercut region near the bottom surface of the via hole 32. An anchor hole 34 including a 34a is formed.
도 1f를 참조하면, 상기 비아 홀(32) 및 앵커 홀(34) 내부를 CVD(Chemical Vapor Deposition) 방법에 의하여 도전 물질, 예를 들면 텅스텐으로 채워서 콘택 플러그(40)를 형성한다. Referring to FIG. 1F, a contact plug 40 is formed by filling the via hole 32 and the anchor hole 34 with a conductive material, for example, tungsten, by a chemical vapor deposition (CVD) method.
상기 콘택 플러그(40)는 상기 언더컷 영역(34a)에 의하여 측방향 돌출부(44a)를 갖추게 되어, 그 단면이 앵커 형상을 갖게 된다. 상기 앵커 형상을 갖는 콘택 플러그(40)의 돌출부(44a)에 의하여 상기 콘택 플러그(40)가 상기 배선층 패턴(20a)으로부터 리프팅되는 것이 방지된다. The contact plug 40 is provided with a lateral protrusion 44a by the undercut region 34a, so that its cross section has an anchor shape. The protrusion 44a of the contact plug 40 having the anchor shape prevents the contact plug 40 from being lifted from the wiring layer pattern 20a.
도 2a 내지 도 2f는 본 발명의 제2 실시예에 따른 반도체 소자의 비아 콘택 형성 방법을 설명하기 위하여 공정 순서에 따라 도시한 단면도들이다. 제2 실시예에서는 제1 실시예와 같은 원리에 의하여 비아 콘택을 형성한다. 단, 제2 실시예에서는 배선층 위에 형성되는 배리어층을 이중층으로 형성한다. 2A through 2F are cross-sectional views illustrating a method of forming a via contact in a semiconductor device according to a second exemplary embodiment of the present invention in a process sequence. In the second embodiment, the via contact is formed by the same principle as in the first embodiment. However, in the second embodiment, the barrier layer formed on the wiring layer is formed as a double layer.
도 2a를 참조하면, 트랜지스터 등과 같은 소자들이 층간 절연막에 의하여 덮여 있는 반도체 기판(110)상에 배선층(120), 예를 들면 알루미늄층을 형성한다. 상기 배선층(120)은 알루미늄 외에 텅스텐, 티타늄, 구리, 또는 이들의 합금으로 형성될 수도 있다. 상기 배선층(120) 위에 배리어층(122, 124)을 형성한다. 본 실시예에서는 배리어층으로서 Ti로 이루어지는 제1 배리어층(122)과 TiN으로 이루어지는 제2 배리어층(124)이 차례로 적층된 이중층을 형성한다. Referring to FIG. 2A, a wiring layer 120, for example, an aluminum layer, is formed on a semiconductor substrate 110 where elements such as a transistor and the like are covered by an interlayer insulating film. The wiring layer 120 may be formed of tungsten, titanium, copper, or an alloy thereof in addition to aluminum. Barrier layers 122 and 124 are formed on the wiring layer 120. In this embodiment, a double layer is formed in which a first barrier layer 122 made of Ti and a second barrier layer 124 made of TiN are stacked in this order.
도 2b를 참조하면, 상기 제2 배리어층(124), 제1 배리어층(122) 및 배선층(120)을 패터닝하여 배선층 패턴(120a), 제1 배리어층 패턴(122a) 및 제2 배리어층 패턴(124a)으로 이루어지는 도전층 패턴을 형성한다. Referring to FIG. 2B, the second barrier layer 124, the first barrier layer 122, and the wiring layer 120 are patterned to form a wiring layer pattern 120a, a first barrier layer pattern 122a, and a second barrier layer pattern. A conductive layer pattern made of 124a is formed.
도 2c를 참조하면, 상기 도전층 패턴이 형성된 결과물을 덮는 금속 층간 절연막(130)을 형성한다. Referring to FIG. 2C, the metal interlayer insulating layer 130 covering the resultant formed with the conductive layer pattern is formed.
상기 금속 층간 절연막(130)은 PE-TEOS, USG, BPSG, FOx 또는 PE-SiH4로 형성된다.The metal interlayer insulating layer 130 is formed of PE-TEOS, USG, BPSG, FO x or PE-SiH 4 .
도 2d를 참조하면, 상기 금속 층간 절연막(130)을 이방성 식각하여 상기 제2 배리어층 패턴(124a)을 일부 노출시키는 비아 홀(132)을 형성한다. 상기 식각 공정중에 상기 비아 홀(132)의 저면에서 상기 제2 배리어층 패턴(124a)이 남아 있을 때 식각을 중단함으로써, 상기 비아 홀(132)의 저면에서 상기 배리어층 패턴(124a)이 노출되도록 한다. Referring to FIG. 2D, the via interlayer insulating layer 130 is anisotropically etched to form via holes 132 partially exposing the second barrier layer pattern 124a. The etching stops when the second barrier layer pattern 124a remains on the bottom surface of the via hole 132 during the etching process, so that the barrier layer pattern 124a is exposed on the bottom surface of the via hole 132. do.
도 2e를 참조하면, 상기 비아 홀(132)을 통하여 노출된 상기 제2 배리어층 패턴(124a)을 등방성 식각하여, 상기 비아 홀(132)로부터 연속적으로 상기 비아 홀(132)보다 큰 폭으로 상기 제2 배리어층 패턴(124a) 내로 연장되는 앵커 홀(134)을 형성한다. Referring to FIG. 2E, the second barrier layer pattern 124a exposed through the via hole 132 is isotropically etched to have a width larger than that of the via hole 132 continuously from the via hole 132. An anchor hole 134 extending into the second barrier layer pattern 124a is formed.
이 때, 상기 제2 배리어층 패턴(124a)을 식각할 때에는 상기 제1 배리어층 패턴(122a)에 대하여 식각 선택비가 큰 조건으로 식각을 행하여 상기 제1 배리어층(122a) 패턴에 대하여는 식각량을 작게함으로써, 상기 제2 배리어층 패턴(120a)만식각되고, 상기 제1 배리어층 패턴(122a)에서 식각이 중단되도록 한다. In this case, when the second barrier layer pattern 124a is etched, the etching amount is etched with respect to the first barrier layer pattern 122a under a large etching selectivity. By reducing the size, only the second barrier layer pattern 120a is etched, and the etching is stopped on the first barrier layer pattern 122a.
바람직하게는, 상기 제2 배리어층 패턴(124a)을 등방성 식각하기 위하여 희석 과산화수소수 용액 또는 희석 과산화수소수 용액과 암모니아수의 혼합액을 식각액으로 사용하는 습식 식각 방법에 의하여 행한다. Preferably, in order to isotropically etch the second barrier layer pattern 124a, a wet etching method using a dilute hydrogen peroxide solution or a mixture of dilute hydrogen peroxide solution and ammonia water as an etching solution is performed.
상기와 같이 상기 제2 배리어층 패턴(124a)을 습식 식각함으로써 상기 제2 배리어층 패턴(124a)은 상기 비아 홀(132)의 연장 방향 및 수직 방향으로 식각되어, 상기 비아 홀(132)의 저면 근방에 언더컷 영역(134a)을 포함하는 앵커 홀(134)이 형성된다. By wet etching the second barrier layer pattern 124a as described above, the second barrier layer pattern 124a is etched in an extending direction and a vertical direction of the via hole 132, thereby forming a bottom surface of the via hole 132. An anchor hole 134 including an undercut region 134a is formed in the vicinity.
도 2f를 참조하면, 상기 비아 홀(132) 및 앵커 홀(134) 내부를 CVD 방법에 의하여 도전 물질, 예를 들면 텅스텐으로 채워서 콘택 플러그(140)를 형성한다. Referring to FIG. 2F, the contact hole 140 is formed by filling the via hole 132 and the anchor hole 134 with a conductive material, for example, tungsten, by a CVD method.
상기 콘택 플러그(140)는 상기 언더컷 영역(134a)에 의하여 측방향 돌출부(140a)를 갖추게 되어, 그 단면이 앵커 형상을 갖게 된다. 상기 앵커 형상을 갖는 콘택 플러그(140)의 돌출부(140a)에 의하여 상기 콘택 플러그(140)가 상기 배선층 패턴(120a)으로부터 리프팅되는 것이 방지된다. The contact plug 140 is provided with a lateral protrusion 140a by the undercut region 134a, so that the cross section has an anchor shape. Lifting of the contact plug 140 from the wiring layer pattern 120a is prevented by the protrusion 140a of the contact plug 140 having the anchor shape.
상기한 바와 같이, 본 발명에 의하면 금속 배선층간의 인터커넥션을 위한 비아 콘택을 형성할 때 콘택 플러그의 단면이 앵커 형상이 되도록 저면에 측방향 돌출부를 형성하고, 상기 돌출부는 상기 비아 콘택과 연결되는 하부 금속 배선층의 상면에 형성되는 배리어층 내에서 상기 비아 콘택의 연장 방향과 수직 방향으로 연장되도록 함으로써, 상기 비아 콘택을 형성하는 콘택 플러그가 상기 금속 배선층으로부터 리프팅되는 것을 물리적으로 방지할 수 있다. As described above, according to the present invention, when forming a via contact for interconnection between the metal wiring layers, a lateral protrusion is formed on the bottom of the contact plug so that the cross section of the contact plug is anchored, and the protrusion is connected to the via contact. By extending in the direction perpendicular to the extending direction of the via contact in the barrier layer formed on the upper surface of the metal wiring layer, it is possible to physically prevent the contact plug forming the via contact from being lifted from the metal wiring layer.
이상, 본 발명을 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 사상의 범위 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러가지 변형이 가능하다. The present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made by those skilled in the art within the scope of the technical idea of the present invention. Do.
도 1a 내지 도 1f는 본 발명의 제1 실시예에 따른 반도체 소자의 비아 콘택 형성 방법을 설명하기 위하여 공정 순서에 따라 도시한 단면도들이다. 1A to 1F are cross-sectional views illustrating a method of forming a via contact in a semiconductor device according to a first embodiment of the present invention in a process sequence.
도 2a 내지 도 2f는 본 발명의 제2 실시예에 따른 반도체 소자의 비아 콘택 형성 방법을 설명하기 위하여 공정 순서에 따라 도시한 단면도들이다. 2A through 2F are cross-sectional views illustrating a method of forming a via contact in a semiconductor device according to a second exemplary embodiment of the present invention in a process sequence.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
110 : 반도체 기판, 120 : 배선층110: semiconductor substrate, 120: wiring layer
120a : 배선층 패턴, 122 : 제1 배리어층120a: wiring layer pattern, 122: first barrier layer
122a : 제1 배리어층 패턴, 124a : 제2 배리어층 패턴122a: first barrier layer pattern, 124a: second barrier layer pattern
130 : 금속 층간 절연막, 132 : 비아 홀130: metal interlayer insulating film, 132: via hole
134 : 앵커 홀, 134a : 언더컷 영역134: anchor hole, 134a: undercut area
140 : 콘택 플러그, 140a : 측방향 돌출부140: contact plug, 140a: lateral protrusion
Claims (8)
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| KR10-1998-0028414A KR100524905B1 (en) | 1998-07-14 | 1998-07-14 | Method for forming anchored via contact |
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| Application Number | Priority Date | Filing Date | Title |
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| KR10-1998-0028414A KR100524905B1 (en) | 1998-07-14 | 1998-07-14 | Method for forming anchored via contact |
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| KR100524905B1 true KR100524905B1 (en) | 2005-12-21 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4943539A (en) * | 1989-05-09 | 1990-07-24 | Motorola, Inc. | Process for making a multilayer metallization structure |
| KR0162140B1 (en) * | 1994-12-30 | 1999-02-01 | 김주용 | Formation method of contact hole |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4943539A (en) * | 1989-05-09 | 1990-07-24 | Motorola, Inc. | Process for making a multilayer metallization structure |
| KR0162140B1 (en) * | 1994-12-30 | 1999-02-01 | 김주용 | Formation method of contact hole |
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