KR100514425B1 - Bonding material, semiconductor device, method of manufacturing semiconductor device, circuit board and electronic device - Google Patents

Bonding material, semiconductor device, method of manufacturing semiconductor device, circuit board and electronic device Download PDF

Info

Publication number
KR100514425B1
KR100514425B1 KR10-2000-7011579A KR20007011579A KR100514425B1 KR 100514425 B1 KR100514425 B1 KR 100514425B1 KR 20007011579 A KR20007011579 A KR 20007011579A KR 100514425 B1 KR100514425 B1 KR 100514425B1
Authority
KR
South Korea
Prior art keywords
resin
semiconductor chip
layer
adhesive member
substrate
Prior art date
Application number
KR10-2000-7011579A
Other languages
Korean (ko)
Other versions
KR20010042822A (en
Inventor
노부아키 하시모토
Original Assignee
세이코 엡슨 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 세이코 엡슨 가부시키가이샤 filed Critical 세이코 엡슨 가부시키가이샤
Publication of KR20010042822A publication Critical patent/KR20010042822A/en
Application granted granted Critical
Publication of KR100514425B1 publication Critical patent/KR100514425B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05671—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29075—Plural core members
    • H01L2224/2908—Plural core members being stacked
    • H01L2224/29082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/29386—Base material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

반도체 장치(1)는, 반도체 칩(10)과, 배선 패턴(22)이 형성된 기판(2O)과, 반도체 칩(1O)과 배선 패턴(22)을 전기적으로 접속하는 접착 부재(3O)를 포함하며, 접착 부재(3O)는, 제 1 수지를 기재로 하여 반도체 칩(10)측에 배치되는 제 1 층(32)과, 제 2 수지를 기재로 하여 기판(2O)측에 배치되는 제 2 층(34)을 포함하고, 제 1 수지와 제 2 수지가, 열팽창 계수 등으로 다른 물성을 갖는다. The semiconductor device 1 includes a semiconductor chip 10, a substrate 20 on which the wiring pattern 22 is formed, and an adhesive member 30 that electrically connects the semiconductor chip 10 and the wiring pattern 22. The adhesive member 30 includes a first layer 32 disposed on the semiconductor chip 10 side based on the first resin and a second layer disposed on the substrate 20 side based on the second resin. The layer 34 is included, and the first resin and the second resin have different physical properties by a thermal expansion coefficient or the like.

Description

접착 부재, 반도체 장치 및 그 제조 방법, 회로 기판 및 전자 기기{Bonding material, semiconductor device, method of manufacturing semiconductor device, circuit board and electronic device}Bonding material, semiconductor device and manufacturing method thereof, circuit board and electronic device TECHNICAL FIELD

본 발명은, 접착 부재, 반도체 장치 및 그 제조 방법, 회로 기판 및 전자 기기에 관한 것이다.TECHNICAL FIELD This invention relates to an adhesive member, a semiconductor device, its manufacturing method, a circuit board, and an electronic device.

반도체 칩과 기판은 열팽창 계수에 있어서 크게 다른 것이 많으며, 특히 가열 후에 냉각되었을 때에, 열팽창 계수의 차에 의해 생기는 응력이 접착 부재에 가해진다. 그리고, 접착 부재의 박리가 생길 가능성이 있었다.A semiconductor chip and a board | substrate are largely different in thermal expansion coefficient, and especially when it cools after heating, the stress which arises by the difference of a thermal expansion coefficient is applied to an adhesive member. And there exists a possibility that peeling of an adhesive member may arise.

또한, 예를 들면 접착 부재로서 이방성 도전 접착 부재를 사용한 경우에는, 반도체 칩 및 기판에 의해 이방성 도전막을 가압했을 때에, 반도체 칩의 범프와, 기판에 형성된 배선 패턴과의 사이에 도전 입자를 남겨서 절연 수지를 유출시키는 것이 어려운 경우가 있었다.For example, when an anisotropic conductive adhesive member is used as the adhesive member, when the anisotropic conductive film is pressed by the semiconductor chip and the substrate, the conductive particles are left insulated between the bumps of the semiconductor chip and the wiring pattern formed on the substrate. In some cases, it was difficult to let the resin out.

이러한 문제는, 접착 부재의 양면에 대하여 다른 성질이 요구되는 것에 기인하지만, 종래의 접착 부재는 이것에 대응되지 않았다.This problem is due to the fact that different properties are required for both surfaces of the adhesive member, but the conventional adhesive member does not correspond to this.

본 발명은, 상술한 바와 같은 과제를 해결하는 것으로, 그 목적은, 양면에 대한 다른 성질의 요구에 대응할 수 있는 접착 부재, 이것을 사용한 반도체 장치 및 그 제조 방법, 회로 기판 및 전자 기기를 제공하는 것에 있다.SUMMARY OF THE INVENTION The present invention solves the above problems, and an object thereof is to provide an adhesive member capable of responding to demands of different properties on both sides, a semiconductor device using the same, a manufacturing method thereof, a circuit board, and an electronic device. have.

도 1a 내지 도 1c는, 본 발명의 실시예에 따른 반도체 장치의 제조 방법을 도시한 도면.1A to 1C show a method of manufacturing a semiconductor device according to the embodiment of the present invention.

도 2는, 본 발명의 실시예에 따른 회로 기판을 도시한 도면.2 illustrates a circuit board according to an embodiment of the present invention.

도 3은 본 발명에 따른 방법을 적용하여 제조된 반도체 장치를 구비하는 전자 기기를 도시한 도면.3 illustrates an electronic device having a semiconductor device manufactured by applying the method according to the present invention.

(1) 본 발명에 따른 접착 부재는, 전자부품을 접착하기 위해 사용되고, 두께 방향에 있어서 물성(物性)이 다르다.(1) The adhesive member according to the present invention is used for adhering electronic components, and has different physical properties in the thickness direction.

이것에 의하면, 접착 부재의 양면에 있어서 물성이 다르므로, 각각의 면에 접착되는 재료에 적합하도록 구성할 수 있다.According to this, since physical properties differ in both surfaces of an adhesive member, it can be comprised so that it may be suitable for the material adhere | attached on each surface.

(2) 상기 접착 부재는, 이방성 도전막이어도 된다.(2) The adhesive member may be an anisotropic conductive film.

이방성 도전막이어도, 각각의 면에 접착되는 재료에 적합하도록 구성할 수 있다.Even if it is an anisotropic conductive film, it can be comprised so that it may be suitable for the material adhere | attached on each surface.

(3) 상기 접착 부재는, 제 1 수지를 기재(基材)로 하는 제 1 층과, 제 2 수지를 기재로 하는 제 2 층의 2 층 구조를 이루고, 상기 제 1 수지와 상기 제 2 수지가 다른 물성을 가져도 된다.(3) The said adhesive member comprises the 2 layer structure of the 1st layer which uses a 1st resin as a base material, and the 2nd layer which uses a 2nd resin as a base material, The said 1st resin and said 2nd resin May have different physical properties.

이것에 의하면, 제 1 층을 구성하는 제 1 수지와, 제 2 층을 구성하는 제 2 수지가 다른 물성을 갖는다. 따라서, 제 1 층에 밀착하는 부재와, 제 2 층에 밀착하는 부재의 각각에 적합한 물성을 갖도록, 제 1 수지와 제 2 수지를 선택할 수 있다.According to this, the 1st resin which comprises a 1st layer, and the 2nd resin which comprises a 2nd layer have different physical properties. Therefore, a 1st resin and a 2nd resin can be selected so that it may have a physical property suitable for each of the member which adheres to a 1st layer, and a member which adheres to a 2nd layer.

(4) 상기 접착 부재에 있어서,(4) In the adhesive member,

상기 제 1 수지의 열팽창 계수는, 상기 제 2 수지의 열팽창 계수보다도 작아도 된다.The thermal expansion coefficient of the first resin may be smaller than the thermal expansion coefficient of the second resin.

이것에 의하면, 열팽창 계수가 작은 부재에 제 1 층이 밀착하고, 열팽창 계수가 큰 부재에 제 2 층이 밀착했을 때에, 제 1 및 제 2 수지가 각각에 대응한 열팽창 계수를 갖기 때문에, 박리가 생기기 어렵게 되어 있다.According to this, when a 1st layer adheres to a member with a small coefficient of thermal expansion, and a 2nd layer adheres to a member with a large coefficient of thermal expansion, since 1st and 2nd resin have a thermal expansion coefficient corresponding to each, peeling is performed. It is hard to occur.

(5) 상기 접착 부재에 있어서,(5) In the adhesive member,

상기 제 1 수지에만 실리카계 필러가 혼입되어도 된다. The silica filler may be mixed only with the first resin.

이렇게 함으로써, 제 1 수지의 열팽창 계수를 작게, 상세하게는 실리콘의 열팽창 계수에 근접하게 할 수 있다.By doing in this way, the thermal expansion coefficient of a 1st resin can be made small, and it can be approximated to the thermal expansion coefficient of silicon in detail.

(6) 상기 접착 부재에 있어서,(6) In the adhesive member,

상기 제 1 수지 및 상기 제 2 수지에는, 실리카계 필러가 혼입되고, 상기 제 1 수지에 대한 상기 실리카계 필러의 혼입율이, 제 2 수지에 대한 상기 실리카계 필러의 혼입율보다도 커도 된다. Silica filler may be mixed in the first resin and the second resin, and the mixing ratio of the silica filler to the first resin may be larger than the mixing ratio of the silica filler to the second resin.

이렇게 함으로써, 제 2 수지의 열팽창 계수보다도, 제 1 수지의 열팽창 계수를 작게, 상세하게는 실리콘의 열팽창 계수에 근접하게 할 수 있다.By doing in this way, the thermal expansion coefficient of a 1st resin can be made smaller than the thermal expansion coefficient of a 2nd resin, and can be closer to the thermal expansion coefficient of silicon in detail.

(7) 상기 접착 부재에 있어서,(7) In the adhesive member,

상기 제 1 수지보다도, 상기 제 2 수지는, 저탄성화되어 있어도 된다. The second resin may be lower elasticized than the first resin.

이렇게 함으로써, 제 2 층이 열팽창 계수가 큰 부재에 밀착하였을 때에, 제 2 수지가 신장하기 용이하여 추종성이 높기 때문에, 박리가 생기기 어렵게 된다.By doing in this way, when a 2nd layer adheres to the member with a large coefficient of thermal expansion, since a 2nd resin is easy to extend | stretch and its followability is high, it becomes difficult to produce peeling.

(8) 상기 접착 부재에 있어서,(8) In the adhesive member,

상기 제 2 수지는, 변성된 에폭시 수지이어도 된다.The modified second resin may be the second resin.

이로써, 제 2 수지를 저탄성화할 수 있다.Thereby, 2nd resin can be made low elastic.

(9) 상기 접착 부재에 있어서,(9) In the adhesive member,

상기 제 1 수지는, 에폭시 수지이고,The first resin is an epoxy resin,

상기 제 2 수지는, 비페닐 수지이어도 된다. Biphenyl resin may be sufficient as said 2nd resin.

이로써, 제 2 수지가 제 1 수지보다도 저탄성화한다.As a result, the second resin is lower elastic than the first resin.

(10) 상기 접착 부재에 있어서,(10) In the adhesive member,

상기 제 2 수지에만, 도전 입자가 분산되어 있어도 된다.Electroconductive particle may be disperse | distributed only to the said 2nd resin.

이렇게 함으로써, 제 1 층에 밀착하는 부재의 표면에는, 도전 입자가 접촉하지 않으므로 전기적인 단락이 생기지 않는다.By doing so, since the conductive particles do not contact the surface of the member in close contact with the first layer, no electrical short occurs.

(11) 상기 접착 부재에 있어서,(11) In the adhesive member,

도전 입자가 상기 제 2 수지에만 분산되고,Conductive particles are dispersed only in the second resin,

상기 제 2 층은 상기 제 1 층보다도 두께가 얇고, 상기 제 2 수지는, 용융되었을 때의 점도가 상기 제 1 수지보다도 높아도 된다. The said 2nd layer may be thinner than the said 1st layer, and the viscosity at the time of melt | dissolution of the said 2nd resin may be higher than the said 1st resin.

이것에 의하면, 제 2 수지에만 도전 입자가 분산되어 있으므로, 제 1 층에 밀착하는 부재의 표면에는, 도전 입자가 접촉하지 않기 때문에 전기적인 단락이 생기지 않는다. 또한, 제 2 층이 제 1 층보다도 얇기 때문에, 도전 입자의 수를 감소시켜 전기적인 단락을 방지할 수 있다. 또한, 도전 입자의 수가 적음에도 불구하고, 제 2 수지의 용융 점도가 높은 것으로, 도전 입자를 확실하게 잔존시킬 수 있다. 한편으로, 제 2 수지보다도 용융 점도가 낮은 제 1 수지는 쉽게 유출시키게 되어 있다.According to this, since electroconductive particle is disperse | distributed only to 2nd resin, since an electroconductive particle does not contact the surface of the member which adjoins to a 1st layer, an electrical short circuit does not arise. In addition, since the second layer is thinner than the first layer, the number of conductive particles can be reduced to prevent electrical short circuit. In addition, despite the small number of the conductive particles, the melt viscosity of the second resin is high, so that the conductive particles can be reliably left. On the other hand, 1st resin with a melt viscosity lower than 2nd resin is made to flow out easily.

(12) 상기 접착 부재에 있어서,(12) In the adhesive member,

상기 제 2 수지에만 실리커계 필러가 혼입되어도 된다.Silica-based filler may be mixed only in the second resin.

이렇게 함으로써, 제 2 수지의 용융 점도를 높일 수 있다.By doing in this way, the melt viscosity of a 2nd resin can be raised.

(13) 상기 접착 부재에 있어서,(13) In the adhesive member,

상기 제 1 수지 및 상기 제 2 수지에는, 실리카계 필러가 혼입되고, 상기 제 2 수지에 대한 상기 실리카계 필러의 혼입율이, 제 1 수지에 대한 상기 실리카계 필러의 혼입율보다도 커도 된다. Silica filler may be mixed in the first resin and the second resin, and the mixing ratio of the silica filler to the second resin may be larger than the mixing ratio of the silica filler to the first resin.

이렇게 함으로써, 제 2 수지의 용융 점도를 올릴 수 있다.By doing in this way, the melt viscosity of a 2nd resin can be raised.

(14) 상기 접착 부재에 있어서,(14) In the adhesive member,

상기 제 2 수지는, 상기 제 1 수지보다도 분자량이 커도 된다.The second resin may have a higher molecular weight than the first resin.

이렇게 함으로써, 제 2 수지의 용융 점도를 올릴 수 있다.By doing in this way, the melt viscosity of a 2nd resin can be raised.

(15) 본 발명에 따른 반도체 장치는, 반도체 칩과, 배선 패턴이 형성된 기판과, 상기 반도체 칩과 상기 배선 패턴을 전기적으로 접속하는 접착 부재를 포함하며,(15) A semiconductor device according to the present invention includes a semiconductor chip, a substrate on which a wiring pattern is formed, and an adhesive member for electrically connecting the semiconductor chip and the wiring pattern,

상기 접착 부재는, 두께 방향에 있어서 물성이 다르다.The said adhesive member differs in physical property in the thickness direction.

이것에 의하면, 접착 부재의 양면에서 물성이 다르므로, 각각의 면에 접착되는 재료에 적합하도록 구성할 수 있다.According to this, since physical properties differ in both surfaces of an adhesive member, it can be comprised so that it may be suitable for the material adhere | attached on each surface.

(16) 상기 반도체 장치에 있어서,(16) In the above semiconductor device,

상기 접착 부재는, 이방성 도전막이어도 된다.The adhesive member may be an anisotropic conductive film.

이방성 도전막이라도, 각각의 면에 접착되는 재료에 적합하도록 구성할 수 있다.Even an anisotropic conductive film can be comprised so that it may be suitable for the material adhere | attached on each surface.

(17) 상기 반도체 장치에 있어서, (17) In the semiconductor device,

상기 접착 부재는, 제 1 수지를 기재로서 상기 반도체 칩측에 배치되는 제 1 층과, 제 2 수지를 기재로서 상기 기판 측에 배치되는 제 2 층의 2 층 구조를 이루고, 상기 제 1 수지와 상기 제 2 수지가 다른 물성을 가져도 된다.The adhesive member forms a two-layer structure of a first layer disposed on the semiconductor chip side using a first resin and a second layer disposed on the substrate side using a second resin, wherein the first resin and the The second resin may have different physical properties.

이것에 의하면, 접착 부재의 제 1 층을 구성하는 제 1 수지와, 제 2 층을 구성하는 제 2 수지가 다른 물성을 갖는다. 따라서, 제 1 층에 밀착하는 반도체 칩과, 제 2 층에 밀착하는 기판의 각각에 적합한 물성을 갖도록, 제 1 수지와 제 2 수지를 선택할 수 있다.According to this, the 1st resin which comprises the 1st layer of an adhesive member, and the 2nd resin which comprises a 2nd layer have different physical properties. Therefore, the first resin and the second resin can be selected so as to have suitable physical properties for each of the semiconductor chip in close contact with the first layer and the substrate in close contact with the second layer.

(18) 상기 반도체 장치에 있어서, (18) In the above semiconductor device,

상기 접착 부재는, 상술한 접착 부재이어도 된다.The adhesive member described above may be the adhesive member.

(19) 본 발명에 따른 회로 기판에는, 상기 반도체 장치가 탑재되어 있다.(19) The semiconductor device is mounted on a circuit board according to the present invention.

(20) 본 발명에 따른 전자 기기는, 상기 반도체 장치를 구비한다.(20) An electronic device according to the present invention includes the semiconductor device.

(21) 본 발명에 따른 반도체 장치의 제조 방법은, 반도체 칩과, 배선 패턴이 형성된 기판의 상기 배선 패턴 사이에 접착 부재를 형성하여, 상기 반도체 칩과 상기 기판을 가압하여, 상기 반도체 칩과 배선 패턴을 전기적으로 접속하는 공정을 포함하며, (21) In the method for manufacturing a semiconductor device according to the present invention, an adhesive member is formed between a semiconductor chip and the wiring pattern of a substrate on which a wiring pattern is formed, and the semiconductor chip and the substrate are pressed to press the semiconductor chip and the wiring. A step of electrically connecting the pattern,

상기 접착 부재는, 두께 방향에 있어서 물성이 다르다.The said adhesive member differs in physical property in the thickness direction.

이것에 의하면, 접착 부재의 양면에서 물성이 다르므로, 각각의 면에 접착되는 재료에 적합하도록 구성할 수 있다.According to this, since physical properties differ in both surfaces of an adhesive member, it can be comprised so that it may be suitable for the material adhere | attached on each surface.

(22) 상기 반도체 장치의 제조 방법에 있어서,(22) In the method for manufacturing the semiconductor device,

상기 접착 부재는, 이방성 도전막이어도 된다.The adhesive member may be an anisotropic conductive film.

이방성 도전막이라도, 각각의 면에 접착되는 재료에 적합하도록 구성할 수 있다.Even an anisotropic conductive film can be comprised so that it may be suitable for the material adhere | attached on each surface.

(23) 상기 반도체 장치의 제조 방법에 있어서,(23) In the method for manufacturing the semiconductor device,

상기 접착 부재를, 제 1 수지를 기재로 하는 제 1 층과, 상기 제 1 수지와는 다른 물성을 갖는 제 2 수지를 기재로 하는 제 2 층의 2 층 구조로 형성하여도 된다.The adhesive member may be formed in a two-layer structure of a first layer based on a first resin and a second layer based on a second resin having physical properties different from those of the first resin.

이것에 의하면, 접착 부재의 제 1 층을 구성하는 제 1 수지와, 제 2 층을 구성하는 제 2 수지가 다른 물성을 갖는다. 따라서, 반도체 칩 및 기판에 밀착하는 데 적합한 물성을 갖도록, 제 1 수지와 제 2 수지를 선택할 수 있다.According to this, the 1st resin which comprises the 1st layer of an adhesive member, and the 2nd resin which comprises a 2nd layer have different physical properties. Therefore, the first resin and the second resin can be selected to have suitable physical properties for close contact with the semiconductor chip and the substrate.

(24) 상기 반도체 장치의 제조 방법에 있어서,(24) In the method for manufacturing the semiconductor device,

상기 제 1 및 제 2 층을 순차로 형성하여도 된다.The said 1st and 2nd layer may be formed in order.

(25) 상기 반도체 장치의 제조 방법에 있어서,(25) In the method of manufacturing the semiconductor device,

상기 제 1 층을 상기 반도체 칩측에 배치하고, 상기 제 2 층을 상기 기판 측에 배치하여도 된다.The first layer may be disposed on the semiconductor chip side, and the second layer may be disposed on the substrate side.

이것에 의하면, 제 1 층에 밀착하는 반도체 칩과, 제 2 층에 밀착하는 기판의 각각에 적합한 물성을 갖도록, 제 1 수지와 제 2 수지를 선택할 수 있다.According to this, 1st resin and 2nd resin can be selected so that it may have a physical property suitable for each of the semiconductor chip which adheres to a 1st layer, and the board | substrate which adheres to a 2nd layer.

(26) 상기 반도체 장치의 제조 방법에 있어서,(26) The method of manufacturing the semiconductor device,

상기 접착 부재는, 상술한 접착 부재이어도 된다. The adhesive member described above may be the adhesive member.

이하, 본 발명의 적합한 실시예에 대해서 도면을 참조하여 설명한다.Best Mode for Carrying Out the Invention Preferred embodiments of the present invention will now be described with reference to the drawings.

도 1a 내지 도 1c는, 본 발명의 실시예에 따른 반도체 장치의 제조 방법을 도시한 도면이다. 도 1c에는, 그 제조 방법에 의해서 완성한 반도체 장치(1)가 도시되어 있다.1A to 1C illustrate a method of manufacturing a semiconductor device according to an embodiment of the present invention. In FIG. 1C, the semiconductor device 1 completed by the manufacturing method is shown.

반도체 장치(1)는, 반도체 칩(10)과, 기판(20)을 포함한다. 반도체 칩(10)의 평면 형상이 구형(정방형 또는 직사각형)인 경우에는, 적어도 1변(대향하는 2변 또는 모든 변을 포함)에 따라서, 반도체 칩(10)의 한면(능동면)에 복수의 전극(12)이 형성되어 있다. 또는, 반도체 칩(10)의 한쪽 면의 중앙에 복수의 전극(12)을 형성하여도 된다. 전극(12)에는, 숄더 볼, 금 와이어 볼, 금도금 등에 의해서 범프(14)가 설치되는 것이 많지만, 이것은 필수가 아니다. 전극(12) 자체가 범프의 형상을 이루고 있어도 된다. 전극(12)과 범프(14)와의 사이에 범프 금속의 확산 방지층으로서, 니켈, 크롬, 티타늄 등을 부가하여도 된다.The semiconductor device 1 includes a semiconductor chip 10 and a substrate 20. In the case where the planar shape of the semiconductor chip 10 is spherical (square or rectangular), a plurality of surfaces are formed on one side (active surface) of the semiconductor chip 10 along at least one side (including two opposite sides or all sides). The electrode 12 is formed. Alternatively, a plurality of electrodes 12 may be formed in the center of one surface of the semiconductor chip 10. Although the bump 14 is often provided in the electrode 12 by a shoulder ball, a gold wire ball, gold plating, etc., this is not essential. The electrode 12 itself may form the bump shape. Nickel, chromium, titanium, or the like may be added as the diffusion barrier layer of the bump metal between the electrode 12 and the bump 14.

기판(20)의 전체 형상은 특별히 한정되지 않고, 구형, 다각형, 또는 복수의 구형을 조합한 형상 중 어느 것이어도 되지만, 반도체 칩(10)의 평면형상의 상사형으로 할 수 있다. 기판(20)의 두께는, 그 재질에 의해 결정되는 것이 많지만, 이것도 한정되지 않는다. 기판(20)은 유기계 또는 무기계 중 어느 것의 재료로 형성된 것이어도 되고, 이들의 복합 구조로 이루어지는 것이어도 되지만, 천공하는 것이 바람직하다. 유기계의 재료로 형성된 테이프형상의 플렉시블 기판을 천공하여 기판(20)을 형성할 수 있다.Although the overall shape of the board | substrate 20 is not specifically limited, Any of the shape which combined the spherical shape, polygonal shape, or some spherical shape may be sufficient, but it can be set as the planar similar shape of the semiconductor chip 10. FIG. Although the thickness of the board | substrate 20 is determined by the material in many cases, this is not limited, either. Although the board | substrate 20 may be formed from the material of any organic type or inorganic type, and may be comprised from these composite structures, it is preferable to perforate. The substrate 20 may be formed by punching a tape-shaped flexible substrate formed of an organic material.

기판(20)으로서, 다층 기판이나 빌드업형 기판을 사용하여도 된다. 빌드업형 기판이나 다층 기판을 이용한 경우, 평면적으로 확대되는 전체 그라운드층상에 배선 패턴을 형성하면, 여분의 배선 패턴이 없는 마이크로스트립 구조로 되므로, 신호의 전송 물성을 향상시킬 수 있다.As the substrate 20, a multilayer substrate or a buildup type substrate may be used. In the case of using a build-up type substrate or a multi-layer substrate, when the wiring pattern is formed on the entire ground layer that is enlarged in a planar manner, the structure becomes a microstrip structure with no extra wiring pattern, thereby improving signal transmission properties.

기판(20)의 한쪽 면에는, 복수의 배선(리드)이 형성되어, 배선 패턴(22)을 구성하고 있다. 복수의 배선 중 적어도 하나 또는 모두는, 다른 배선과 전기적으로 도통되어 있지 않고, 전기적으로 독립하고 있다. 또는, 복수의 배선 중, 반도체 칩(10)의 전원이나 그라운드 등 공통의 장소에 접속되는 것은, 서로 접속되어 있어도 된다. 각각의 배선 양단에는, 그라운드부가 형성되어 있다. 그라운드부는, 그 사이를 접속하는 부분보다도 큰 폭을 갖도록 형성되어 있는 것이 많다. 한쪽의 그라운드부를 기판(20)의, 최종적인 제품으로서의 반도체 장치의 단부에 가까운 위치에 형성하고, 다른 쪽의 그라운드부를 기판(20)의 중앙에 가까운 위치에 형성하여도 된다. 배선 패턴(22)에 있어서의 반도체 칩(10)의 전극(12)과 접합되는 부분(예를 들면 그라운드부)에, 범프가 형성되어 있어도 된다. 그 경우에, 반도체 칩(10)의 범프(14)를 생략할 수 있다.A plurality of wirings (leads) are formed on one surface of the substrate 20 to form the wiring pattern 22. At least one or both of the plurality of wirings are not electrically connected to other wirings and are electrically independent of each other. Alternatively, the plurality of wirings may be connected to a common place such as a power supply or a ground of the semiconductor chip 10. Ground portions are formed at both ends of each wiring. In many cases, the ground portion is formed to have a larger width than the portion that connects therebetween. One ground portion may be formed at a position near the end of the semiconductor device as the final product of the substrate 20, and the other ground portion may be formed at a position near the center of the substrate 20. The bump may be formed in the part (for example, ground part) joined to the electrode 12 of the semiconductor chip 10 in the wiring pattern 22. In that case, the bump 14 of the semiconductor chip 10 can be omitted.

기판(20)에는, 복수의 스루 홀(24)이 형성되어 있다. 각각의 스루 홀(24) 상을, 어느 하나의 배선이 통과하도록, 배선 패턴(22)은 형성되어 있다. 배선의 단부가 스루 홀(24)상에 위치하여도 된다. 배선의 단부에 그라운드부가 형성되어 있는 경우에는, 그라운드부가 스루 홀(24)상에 위치한다.A plurality of through holes 24 are formed in the substrate 20. The wiring pattern 22 is formed so that any one wire may pass through each through hole 24. An end portion of the wiring may be located on the through hole 24. When the ground portion is formed at the end of the wiring, the ground portion is positioned on the through hole 24.

도 1c에 도시한 바와 같이, 기판(20)에는 외부단자(40)가 형성되어 있다. 숄더 볼을 외부단자(40)로 하여도 된다. 외부단자(40)는 배선 패턴(22)에 전기적으로 접속되어 있다. 예를 들면, 스루 홀(24)내에 도금 등으로 도전부재를 형성하거나, 스루 홀 내에 숄더 볼을 형성하기도 하여, 외부단자(40)를 배선 패턴(22)에 전기적으로 접속할 수 있다. As shown in FIG. 1C, the external terminal 40 is formed on the substrate 20. The shoulder ball may be used as the external terminal 40. The external terminal 40 is electrically connected to the wiring pattern 22. For example, a conductive member may be formed in the through hole 24 by plating or the like, or a shoulder ball may be formed in the through hole so that the external terminal 40 can be electrically connected to the wiring pattern 22.

배선 패턴(22)에는, 도금이 실시되어 있다. 배선 패턴(22)을 구리로 형성하고, 니켈, 금, 땜납 또는 주석으로 도금을 실시할 수 있다. 도금을 실시함으로써, 도전성이 확보된다. 구체적으로는 외부단자(40)와의 양호한 납땜이 가능하게 되어, 배선의 표면의 산화가 방지되어, 범프와의 전기적인 접속 저항이 저하한다.The wiring pattern 22 is plated. The wiring pattern 22 is formed of copper, and plating can be performed with nickel, gold, solder or tin. By plating, electroconductivity is ensured. Specifically, good soldering with the external terminal 40 is enabled, oxidation of the surface of the wiring is prevented, and electrical connection resistance with the bumps is lowered.

반도체 칩(10)은 기판(20)에 대하여 페이스다운 실장된다. 반도체 칩(10)의 범프(14)와, 기판(20)에 형성된 배선 패턴(22)이 전기적으로 접속된다. 본 발명에서는, 상술한 외부단자(40)는, 반드시 필요하지 않다. 최저한, 반도체 칩(10)과 마주 대하는 배선 패턴(22)이 형성된 기판(20)이 있고, 그 사이에 접착 부재(30)가 존재하는 구성이면 된다. 접착 부재(30)도 최저한, 절연성을 갖고 있는 수지(언더필 수지)이면 되고, 이방성 도전성을 갖는 수지이어도 된다. 반도체 칩(1O)의 범프(14)와, 기판(20)의 배선 패턴(22)의 페이스다운 접합은, 땜납 등 로우재 등에 의한 금속간 접합에 의한 방법, 수지의 수축을 이용하여 기계적인 접합 강도를 유지하는 방법, 금 범프 장착의 반도체 칩을 가열·가압하는 방법(필요에 따라서 초음파 접합한다), 이방성 도전막을 사용하는 방법 등이 알려져 있고, 어떤 방법을 적용하여도 된다.The semiconductor chip 10 is face-down mounted on the substrate 20. The bump 14 of the semiconductor chip 10 and the wiring pattern 22 formed on the substrate 20 are electrically connected. In the present invention, the external terminal 40 described above is not necessarily required. At least, the board | substrate 20 in which the wiring pattern 22 facing the semiconductor chip 10 was formed may be sufficient, and what is necessary is just the structure which the adhesive member 30 exists between. The adhesive member 30 may also be a resin having minimum insulation (underfill resin) or a resin having anisotropic conductivity. The face-down bonding of the bump 14 of the semiconductor chip 10 and the wiring pattern 22 of the substrate 20 is performed by mechanical bonding using a method of intermetal bonding by a raw material such as solder or the shrinkage of resin. A method of maintaining strength, a method of heating and pressing a semiconductor chip with gold bumps (sonic bonding as necessary), a method of using an anisotropic conductive film, and the like are known, and any method may be applied.

접착 부재(30)는, 제 1 층(32) 및 제 2 층(34)의 2 층 구조를 이룬다. 제 1 층(32)은 제 1 수지로 구성되고, 제 2 층(34)은 제 2 수지로 구성된다. 본 실시예에서는, 제 1 수지와 제 2 수지가 다른 물성을 갖는다. 도 1a에는, 접착 부재(30)로서, 이방성 도전막을 사용한 예가 도시되어 있다. 접착 부재(30)는 바인더에 도전 입자(36)가 분산되어진다. The adhesive member 30 has a two-layer structure of the first layer 32 and the second layer 34. The first layer 32 is composed of the first resin, and the second layer 34 is composed of the second resin. In this embodiment, the first resin and the second resin have different physical properties. FIG. 1A shows an example in which an anisotropic conductive film is used as the adhesive member 30. The conductive member 36 is dispersed in the adhesive member 30 in the binder.

(열팽창 계수가 다른 경우) (When the coefficient of thermal expansion is different)

제 1 수지의 열팽창 계수(예를 들면 20 내지 4O(1O-6/℃))가, 제 2 수지의 열팽창 계수(예를 들면 4O 내지 2OO(1O-6/℃))보다도 작아도 된다. 제 1 수지로 구성되는 제 1 층(32)은 반도체 칩(10)에 밀착하고, 제 2 수지로 구성되는 제 2 층(34)은, 기판(20)에 밀착한다. 여기서, 반도체 칩(10)은 열팽창 계수가 작은 재료(예를 들면 실리콘 등)로 구성되는 것이 많고, 기판(20)은, 열팽창 계수가 많은 재료(예를 들면 폴리이미드 수지 등)로 구성되는 것이 많다.The thermal expansion coefficient of the first resin (for example, 20 to 40 (10 -6 / ° C)) may be smaller than the thermal expansion coefficient of the second resin (for example, 40 to 20 (10 -6 / ° C)). The first layer 32 made of the first resin is in close contact with the semiconductor chip 10, and the second layer 34 made of the second resin is in close contact with the substrate 20. Here, the semiconductor chip 10 is often made of a material having a small thermal expansion coefficient (for example, silicon), and the substrate 20 is made of a material having a large thermal expansion coefficient (for example, a polyimide resin or the like). many.

열팽창 계수가 작은 제 1 수지로 구성되는 제 1 층(32)과, 열팽창 계수가 작은 반도체 칩(10) 사이에는, 열팽창 계수의 차가 작으므로, 접착 부재(30)의 박리가 생기기 어렵다. 제 1 수지의 열팽창 계수를 실리콘의 열팽창 계수에 근접하게 하기 위해서는, 제 1 수지에 실리카계 필러를 예를 들면 3O 내지 6O%의 혼입율로 혼입시켜도 된다. 그 경우에는, 제 2 수지에는 실리카계 필러를 혼입시키지 않은 것이 바람직하다. 또는, 제 1 수지 및 제 2 수지에 실리카계 필러를 혼입하더라도, 제 1 수지에 대한 실리카계 필러의 혼입율이, 제 2 수지에 대한 실리카계 필러의 혼입율보다도 크면 된다. 그 경우, 실리카계 필러의 혼입율의 차가 3O 내지 60% 정도인 것이 바람직하다.Since the difference in thermal expansion coefficient is small between the 1st layer 32 comprised from the 1st resin with a small thermal expansion coefficient, and the semiconductor chip 10 with a small thermal expansion coefficient, peeling of the adhesive member 30 hardly occurs. In order to make the thermal expansion coefficient of the first resin close to the thermal expansion coefficient of silicon, the silica-based filler may be incorporated into the first resin at a mixing ratio of, for example, 30 to 60%. In that case, it is preferable that a silica filler is not mixed in 2nd resin. Alternatively, even if the silica filler is mixed into the first resin and the second resin, the mixing ratio of the silica filler to the first resin may be larger than the mixing ratio of the silica filler to the second resin. In that case, it is preferable that the difference of the content rate of a silica filler is about 30 to 60%.

열팽창 계수가 큰 제 2 수지로 구성되는 제 2 층(34)과, 열팽창 계수가 큰 기판(20) 사이에는, 열팽창 계수의 차가 작으므로, 접착 부재(30)의 박리가 생기기 어렵다.Since the difference in thermal expansion coefficient is small between the 2nd layer 34 comprised from the 2nd resin with a large thermal expansion coefficient, and the board | substrate 20 with a large thermal expansion coefficient, peeling of the adhesive member 30 hardly occurs.

접착 부재(30)로서 이방성 도전막을 사용하는 경우에, 제 1 및 제 2 수지의 열팽창 계수가 다른 경우에, 한쪽에만 도전 입자(36)를 분산시켜도 된다. 구체적으로는, 반도체 칩(10)의 범프(14)보다도 전기적 접속 면적이 큰 배선 패턴(22)에 밀착하는 제 2 층(34)에만, 도전 입자(36)를 분산시키는 것이 바람직하다. 이렇게 함으로써, 접착 부재(30)(이방성 도전막)에 범프(14)가 가라앉았을 때에, 범프(14)의 아래에 도전 입자(36)가 잔존할 확률이 높게 되어, 전기적 접속의 신뢰성이 높아진다. 또한, 반도체 칩(10)에 밀착하는 제 1 층(32)에 도전 입자(36)가 분산하지 않고 있으므로, 반도체 칩(10)의 전극(12)간의 단락이 방지된다. In the case where an anisotropic conductive film is used as the adhesive member 30, when the thermal expansion coefficients of the first and second resins are different, the conductive particles 36 may be dispersed only on one side. Specifically, it is preferable to disperse the conductive particles 36 only in the second layer 34 in close contact with the wiring pattern 22 having a larger electrical connection area than the bump 14 of the semiconductor chip 10. In this way, when the bump 14 sinks in the adhesive member 30 (anisotropic conductive film), the probability that the conductive particles 36 remain under the bump 14 is high, and the reliability of the electrical connection is increased. In addition, since the conductive particles 36 are not dispersed in the first layer 32 in close contact with the semiconductor chip 10, a short circuit between the electrodes 12 of the semiconductor chip 10 is prevented.

(탄성율이 다른 경우)(When elastic modulus is different)

제 1 수지보다도, 제 2 수지가 저탄성화되어 있어도 된다. 예를 들면, 제 1 수지의 탄성율이 약 3 내지 10(GPa)이고, 제 2 수지의 탄성율이 약 1 내지 3GPa이어도 된다. 이렇게 함으로써, 제 2 수지로 이루어지는 제 2 층(34)이, 열팽창 계수가 큰 기판(20)에 밀착하였을 때에, 제 2 수지가 신장하기 쉽고 추종성이 높으므로 박리가 생기기 어렵게 된다.The second resin may be lower elasticized than the first resin. For example, the elasticity modulus of 1st resin may be about 3-10 (GPa), and the elasticity modulus of 2nd resin may be about 1-3 GPa. By doing in this way, when the 2nd layer 34 which consists of 2nd resins adheres to the board | substrate 20 with a large coefficient of thermal expansion, since 2nd resin is easy to extend | stretch and is easy to follow, peeling will become difficult to occur.

제 2 수지를 저탄성화하기 위해서는, 에폭시 수지를 변성시켜 제 2 수지로 하여도 된다. 또는, 제 1 수지는 에폭시 수지이고, 제 2 수지는 비페닐 수지이어도 된다.In order to make a 2nd resin low elasticity, you may modify an epoxy resin to make it a 2nd resin. Alternatively, the first resin may be an epoxy resin, and the second resin may be a biphenyl resin.

접착 부재(30)로서 이방성 도전막을 사용하는 경우에, 제 1 및 제 2 수지의 탄성율이 다른 경우에도, 그 한쪽에만 도전 입자(36)를 분산시켜도 된다. 구체적으로는, 반도체 칩(10)의 범프(14)보다도, 전기적 접속 면적이 큰 배선 패턴(22)에 밀착하는 제 2 층(34)을 구성하는 제 2 수지에만, 도전 입자(36)를 분산시키는 것이 바람직하다. 이렇게 함으로써, 접착 부재(30)에 범프(14)가 가라앉았을 때에, 범프(14)의 아래에 도전 입자(36)가 잔존할 확률이 높게 되어, 전기적 접속의 신뢰성이 높아진다. 또한, 반도체 칩(10)에 밀착하는 제 1 층(32)을 형성하는 제 1 수지에 도전 입자(36)가 분산하지 않고 있기 때문에, 반도체 칩(10)의 전극(12)간의 단락이 방지된다.In the case of using an anisotropic conductive film as the adhesive member 30, even when the elastic modulus of the first and second resins is different, the conductive particles 36 may be dispersed only on one side thereof. Specifically, the conductive particles 36 are dispersed only in the second resin constituting the second layer 34 in close contact with the wiring pattern 22 having a larger electrical connection area than the bump 14 of the semiconductor chip 10. It is preferable to make it. By doing in this way, when the bump 14 sinks in the adhesive member 30, the possibility that the electrically-conductive particle 36 remains under bump 14 becomes high, and the reliability of electrical connection becomes high. In addition, since the conductive particles 36 are not dispersed in the first resin forming the first layer 32 in close contact with the semiconductor chip 10, a short circuit between the electrodes 12 of the semiconductor chip 10 is prevented. .

(용융 점도가 다른 경우)(If melt viscosity is different)

접착 부재(30)로서 이방성 도전막을 사용하는 경우에, 제 2 수지는, 용융하였을 때의 점도가 제 1 수지보다도 높아도 된다. 이것에 의하면, 접착 부재(30)에 범프(14)가 가라앉았을 때에, 용융 점도가 낮은 제 1 수지는 쉽게 유출하고, 용융 점도가 높은 제 2 수지는 유출하기 어렵다. 제 2 수지의 용융 점도가 높기 때문에, 배선 패턴(22)상에 도전 입자(36)가 잔존하기 쉽다. 이 경우, 배선 패턴(22)에 밀착하는 제 2 층(34)을 구성하는 제 2 수지에만 도전 입자(36)를 분산시켜도 된다. 반도체 칩(10)에 밀착하는 제 1 층(32)을 구성하는 제 1 수지에 도전 입자(36)가 분산하지 않고 있기 때문에, 반도체 칩(10)의 전극(12)간의 단락이 방지된다.In the case of using an anisotropic conductive film as the adhesive member 30, the viscosity of the second resin when melted may be higher than that of the first resin. According to this, when the bump 14 sinks in the adhesive member 30, the 1st resin with low melt viscosity will flow out easily, and the 2nd resin with high melt viscosity will not flow easily. Since the melt viscosity of the second resin is high, the conductive particles 36 are likely to remain on the wiring pattern 22. In this case, the conductive particles 36 may be dispersed only in the second resin constituting the second layer 34 in close contact with the wiring pattern 22. Since the conductive particles 36 are not dispersed in the first resin constituting the first layer 32 in close contact with the semiconductor chip 10, a short circuit between the electrodes 12 of the semiconductor chip 10 is prevented.

또한, 제 2 층(34)은 제 1 층(32)보다도 두께가 얇아도 된다. 이것에 의해, 도전 입자(36)의 수를 저감하여 전기적인 단락을 방지할 수 있고, 도전 입자(36)의 수가 적음에도 불구하고, 제 2 수지의 용융 점도가 높은 것으로, 도전 입자(36)를 확실하게 배선 패턴(22)상에 잔존시킬 수 있다.In addition, the second layer 34 may be thinner than the first layer 32. As a result, the number of the conductive particles 36 can be reduced to prevent electrical short-circuit, and although the number of the conductive particles 36 is small, the melt viscosity of the second resin is high and the conductive particles 36 are high. Can be reliably left on the wiring pattern 22.

접착 부재(30)로서 이방성 도전막을 사용하는 경우로, 제 2 수지의 용융 점도를 제 1 수지보다도 높게 하기 위해서는, 제 2 수지에만 실리카계 필러를 혼입하여도 된다. 또는, 제 1 수지 및 제 2 수지에 실리카계 필러를 혼입하고, 제 2 수지에 대한 실리카계 필러의 혼입율을, 제 1 수지에 대한 실리카계 필러의 혼입율보다도 크게 하여도 된다. 또는, 제 2 수지의 분자량을, 제 1 수지의 분자량보다도 크게 하여도 된다.When using an anisotropic conductive film as the adhesive member 30, in order to make the melt viscosity of 2nd resin higher than 1st resin, you may mix a silica filler only to 2nd resin. Alternatively, the silica filler may be mixed into the first resin and the second resin, and the mixing ratio of the silica filler to the second resin may be larger than the mixing ratio of the silica filler to the first resin. Alternatively, the molecular weight of the second resin may be larger than the molecular weight of the first resin.

이상, 본 실시예에 대해서, 2 층의 물성이 다른 수지에 대해서 기술하였지만, 보다 바람직하게는, 층간의 물성차가 단계적이 아니라 연속적으로 변화하고 있는 쪽이, 두께 방향의 물성차가 존재하지 않기 때문에 유익하다. 2 층 계면에서의 물성차에 의한 박리 등이 발생하기 어렵기 때문이다. 그러므로, 구체적으로는, 작은 차로서 물성이 다른 다층으로 이루어지는 수지나, 연속적으로 두께 방향에 있어서 물성이 변화하는 수지를 사용할 수 있다.As mentioned above, although the physical property of two layers was described about resin different from this Example, it is more preferable that the physical property difference between layers is continuously changing rather than being stepwise because there is no physical property difference of the thickness direction. Do. This is because peeling due to the difference in physical properties at the two-layer interface hardly occurs. Therefore, specifically, the resin which consists of a multilayer with a different physical property as a small difference, and resin which changes a physical property in thickness direction continuously can be used.

2 층의 이방성 도전막은 1 층의 이방성 도전막을 시트형상으로 작성한 후, 또한 그 층 위에, 별도의 물성을 갖는 1 층의 이방성 도전막을 시트형상으로 작성함으로써 얻어진다. 그 후의 취급은 1 층의 이방성 도전막과 동일하다. 다층인 경우에는, 이 작업을 반복한다. 연속적으로 두께 방향에 물성이 다른 이방성 도전막을 형성하기 위해서는, 2 층 또는 다층의 이방성 도전막을 작성할 때에 사용되는 용제에 의해서, 또는 약간의 가열에 의해서, 층간의 상호 확산을 생기게 한다. 이것에 의해서 연속층을 얻을 수 있다.The two-layer anisotropic conductive film is obtained by making one layer of the anisotropic conductive film in sheet form, and then creating one layer of the anisotropic conductive film having other physical properties in the form of a sheet on the layer. Subsequent handling is the same as that of the anisotropic conductive film of one layer. In the case of a multilayer, this operation is repeated. In order to continuously form anisotropic conductive films having different physical properties in the thickness direction, mutual diffusion between the layers is caused by a solvent used when preparing an anisotropic conductive film of two layers or a multilayer or by slight heating. Thereby, a continuous layer can be obtained.

본 실시예에 따른 반도체 장치는, 상기한 바와 같이 구성되어 있고, 이하 그 제조 방법을 설명한다.The semiconductor device according to the present embodiment is configured as described above, and the manufacturing method thereof will be described below.

도 1a에 도시한 바와 같이, 반도체 칩(10)의 전극(12)(또는 범프(14))이 형성된 면과, 기판(20)의 배선 패턴(22)이 형성된 면을 대향시켜 배치한다. 또한, 반도체 칩(10)과 기판(20) 사이에, 접착 부재(30)를 배치한다. 상세하게는, 제 1 층(32)을 반도체 칩(10)을 향하여, 제 2 층(34)을 기판(20)을 향해 접착 부재(30)를 형성한다. 또한, 접착 부재(30)는, 반도체 칩(10)과 기판(20) 중 어느 한쪽에 접착하는 것이 바람직하다.As shown in FIG. 1A, the surface on which the electrode 12 (or bump 14) of the semiconductor chip 10 is formed and the surface on which the wiring pattern 22 of the substrate 20 is formed are disposed to face each other. In addition, the adhesive member 30 is disposed between the semiconductor chip 10 and the substrate 20. Specifically, the adhesive member 30 is formed with the first layer 32 facing the semiconductor chip 10 and the second layer 34 facing the substrate 20. In addition, the adhesive member 30 is preferably bonded to either of the semiconductor chip 10 and the substrate 20.

접착 부재(30)가 복수층(예를 들면 제 1 및 제 2 층(32, 34)의 2 층)으로 이루어지는 경우에는, 복수층(예를 들면 제 1 층(32)과 제 2 층(34))의 각 층을 순차로 형성하여도 된다. 상세하게는, 반도체 칩(10) 또는 기판(20)의 한쪽에 각 층을 순차로 형성하여도 되고, 반도체 칩(10)에 어느 한 층(예를 들면 제 1 층(32))을 형성하고, 기판(20)에 다른 층(예를 들면 제 2 층(34))을 형성하여도 된다.When the adhesive member 30 consists of multiple layers (for example, two layers of the 1st and 2nd layers 32 and 34), multiple layers (for example, the 1st layer 32 and the 2nd layer 34) You may form each layer of)) one by one. In detail, each layer may be sequentially formed on one side of the semiconductor chip 10 or the substrate 20, and any one layer (for example, the first layer 32) may be formed on the semiconductor chip 10. Another layer (for example, the second layer 34) may be formed on the substrate 20.

도 1b에 도시한 바와 같이, 반도체 칩(10)과 기판(20)을 접착 부재(30)를 개재하여 밀착시킨다. 상세하게는, 반도체 칩(10)과 기판(20)을, 양자의 간극이 좁아지는 방향으로 가압한다. 이로써, 반도체 칩(10)의 전극(12)(또는 범프(14))과 배선 패턴(22) 사이에 도전 입자(36)가 삽입되어 개재하고, 양자간의 전기적인 접속이 도모된다.As shown in FIG. 1B, the semiconductor chip 10 and the substrate 20 are brought into close contact with each other via the adhesive member 30. In detail, the semiconductor chip 10 and the board | substrate 20 are pressed in the direction from which the clearance gap of both is narrowed. As a result, the conductive particles 36 are interposed between the electrode 12 (or the bump 14) and the wiring pattern 22 of the semiconductor chip 10, and electrical connection between the two is achieved.

도 1c에 도시한 바와 같이, 외부단자(40)를 기판(20)에 형성함으로써, 반도체 장치(1)를 얻을 수 있다. 도 1c에는, 외부단자(40)가 반도체 칩(10)의 탑재영역 내에만 형성된 FAN-IN형 반도체 장치가 도시되어 있지만, 이것에 한정되는 것이 아니다. 예를 들면, 반도체 칩(10)의 탑재 영역 외에만 외부단자(40)가 형성된 FAN-OUT형 반도체 장치나, 이것에 FAN-IN형을 조합한 FAN-IN/0UT형 반도체 장치에도 본 발명을 적용할 수 있다. 또한, FAN-OUT형 또는 FAN-IN/OUT형 반도체 장치에서는, 이방성 도전막에 의해서, 반도체 칩의 외측에 스티프너를 접착하여도 된다.As shown in FIG. 1C, the semiconductor device 1 can be obtained by forming the external terminal 40 on the substrate 20. Although FIG. 1C shows a FAN-IN type semiconductor device in which the external terminal 40 is formed only in the mounting region of the semiconductor chip 10, the present invention is not limited thereto. For example, the present invention also applies to a FAN-OUT type semiconductor device in which the external terminal 40 is formed only outside the mounting region of the semiconductor chip 10, or a FAN-IN / 0UT type semiconductor device in which the FAN-IN type is combined. Applicable In addition, in a FAN-OUT type | mold or a FAN-IN / OUT type | mold semiconductor device, you may adhere a stiffener to the outer side of a semiconductor chip by an anisotropic conductive film.

본 실시예에서는 제 1 및 제 2 층(32, 34)으로 이루어진 접착 부재(30)를 사용하므로, 상술한 효과를 달성할 수 있다.In this embodiment, since the adhesive member 30 which consists of the 1st and 2nd layers 32 and 34 is used, the above-mentioned effect can be achieved.

본 실시예는, 반도체 칩(10)을 BGA(Ba1l Grid Array)형 기판(20)에 페이스 다운 실장하는 예에서 설명하였지만, 상술한 바와 같이, 기판(20)의 형태 체에 관계없이, 단지 반도체 칩(10)을 기판(20)에 페이스다운 실장한 모든 실장 형태에 적용할 수 있다.Although the present embodiment has been described in the example in which the semiconductor chip 10 is face-down mounted on a B1 (Ba1 Grid Array) type substrate 20, as described above, regardless of the form of the substrate 20, only the semiconductor The chip 10 can be applied to all mounting forms in which the chip 10 is face-down mounted on the substrate 20.

도 2에는, 본 실시예에 따른 반도체 장치(1)를 실장한 회로 기판(50)이 도시되어 있다. 회로 기판(50)에는 예를 들면 유리 에폭시 기판 등의 유기계 기판을 사용하는 것이 일반적이다. 회로 기판(50)에는 예를 들면 구리로 이루어지는 배선 패턴(52)이 소망의 회로가 되도록 형성되어 있고, 그들의 배선 패턴과 반도체 장치(1)의 외부 단자(40)를 기계적으로 접속함으로써 그들의 전기적 도통을 꾀한다.2 shows a circuit board 50 in which the semiconductor device 1 according to the present embodiment is mounted. As the circuit board 50, for example, an organic substrate such as a glass epoxy substrate is generally used. The circuit board 50 is formed such that, for example, a wiring pattern 52 made of copper becomes a desired circuit, and their electrical conduction is achieved by mechanically connecting the wiring pattern and the external terminal 40 of the semiconductor device 1. Willing to.

그리고, 본 발명을 적용한 반도체 장치(1)를 갖는 전자 기기(60)로서, 도 3에는, 노트형 퍼스널 컴퓨터가 도시되어 있다.Note that a notebook personal computer is shown in FIG. 3 as an electronic device 60 having the semiconductor device 1 to which the present invention is applied.

또한, 상기 본 발명의 구성 요건 「반도체 칩」을 「전자 소자」로 치환하여, 반도체 칩과 동일하게 전자소자(능동 소자이거나 수동 소자이거나 관계없음)를, 기판에 실장하여 전자부품을 제조할 수 있다. 이러한 전자소자를 사용하여 제조된 전자 부품으로서, 예를 들면, 저항기, 콘덴서, 코일, 발진기, 필러, 온도 센서, 더미스터, 배리서터, 볼륨 또는 휴즈 등이 있다. In addition, by replacing the above-described "semiconductor chip" with the "electronic device", the electronic device (whether an active device or a passive device) can be mounted on a substrate in the same way as a semiconductor chip to manufacture an electronic component. have. Examples of electronic components manufactured using such electronic devices include resistors, capacitors, coils, oscillators, fillers, temperature sensors, dummysters, varistors, volumes, or fuses.

Claims (28)

삭제delete 삭제delete 삭제delete 삭제delete 삭제delete 삭제delete 삭제delete 삭제delete 삭제delete 삭제delete 반도체 칩과 배선 패턴이 형성되고, 상기 반도체 칩보다도 열팽창 계수가 큰 기판과, 상기 반도체 칩과 상기 배선 패턴을 전기적으로 접속하는 접착 부재를 포함하고,A semiconductor chip and a wiring pattern are formed, the substrate having a larger thermal expansion coefficient than the semiconductor chip, and an adhesive member for electrically connecting the semiconductor chip and the wiring pattern, 상기 접착 부재는 두께 방향에서 물성이 다르고, 제 1 수지를 기재로 하는 제 1 층과, 제 2 수지를 기재로 하고 상기 제 1 층보다도 상기 기판에 가까운 위치에 배치되는 제 2 층을 포함하고, The adhesive member has different physical properties in the thickness direction, and includes a first layer based on a first resin, and a second layer based on a second resin and disposed closer to the substrate than the first layer, 상기 제 1 수지보다도 상기 제 2 수지는 저탄성화되어 있고, The second resin is lower elastic than the first resin, 상기 제 2 수지는 변성된 에폭시 수지인, 반도체 장치. And the second resin is a modified epoxy resin. 반도체 칩과 배선 패턴이 형성되고, 상기 반도체 칩보다도 열팽창 계수가 큰 기판과, 상기 반도체 칩과 상기 배선 패턴을 전기적으로 접속하는 접착 부재를 포함하고, A semiconductor chip and a wiring pattern are formed, the substrate having a larger thermal expansion coefficient than the semiconductor chip, and an adhesive member for electrically connecting the semiconductor chip and the wiring pattern, 상기 접착 부재는 두께 방향에서 물성이 다르고, 제 1 수지를 기재로 하는 제 1 층과, 제 2 수지를 기재로 하고 상기 제 1 층보다도 상기 기판에 가까운 위치에 배치되는 제 2 층을 포함하고, 상기 제 1 수지보다도 상기 제 2 수지는 저탄성화되어 있고, 상기 제 1 수지는 에폭시 수지이고, 상기 제 2 수지는 비페닐 수지인, 반도체 장치. The adhesive member has different physical properties in the thickness direction, and includes a first layer based on a first resin, and a second layer based on a second resin and disposed closer to the substrate than the first layer, The semiconductor device according to claim 1, wherein the second resin is lower elasticized than the first resin, the first resin is an epoxy resin, and the second resin is a biphenyl resin. 삭제delete 삭제delete 삭제delete 삭제delete 반도체 칩과 배선 패턴이 형성되고, 상기 반도체 칩보다도 열팽창 계수가 큰 기판과, 상기 반도체 칩과 상기 배선 패턴을 전기적으로 접속하는 접착 부재를 포함하고, A semiconductor chip and a wiring pattern are formed, the substrate having a larger thermal expansion coefficient than the semiconductor chip, and an adhesive member for electrically connecting the semiconductor chip and the wiring pattern, 상기 접착 부재는 두께 방향에서 물성이 다르고, 제 1 수지를 기재로 하는 제 1 층과, 제 2 수지를 기재로 하고 상기 제 1 층보다도 상기 기판에 가까운 위치에 배치되는 제 2 층을 포함하고,The adhesive member has different physical properties in the thickness direction, and includes a first layer based on a first resin, and a second layer based on a second resin and disposed closer to the substrate than the first layer, 상기 제 1 수지보다도 상기 제 2 수지는 저탄성화되어 있는 반도체 장치가 탑재되어 있고,The second resin is mounted on the semiconductor device that is lower elastic than the first resin, 상기 제 2 수지는 변성된 에폭시 수지인, 회로기판. The second resin is a modified epoxy resin, the circuit board. 반도체 칩과 배선 패턴이 형성되고, 상기 반도체 칩보다도 열팽창 계수가 큰 기판과, 상기 반도체 칩과 상기 배선 패턴을 전기적으로 접속하는 접착 부재를 포함하고, A semiconductor chip and a wiring pattern are formed, the substrate having a larger thermal expansion coefficient than the semiconductor chip, and an adhesive member for electrically connecting the semiconductor chip and the wiring pattern, 상기 접착 부재는 두께 방향에서 물성이 다르고, 제 1 수지를 기재로 하는 제 1 층과, 제 2 수지를 기재로 하고 상기 제 1 층보다도 상기 기판에 가까운 위치에 배치되는 제 2 층을 포함하고, 상기 제 1 수지보다도 상기 제 2 수지는 저탄성화되어 있고, 상기 제 1 수지는 에폭시 수지이고, 상기 제 2 수지는 비페닐 수지인 반도체 장치를 구비하는, 회로 기판. The adhesive member has different physical properties in the thickness direction, and includes a first layer based on a first resin, and a second layer based on a second resin and disposed closer to the substrate than the first layer, A circuit board comprising a semiconductor device wherein the second resin is lower in elasticity than the first resin, the first resin is an epoxy resin, and the second resin is a biphenyl resin. 삭제delete 삭제delete 삭제delete 삭제delete 반도체 칩과 배선 패턴이 형성되고, 상기 반도체 칩보다도 열팽창 계수가 큰 기판과, 상기 반도체 칩과 상기 배선 패턴을 전기적으로 접속하는 접착 부재를 포함하고,A semiconductor chip and a wiring pattern are formed, the substrate having a larger thermal expansion coefficient than the semiconductor chip, and an adhesive member for electrically connecting the semiconductor chip and the wiring pattern, 상기 접착 부재는 두께 방향에서 물성이 다르고, 제 1 수지를 기재로 하는 제 1 층과, 제 2 수지를 기재로 하고 상기 제 1 층보다도 상기 기판에 가까운 위치에 배치되는 제 2 층을 포함하고,The adhesive member has different physical properties in the thickness direction, and includes a first layer based on a first resin, and a second layer based on a second resin and disposed closer to the substrate than the first layer, 상기 제 1 수지보다도 상기 제 2 수지는 저탄성화되어 있는 반도체 장치를 구비하고,The second resin has a semiconductor device which is lower in elasticity than the first resin, 상기 제 2 수지는 변성된 에폭시 수지인, 전자 기기. The second resin is a modified epoxy resin. 반도체 칩과 배선 패턴이 형성되고, 상기 반도체 칩보다도 열팽창 계수가 큰 기판과, 상기 반도체 칩과 상기 배선 패턴을 전기적으로 접속하는 접착 부재를 포함하고, A semiconductor chip and a wiring pattern are formed, the substrate having a larger thermal expansion coefficient than the semiconductor chip, and an adhesive member for electrically connecting the semiconductor chip and the wiring pattern, 상기 접착 부재는 두께 방향에서 물성이 다르고, 제 1 수지를 기재로 하는 제 1 층과, 제 2 수지를 기재로 하고 상기 제 1 층보다도 상기 기판에 가까운 위치에 배치되는 제 2 층을 포함하고, 상기 제 1 수지보다도 상기 제 2 수지는 저탄성화되어 있고, 상기 제 1 수지는 에폭시 수지이고, 상기 제 2 수지는 비페닐 수지인 반도체 장치를 구비하는, 전자 기기. The adhesive member has different physical properties in the thickness direction, and includes a first layer based on a first resin, and a second layer based on a second resin and disposed closer to the substrate than the first layer, An electronic device comprising a semiconductor device wherein the second resin is lower in elasticity than the first resin, the first resin is an epoxy resin, and the second resin is a biphenyl resin. 삭제delete 삭제delete 삭제delete 삭제delete
KR10-2000-7011579A 1999-02-18 2000-02-09 Bonding material, semiconductor device, method of manufacturing semiconductor device, circuit board and electronic device KR100514425B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3962599 1999-02-18
JP99-39625 1999-02-18

Publications (2)

Publication Number Publication Date
KR20010042822A KR20010042822A (en) 2001-05-25
KR100514425B1 true KR100514425B1 (en) 2005-09-14

Family

ID=12558298

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2000-7011579A KR100514425B1 (en) 1999-02-18 2000-02-09 Bonding material, semiconductor device, method of manufacturing semiconductor device, circuit board and electronic device

Country Status (4)

Country Link
JP (1) JP4029255B2 (en)
KR (1) KR100514425B1 (en)
TW (1) TW550714B (en)
WO (1) WO2000049652A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2863767B1 (en) * 2003-12-12 2006-06-09 Commissariat Energie Atomique IRREVERSIBLE MEMORY HOLDER WITH PLASTIC DEFORMATION AND METHOD OF MAKING SUCH A SUPPORT
JP2006100752A (en) * 2004-09-30 2006-04-13 Sanyo Electric Co Ltd Circuit arrangement and its manufacturing method
KR102492533B1 (en) 2017-09-21 2023-01-30 삼성전자주식회사 Support substrate, Method of fabricating a semiconductor Package and Method of fabricating an electronic device
TWI714905B (en) * 2018-11-08 2021-01-01 瑞昱半導體股份有限公司 Circuit device and circuit design and assembly method
CN114023704B (en) * 2022-01-05 2022-04-01 长鑫存储技术有限公司 Non-conductive film, forming method thereof, chip packaging structure and method
CN114374101A (en) * 2022-01-12 2022-04-19 业成科技（成都）有限公司 Connection structure and method of forming a connection structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0513119A (en) * 1991-07-04 1993-01-22 Sharp Corp Tape connector for connecting electronic parts
JPH09266229A (en) * 1996-03-28 1997-10-07 Matsushita Electric Ind Co Ltd Packaging method of semiconductor device and packaged structure of semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1013002A (en) * 1996-06-20 1998-01-16 Matsushita Electric Ind Co Ltd Method for mounting semiconductor element
JPH1084014A (en) * 1996-07-19 1998-03-31 Shinko Electric Ind Co Ltd Manufacture of semiconductor device
JPH10199930A (en) * 1996-12-28 1998-07-31 Casio Comput Co Ltd Connection structure of electronic components and connecting method therefor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0513119A (en) * 1991-07-04 1993-01-22 Sharp Corp Tape connector for connecting electronic parts
JPH09266229A (en) * 1996-03-28 1997-10-07 Matsushita Electric Ind Co Ltd Packaging method of semiconductor device and packaged structure of semiconductor device

Also Published As

Publication number Publication date
WO2000049652A1 (en) 2000-08-24
WO2000049652A8 (en) 2000-10-26
JP4029255B2 (en) 2008-01-09
TW550714B (en) 2003-09-01
KR20010042822A (en) 2001-05-25

Similar Documents

Publication Publication Date Title
US7276400B2 (en) Methods of making microelectronic packages with conductive elastomeric posts
KR960006982B1 (en) Stepped multilayer interconnection apparatus and the method for making the same
US6720644B2 (en) Semiconductor device using interposer substrate and manufacturing method therefor
JP3213291B2 (en) Multilayer substrate and semiconductor device
KR20050018623A (en) Apparatus with compliant electrical terminals, and methods for forming same
WO2000070677A1 (en) Semiconductor device, method of manufacture thereof, circuit board, and electronic device
JP3654116B2 (en) Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
US6417029B1 (en) Compliant package with conductive elastomeric posts
JP3436170B2 (en) Anisotropic conductive film, semiconductor device using the same, and method of manufacturing the same
JP2000243864A (en) Semiconductor device, its manufacture, circuit board and electronic apparatus
KR100514425B1 (en) Bonding material, semiconductor device, method of manufacturing semiconductor device, circuit board and electronic device
JP2004363566A (en) Electronic-component mounting body and method of manufacturing the same
US20070069242A1 (en) Semiconductor chip and semiconductor device, and method for manufacturing semiconductor device
JP3225800B2 (en) Semiconductor device
US6492715B1 (en) Integrated semiconductor package
KR100735211B1 (en) Anisotropic conductive film with conductive ball of highly reliable electric connection
JPH10125725A (en) Semiconductor device and manufacturing method thereof
JP2003152022A (en) Bonding member, semiconductor device and method for manufacturing the same, circuit board, and electronic equipment
JP2008024941A (en) Semiconductor device
KR100946597B1 (en) Conductive ball with easily pressed down, method of mamufacturing thereof and anisotropic conductive film using the same
JP2001068604A (en) Fixing resin, anisotropic conductive resin, semiconductor device and manufacture thereof, circuit board and electronic equipment
KR100613026B1 (en) Conductive ball, method of mamufacturing thereof and anisotropic conductive film using the same
JPH087957A (en) Connecting method of circuit board and connecting structure body, and adhesive film using for it
JP3841135B2 (en) Semiconductor device, circuit board and electronic equipment
JP3692810B2 (en) Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E902 Notification of reason for refusal
E902 Notification of reason for refusal
E902 Notification of reason for refusal
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20120821

Year of fee payment: 8

FPAY Annual fee payment

Payment date: 20130819

Year of fee payment: 9

FPAY Annual fee payment

Payment date: 20140826

Year of fee payment: 10

FPAY Annual fee payment

Payment date: 20150820

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee