KR100511353B1 - Fabrication method of liquid crystal display device and liquid crystal display device fabticated by the same - Google Patents
Fabrication method of liquid crystal display device and liquid crystal display device fabticated by the same Download PDFInfo
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- KR100511353B1 KR100511353B1 KR10-2002-0085620A KR20020085620A KR100511353B1 KR 100511353 B1 KR100511353 B1 KR 100511353B1 KR 20020085620 A KR20020085620 A KR 20020085620A KR 100511353 B1 KR100511353 B1 KR 100511353B1
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- 238000000034 method Methods 0.000 title claims abstract description 61
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000010409 thin film Substances 0.000 claims abstract description 30
- 239000010410 layer Substances 0.000 claims description 69
- 239000010408 film Substances 0.000 claims description 22
- 239000007769 metal material Substances 0.000 claims description 21
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 9
- 230000001681 protective effect Effects 0.000 claims description 9
- 229910004205 SiNX Inorganic materials 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011241 protective layer Substances 0.000 claims description 3
- 241001239379 Calophysus macropterus Species 0.000 claims description 2
- -1 MoNb Inorganic materials 0.000 claims description 2
- 229910016024 MoTa Inorganic materials 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 229910016048 MoW Inorganic materials 0.000 claims 1
- 229910052721 tungsten Inorganic materials 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 description 16
- 239000002184 metal Substances 0.000 description 16
- 238000003860 storage Methods 0.000 description 13
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 239000003086 colorant Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133345—Insulating layers
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13458—Terminal pads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
- G02F1/136281—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon having a transmissive semiconductor substrate
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
- G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
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- Optics & Photonics (AREA)
- Crystallography & Structural Chemistry (AREA)
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- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
본 발명은 마스크 공정수를 단순화할 수 있는 액정표시소자의 제조방법 및 이 방법에 의한 액정표시소자의 구조에 관한 것으로, 본 발명은 박막트랜지스터 및 화소영역이 정의된 기판을 준비하는 단계와; 상기 박막트랜지스터 영역에 제 1마스크 공정을 통하여 소스/드레인전극을 형성하는 단계와; 상기 소스/드레인 상에 제 2마스크 공정을 통하여 액티브층 및 게이트 전극을 형성하는 단계와; 상기 화소영역에 제 3마스크 공정을 통하여 화소전극을 형성하는 단계를 포함하여 구성된다.The present invention relates to a method of manufacturing a liquid crystal display device and a structure of the liquid crystal display device according to the method that can simplify the number of mask process, the present invention comprises the steps of preparing a substrate having a thin film transistor and a pixel region defined; Forming a source / drain electrode on the thin film transistor region through a first mask process; Forming an active layer and a gate electrode on the source / drain through a second mask process; And forming a pixel electrode in the pixel region through a third mask process.
Description
본 발명은 액정표시소자에 관한 것으로, 특히 마스크수를 줄여 공정을 단순화할 수 있는 액정표시소자의 제조방법 및 그 방법에 의한 액정표시소자의 구조에 관한 것이다.The present invention relates to a liquid crystal display device, and more particularly, to a manufacturing method of a liquid crystal display device capable of simplifying a process by reducing the number of masks and a structure of a liquid crystal display device by the method.
TV와 컴퓨터의 정보를 디스플레이 하기 위해 지금까지 주로 CRT 모니터가 사용되어 왔다. CRT는 화질이 우수하고 화면 밝기가 좋아 그 동안 디스플레이의 주종을 이루어왔다. 그러나 화면이 커짐에 따라 CRT 모니터의 크기가 너무 커져 공간을 많이 차지하는 문제점이 발생하기도 하였으며, 휴대용 기기가 보편화되면서 디스플레이의 무게 또한 문제가 되었다.CRT monitors have traditionally been used to display information from TVs and computers. CRT has been the dominant display for a long time because of its excellent image quality and high screen brightness. However, as the screen became larger, the size of the CRT monitor became too large to occupy a lot of space. As portable devices became more common, the weight of the display also became a problem.
이러한 문제점들을 해결한 것이 액정 디스플레이, 플라즈마 디스플레이 패널(Plazma Display Panel), 유기 EL(Electro Luminescence), LED(Light Emitting Diode), FED(Field Emission Display) 등의 평판형 디스플레이 소자들이다. 이러한 평판형 디스플레이 중 노우트 북 PC나 컴퓨터 모니터 등으로 이미 널리 사용되고 있으며 소비전격 소모가 적은 장점을 가지고 있는 액정 표시 장치(LCD)가 각광을 받고 있다.These problems are solved by flat panel display devices such as liquid crystal displays, plasma display panels, organic luminescence (EL), light emitting diodes (LEDs), and field emission displays (FEDs). Among such flat panel displays, a liquid crystal display (LCD), which is already widely used as a notebook computer or a computer monitor and has a low consumption consumption, is in the spotlight.
도 1은 일반적인 액정표시소자의 개략적인 단면도를 나타낸 것으로, 도면에 도시한 바와 같이 액정표시소자는 하부기판(10)과 상부기판(20) 그리고 그 사이에 형성된 액정층(15)으로 구성되어 있다.FIG. 1 is a schematic cross-sectional view of a general liquid crystal display device. As shown in the drawing, the liquid crystal display device includes a lower substrate 10 and an upper substrate 20 and a liquid crystal layer 15 formed therebetween. .
하부기판(10)에는 박막트랜지스터(T)와 화소전극(7)이 형성되어 있다. 상기 박막트랜지스터(T)는 주사신호가 인가되는 게이트 전극(1)과, 주사 신호에 대응하여 데이터 신호를 전송하도록 마련된 반도체층(3)과, 반도체층(3)과 게이트 전극(1)을 전기적으로 격리시켜주는 게이트 절연막(2)과, 반도체층(3)의 상부에 형성되어 데이터 신호를 인가하는 소오스 전극(4)과, 데이터 신호를 화소전극(7)에 인가하는 드레인전극(5)으로 구성되어 있으며, 상기 반도체층(3)은 비정질 실리콘(a-Si)을 증착하여 형성된 액티브층(3a)과, 액티브층(3a)의 양측 상부에 n+ 도핑된 오믹 접촉층(ohmic contact layer)(3b)으로 구성되어 있다. 상기 박막트랜지스터(T) 위에는 보호막(6) 및 화소전극(7)이 형성되어 있으며, 화소전극(7) 상부에는 액정 분자들의 배향을 위해 형성된 제 1배향막(4a)이 형성되어 있다. 여기서, 상기 화소전극(7)은 사용하고자하는 모드, 즉 투과형인지 반사형인지에 따라 결정되며, 반사형인 경우에는 반사특성이 우수한 Al 또는 Al합금과 같은 불투명 금속물질을 사용하고, 투과형인 경우에는 ITO(Indium Tin Oxide) 또는 IZO(Indium Zinc Oxide)와 같은 투명한 전도성물질을 사용한다.The thin film transistor T and the pixel electrode 7 are formed on the lower substrate 10. The thin film transistor T is configured to electrically connect the gate electrode 1 to which a scan signal is applied, the semiconductor layer 3 provided to transmit a data signal in response to the scan signal, and the semiconductor layer 3 and the gate electrode 1. A gate insulating film 2 that is isolated from each other, a source electrode 4 formed on the semiconductor layer 3 to apply a data signal, and a drain electrode 5 to apply the data signal to the pixel electrode 7. The semiconductor layer 3 includes an active layer 3a formed by depositing amorphous silicon (a-Si), and an ohmic contact layer n + doped on both sides of the active layer 3a ( 3b). A passivation layer 6 and a pixel electrode 7 are formed on the thin film transistor T, and a first alignment layer 4a formed for alignment of liquid crystal molecules is formed on the pixel electrode 7. Here, the pixel electrode 7 is determined according to a mode to be used, that is, a transmission type or a reflection type. In the case of the reflection type, an opaque metal material such as Al or an Al alloy having excellent reflection characteristics is used. Transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO) are used.
상부기판(20)에는 화소간의 빛샘을 방지하기 위한 블랙매트릭스(12)와 칼라를 구현하기 위한 R, G, B 색상의 칼라필터(11)가 형성되어 있다. 상기 칼라필터(11) 상에는 칼라필터의 평탄화 및 그 상부에 형성된 공통전극(13)과의 접착성을 향상시키기 위한 평탄화막(미도시)이 추가로 형성되어 있으며, 그 상부에는 액정층(15)에 전압을 인가하기 위한 공통전극(13)과, 액정 분자들의 배향을 위해 형성된 제 2배향막(4b)이 형성되어 있다. 여기서 공통전극(13)은 빛이 투과할 수 있도록 투명한 전도체인 ITO(Indium Tin Oxide) 또는 IZO(Indium Zinc Oxide)로 이루어져 있다.The upper substrate 20 is provided with a black matrix 12 for preventing light leakage between pixels and a color filter 11 for R, G, and B colors for implementing colors. A planarization film (not shown) is further formed on the color filter 11 to improve planarization of the color filter and adhesion to the common electrode 13 formed thereon, and a liquid crystal layer 15 thereon. The common electrode 13 for applying a voltage to the second electrode and the second alignment layer 4b formed for the alignment of the liquid crystal molecules are formed. The common electrode 13 is made of indium tin oxide (ITO) or indium zinc oxide (IZO), which are transparent conductors to allow light to pass therethrough.
상기와 같이 구성된 액정표시소자 특히, 박막트랜지스터가 형성된 하부기판은 여러 단계의 마스크 공정을 통하여 제조되는데, 상기 마스크 공정수는 제품의 생산단가 및 생산력을 결정하는 주요인이 된다. 따라서, 마스크 공정수를 줄이기 위한 연구가 활발히 진행되고 있다.The liquid crystal display device configured as described above, in particular, the lower substrate on which the thin film transistor is formed is manufactured through several steps of masking process, and the number of masking processes becomes a major factor in determining the production cost and productivity of the product. Therefore, research to reduce the number of mask processes is actively being conducted.
도 2는 4마스크 공정을 통한 박막트랜지스터의 공정단면도를 도시한 것으로, 종래 4마스크 공정을 통한 박막트랜지스터의 제조방법을 설명하면 다음과 같다.2 illustrates a process cross-sectional view of a thin film transistor through a four mask process. A method of manufacturing a thin film transistor through a conventional four mask process is as follows.
먼저, 도 2a에 도시한 바와 같이, 투명한 기판(20) 위에 금속물질을 증착한 다음, 제 1마스크(미도시)를 사용하여 포토리소그래피(photolithography) 공정으로 제 1PR 패턴(23a)을 형성한 후, 이를 마스크로 하여 게이트 전극(23)을 형성한다. 포토리소그래피 공정은 PR 도포->노광->현상->식각 공정으로 진행되며, 상기 노광 공정시 PR 패턴을 형성하기 위하여 마스크를 사용하게 된다. 또한, 식각 공정은 PR 현상 이후 형성된 PR 패턴을 마스크로하여 실질적으로 금속패턴(게이트 전극)을 형성하게 되며, 이후에 잔류하는 PR 패턴은 제거된다.First, as shown in FIG. 2A, a metal material is deposited on the transparent substrate 20, and then a first PR pattern 23a is formed by a photolithography process using a first mask (not shown). The gate electrode 23 is formed using this as a mask. The photolithography process is performed by a PR coating-> exposure-> developing-> etching process, and a mask is used to form a PR pattern during the exposure process. In addition, the etching process forms a metal pattern (gate electrode) substantially using the PR pattern formed after the PR development as a mask, and the remaining PR pattern is subsequently removed.
그리고, 도 2b에 도시한 바와 같이, 상기 게이트 전극(23)이 형성된 기판(20)의 상부에 SiNx 또는 SiOx와 같은 무기물질과 반도체층(28a, 28b)과 금속물질(25)을 연속적으로 증착한 다음, 제 2마스크(미도시)를 사용하여 포토리소그래피 공정으로 채널영역 상에 선택적으로 잔류하는 제 2PR 패턴(23b)을 형성하되, 상기 게이트 전극(23) 상의 금속층(25) 상부에서는 PR층에 회절노광을 적용하여 다른 영역의 PR 패턴에 비해 얇은 두께를 갖도록 한다. 이어서, 상기 제 2PR 패턴(23b)을 마스크로 하여 게이트 절연막(22)이 노출될 때까지 식각한 다음, 도 2c에 도시한 바와 같이, 상기 회절 노광이 적용된 PR 패턴 영역을 제거하여, 금속층을 노출시키는 제 3PR 패턴(23c)을 형성한 후, 상기 제 3PR 패턴(23c)을 마스크로 하여 금속층(25)을 식각함으로써, 소스/드레인전극(25a/25b)을 형성한다. 이때 사용되는 제 2마스크는 회절 마스크로써, 부분적으로 광투과율 특성이 다르기 때문에 부분적으로 PR 패턴 두께를 다르게 형성할 수가 있다. 일반적으로 회절 마스크는 한번의 마스크 공정을 통하여 서로 다르게 적층된 층을 동시에 적절하게 패터닝하기 위하여 사용되는 것으로, 예시한 바와 같이, 액티브층(28)과 소스/드레인전극층(25a/25b) 한번의 마스크 공정으로 형성할 수가 있다.As shown in FIG. 2B, inorganic materials such as SiNx or SiOx, semiconductor layers 28a and 28b, and metal material 25 are continuously deposited on the substrate 20 on which the gate electrode 23 is formed. Next, a second PR pattern 23b is selectively formed on the channel region by a photolithography process using a second mask (not shown), but the PR layer is formed on the metal layer 25 on the gate electrode 23. Diffraction exposure is applied to the film to have a thickness thinner than that of the PR patterns in other areas. Subsequently, using the second PR pattern 23b as a mask, the gate insulating layer 22 is etched until the gate insulating film 22 is exposed, and as shown in FIG. 2C, the PR pattern region to which the diffraction exposure is applied is removed to expose the metal layer. After the third PR pattern 23c is formed, the metal layer 25 is etched using the third PR pattern 23c as a mask to form the source / drain electrodes 25a / 25b. At this time, the second mask used is a diffraction mask, and since the light transmittance characteristics are partially different, the PR mask thickness can be formed differently. In general, a diffraction mask is used to simultaneously and appropriately pattern layers stacked differently through one mask process. As illustrated, one mask of the active layer 28 and the source / drain electrode layers 25a and 25b may be used. It can form by a process.
5 마스크 공정의 경우에는 액티브층(28)과 소스/드레인전극층(25a/25b) 형성시 두 번의 마스크 공정이 진행되기 때문에 4 마스크 공정에 비하여 마스크 공정이 한번 더 추가되는 것이다.In the case of the 5 mask process, since the mask process is performed twice when the active layer 28 and the source / drain electrode layers 25a / 25b are formed, the mask process is added once more than the 4 mask process.
상기와 같이, 액티브층(28) 및 소스/드레인전극층(25a/25b)을 형성한 후, 도 2d에 도시한 바와 같이, 소스/드레인전극층(25a/25b) 상에 잔류하는 PR 패턴을 제거하고, 그 상부에 SiOx 또는 SiNx와 같은 무기물질이나. BCB 또는 아크릴과 같은 유기물질을 도포한 다음, 제 3마스크를 사용하여 포토리소그래피(photolithography) 공정으로 제 4PR 패턴(23d)을 형성한 후, 드레인전극(25b)의 일부를 노출시키는 보호막(29)을 형성한다.As described above, after the active layer 28 and the source / drain electrode layers 25a / 25b are formed, as shown in FIG. 2D, the PR pattern remaining on the source / drain electrode layers 25a / 25b is removed. Or inorganic material such as SiOx or SiNx on top of it. After applying an organic material such as BCB or acrylic, the fourth PR pattern 23d is formed by a photolithography process using a third mask, and then a protective film 29 exposing a part of the drain electrode 25b. To form.
마지막으로, 도 2e에 도시한 바와 같이, 상기 보호막(29) 상에 잔류하는 제 4PR 패턴을 제거한 다음, 상기 보호막(29) 상에 ITO와 같은 투명한 전도성 물질을 증착한 후, 이를 제 4마스크를 사용하여 패터닝함으로써, 화소전극(31)을 형성한다.Finally, as shown in FIG. 2E, after removing the fourth PR pattern remaining on the passivation layer 29, a transparent conductive material such as ITO is deposited on the passivation layer 29, and then the fourth mask is formed. By patterning using the same, the pixel electrode 31 is formed.
그러나, 상기와 같은 종래 4마스크 공정은 5마스크 공정에 비하여 마스크수를 줄여 공정을 단순화할 수 있으나, 이때 사용되는 회절마스크가 고가이기 때문에 재료비 차원에서 효과를 거두지 못하는 문제점이 있었다.However, the conventional four-mask process as described above can simplify the process by reducing the number of masks compared to the five-mask process, but there is a problem in that the diffraction mask used at this time is not expensive in terms of material cost.
따라서, 본 발명은 상기와 같은 문제점들을 해결하기 위해서 이루어진 것으로, 3 마스크 공정을 통하여 액정표시소자를 제작할 수 있는 액정표시소자의 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, and an object thereof is to provide a method of manufacturing a liquid crystal display device which can manufacture a liquid crystal display device through a three mask process.
본 발명의 다른 목적은 회절마스크를 사용하지 않고 4 마스크 공정을 통하여 액정표시소자를 제작할 수 있는 액정표시소자의 제조방법을 제공하는데 그 목적이 있다.Another object of the present invention is to provide a method for manufacturing a liquid crystal display device that can produce a liquid crystal display device through a four-mask process without using a diffraction mask.
기타 본 발명의 목적 및 특징은 이하의 발명의 구성 및 특허청구범위에서 상세히 기술될 것이다.Other objects and features of the present invention will be described in detail in the configuration and claims of the following invention.
상기한 목적을 달성하기 위한 본 발명은 박막트랜지스터 및 화소영역이 정의된 기판을 준비하는 단계와; 상기 박막트랜지스터 영역에 제 1마스크 공정을 통하여 소스/드레인전극을 형성하는 단계와; 상기 소스/드레인 상에 제 2마스크 공정을 통하여 액티브층 및 게이트 전극을 형성하는 단계와; 상기 화소영역에 제 3마스크 공정을 통하여 화소전극을 형성하는 단계를 포함하여 구성된다.The present invention for achieving the above object comprises the steps of preparing a substrate in which the thin film transistor and the pixel region is defined; Forming a source / drain electrode on the thin film transistor region through a first mask process; Forming an active layer and a gate electrode on the source / drain through a second mask process; And forming a pixel electrode in the pixel region through a third mask process.
상기와 같은 본 발명은 3마스크 공정을 통하여 액정표시소자가 제조되기 때문에 종래에 비하여 생산효율을 더욱 향상시킬 수가 있다.In the present invention as described above, since the liquid crystal display device is manufactured through a three mask process, the production efficiency can be further improved as compared with the related art.
한편, 상기 게이트전극 및 화소전극을 포함하는 기판의 전면에 보호막을 형성한 후, 이를 패터닝하여 게이트 및 데이터 패드의 일부를 노출시키는 콘택홀을 형성하는 단계를 추가로 포함시킬 수 있다. 이는 4마스크 공정으로 액정표시소자가 제작 되지만, 고가의 회절마스크를 사용하지 않기 때문에 종래에 비하여 재료비를 절감할 수 있는 잇점을 가진다.Meanwhile, after forming a protective film on the entire surface of the substrate including the gate electrode and the pixel electrode, patterning the protective layer may further include forming a contact hole exposing a portion of the gate and the data pad. Although the liquid crystal display device is manufactured in a four-mask process, it does not use an expensive diffraction mask has the advantage of reducing the material cost compared to the conventional.
상기와 같은 공정을 통하여 완성된 본 발명의 액정표시소자는 박막트랜지스터 및 화소영역이 정의된 기판의 박막트랜지스터 영역에 형성되며, 소정간격 이격하는 소스 및 드레인전극과; 상기 소스 및 드레인 전극 상에 순차적으로 형성된 게이트 절연막, 액티브층 및 게이트전극으로 구성되어 있으며, 상기 화소영역에는 상기 드레인전극과 접속하는 화소전극이 형성되어 있다. 이때, 상기 화소전극은 반사특성이 우수한 불투명한 금속물질로 형성되어 있다. 그리고, 상기 소스/드레인 전극 및 화소전극 상에는 보호막이 추가로 형성될 수도 있다.The liquid crystal display device of the present invention completed through the above process is formed in the thin film transistor region of the substrate in which the thin film transistor and the pixel region is defined, and source and drain electrodes spaced at predetermined intervals; A gate insulating film, an active layer, and a gate electrode sequentially formed on the source and drain electrodes are formed, and a pixel electrode connected to the drain electrode is formed in the pixel region. In this case, the pixel electrode is formed of an opaque metal material having excellent reflection characteristics. In addition, a passivation layer may be further formed on the source / drain electrodes and the pixel electrode.
이하, 참조한 도면을 통하여 상기와 같은 본 발명의 액정표시소자의 제조방법에 대하여 상세히 설명하면 다음과 같다.Hereinafter, the manufacturing method of the liquid crystal display device of the present invention as described above will be described in detail with reference to the accompanying drawings.
도 3은 본 발명에 따른 액정표시소자의 제조방법을 나타낸 공정수순도이다.3 is a process flowchart showing the manufacturing method of the liquid crystal display device according to the present invention.
먼저, 도 3a에 도시한 바와 같이, 박막트랜지스터, 화소, 스토리지 커패시터, 데이터 및 게이트패드 영역이 정의된 기판(120)을 준비한 다음, 상기 기판(120) 상에 Mo, MoW, MoTa, MoNb, Cr, W등과 같은 금속물질을 스퍼터링 방법으로 증착하여 제 1금속층(125)을 형성한 다음 상기 제 1금속층(125) 상에 인(P)과 같은 불순물이 도핑된 n+ 비정질 실리콘(130)을 CVD 방법을 통하여 증착한다. 그 다음, 도 3b에 도시한 바와 같이, 상기 n+ 비정질 실리콘(130)의 전면에 포토레지스트를 도포한 다음, 이를 패터닝하여 상기 n+ 비정질 실리콘(130) 상에 선택적으로 잔존하는 제 1포토레지스트 패턴(135)을 형성한 후, 상기 제 1포토레지스트 패턴(135)을 마스크로 하여 노출된 n+ 비정질 실리콘(130) 및 제 1금속층(125)을 식각함으로써, 소정간격 이격하는 소스 및 드레인전극(121a,121b)과 n+ 비정질 실리콘 패턴(131)을 형성한다. 이때, 스토리지의 하부전극(123) 및 데이터패드(125)도 함께 형성한다. 상기 데이터패드(125)는 외부의 회로와 전기적으로 연결되어 상기 소스 및 드레인전극(121a,121b)에 데이터신호를 전달해주는 역할을 한다.First, as shown in FIG. 3A, a substrate 120 having a thin film transistor, a pixel, a storage capacitor, data, and a gate pad region is prepared, and then Mo, MoW, MoTa, MoNb, Cr are formed on the substrate 120. A metal material such as W or the like is deposited by a sputtering method to form a first metal layer 125, and then n + amorphous silicon 130 doped with impurities such as phosphorus (P) on the first metal layer 125. Deposition through. Next, as shown in FIG. 3B, a photoresist is applied to the entire surface of the n + amorphous silicon 130, and then patterned to form a first photoresist pattern selectively remaining on the n + amorphous silicon 130 ( 135, the exposed n + amorphous silicon 130 and the first metal layer 125 are etched using the first photoresist pattern 135 as a mask, so that the source and drain electrodes 121a, 121b) and an n + amorphous silicon pattern 131 are formed. In this case, the lower electrode 123 and the data pad 125 of the storage are also formed. The data pad 125 is electrically connected to an external circuit and transmits a data signal to the source and drain electrodes 121a and 121b.
이후에 상기 n+ 비정질 실리콘 패턴(131) 상에 잔류하는 제 1포토레지스트 패턴(135)을 제거한 다음, 도 3c에 도시한 바와 같이, 소스/드레인전극(121a,121b) 및 n+ 비정질 실리콘 패턴(131)이 형성된 기판(120) 상에 CVD방법을 통하여 비정질 실리콘(136) 및 SiNx 또는 SiOx과 같은 절연막(138)을 순차적으로 증착한 후, 그 상부에 스퍼터링 방법을 통하여 Al. AlNd, Cr, Mo, Cu등과 같은 금속물질을 증착하여 제 2금속층(140)을 형성한다. 이어서, 도 3d에 도시한 바와 같이, 상기 제 2금속층(140) 전면에 포토레지스트를 도포한 다음, 이를 패터닝하여 상기 제 2금속층(140) 상에 선택적으로 전존하는 제 2포토레지스트 패턴(145)을 형성한다. 그 다음, 상기 제 2포토레지스트 패턴(145)을 마스크로 하여 상기 비정질 실리콘(136), 절연막(138), 제 2금속층(140) 및 n+ 비정질 실리콘 패턴(131)의 일부를 동시에 식각함으로써, 액티브층(137), 게이트절연막(139), 게이트전극(141) 및 상기 액티브층(137)과 소스/드레인전극(121a,121b) 사이에 개재된 오믹접촉층(133)을 형성한다. 상기 오믹접촉층(137)은 액티브층(137)과 소스/드레인전극(121a,121b) 사이의 저항을 줄여 신호의 전달을 원활하게 해주는 역할을 한다. 또한, 스토리지 하부전극(123) 상에도 상기의 패턴들(즉, 비정질 실리콘, 절연막 및 제 2금속패턴)을 그대로 형성하여 스토리지 상부전극(143)을 함께 형성한다. 상기 스토리지 하부전극(123)과 상부전극(143)은 스토리지 커패시터(Storage Capacitor)를 형성하여 박막트랜지스터의 게이트전극(141)에 게이트 신호가 인가되는 동안 게이트 전압을 충전한 후, 다음 게이트라인 구동시 이후에 형성될 화소전극에 데이터전압이 공급되는 동안 충전된 전압을 방전하여 화소전극의 전압 변동을 방지하는 역할을 한다. 아울러, 상기 게이트 패드부에 게이트패드(144)도 함께 형성된다. 상기 게이트패드(144)는 외부의 회로와 전기적으로 연결되어 게이트전극(141)에 게이트 신호를 전달해주는 역할을 한다.Thereafter, the first photoresist pattern 135 remaining on the n + amorphous silicon pattern 131 is removed, and as shown in FIG. 3C, the source / drain electrodes 121a and 121b and the n + amorphous silicon pattern 131 are removed. ) Is sequentially deposited on the substrate 120 on which the amorphous silicon 136 and the insulating film 138 such as SiNx or SiOx are deposited by a CVD method, and then sputtered on top of Al. A second metal layer 140 is formed by depositing a metal material such as AlNd, Cr, Mo, Cu, or the like. Subsequently, as shown in FIG. 3D, a photoresist is coated on the entire surface of the second metal layer 140, and then patterned to form the second photoresist pattern 145 selectively present on the second metal layer 140. To form. Subsequently, a portion of the amorphous silicon 136, the insulating layer 138, the second metal layer 140, and the n + amorphous silicon pattern 131 are simultaneously etched using the second photoresist pattern 145 as a mask, thereby active. A layer 137, a gate insulating film 139, a gate electrode 141, and an ohmic contact layer 133 interposed between the active layer 137 and the source / drain electrodes 121a and 121b are formed. The ohmic contact layer 137 serves to facilitate signal transmission by reducing the resistance between the active layer 137 and the source / drain electrodes 121a and 121b. In addition, the above patterns (that is, amorphous silicon, an insulating film, and a second metal pattern) are formed on the storage lower electrode 123 as they are to form the storage upper electrode 143 together. The storage lower electrode 123 and the upper electrode 143 form a storage capacitor to charge the gate voltage while the gate signal is applied to the gate electrode 141 of the thin film transistor, and then drive the next gate line. Since the charged voltage is discharged while the data voltage is supplied to the pixel electrode to be formed later, it serves to prevent the voltage variation of the pixel electrode. In addition, a gate pad 144 is also formed at the gate pad part. The gate pad 144 is electrically connected to an external circuit and serves to transfer a gate signal to the gate electrode 141.
이후에, 상기 게이트전극(141), 스토리지 상부전극(143) 및 게이트패드(144)에 전류하는 제 2포토레지스트 패턴(145)을 제거한 다음, 도 3e에 도시한 바와 같이, 박막트랜지스터 및 스토리지 커패시터가 형성된 기판 전면에 기판(120) 전면에 Al, AlNd, Ag와 같이 반사율이 우수하고 불투명한 금속물질을 증착하여 제 3금속층(150)을 형성한다. 그리고, 도 3f에 도시한 바와 같이, 상기 제 3금속층(150) 상부 전면에 포토레지스트를 도포한 다음, 이를 패터닝하여 닝하여 제 3금속층(150) 상에 선택적으로 잔존하는 제 3포토레지스트 패턴(155)을 형성한다. 이후에, 상기 제 2포토레지스트 패턴(155)을 마스크로 하여 상기 제 3금속층(150)을 식각하여 화소전극(151)을 형성한다. 이때, 상기 화소전극(151)은 박막트랜지스터의 드레인전극(121b) 및 스토리지 하부전극(123)과 그 일부가 중첩되어 전기적인 접속을 이루고 있다. 아울러, 상기 데이터 및 게이트패드(125, 144) 상에도 외부회로와의 연결을 용이하게 하기 위하여 완충층(153)을 함께 형성한다.Subsequently, the second photoresist pattern 145 that currents the gate electrode 141, the storage upper electrode 143, and the gate pad 144 is removed, and as shown in FIG. 3E, the thin film transistor and the storage capacitor are removed. The third metal layer 150 is formed by depositing an opaque metal material having excellent reflectivity such as Al, AlNd, and Ag on the entire surface of the substrate 120 on which the substrate 120 is formed. As shown in FIG. 3F, after the photoresist is coated on the entire upper surface of the third metal layer 150, the photoresist is patterned and then selectively rested on the third metal layer 150. 155). Thereafter, the third metal layer 150 is etched using the second photoresist pattern 155 as a mask to form the pixel electrode 151. In this case, the pixel electrode 151 overlaps the drain electrode 121b and the storage lower electrode 123 of the thin film transistor to form an electrical connection. In addition, the buffer layer 153 is also formed on the data and gate pads 125 and 144 to facilitate connection with an external circuit.
도 4는 본 발명의 다른 실시예를 도시한 도면으로 화소전극의 공정순서를 제외한 모든 공정이 도 3에 도시된 내용과 동일하다 따라서, 여기에서는 그 차이점만을 간략하게 설명하기로 한다.FIG. 4 is a view showing another embodiment of the present invention. All processes except for the process sequence of the pixel electrode are the same as those shown in FIG. 3. Therefore, only the differences will be briefly described here.
먼저, 도 4a에 도시한 바와 같이, 박막트랜지스터, 화소, 스토리지 커패시터, 데이터 및 게이트패드 영역이 정의된 기판(220)을 준비한 다음, 상기 기판(220) 상에 반사특성이 우수한 금속물질을 증착한 후, 이를 패터닝하여 화소영역에 배치되는 화소전극(251)을 형성한다.First, as shown in FIG. 4A, a substrate 220 having a thin film transistor, a pixel, a storage capacitor, data, and a gate pad region is prepared, and then a metal material having excellent reflection characteristics is deposited on the substrate 220. After that, the pixel electrode 251 is patterned to form a pixel electrode 251.
이어서, 도 4b에 도시한 바와 같이, 상기 화소전극(251)의 일부와 접속하는 박막트랜지스터의 소스/드레인전극(221a, 221b) 및 n+ 비정질실리콘 패턴(231)을 형성함과 동시에, 화소전극(251)과 접속하는 스토리지 하부전극(223) 및 데이터패드(225)를 함께 형성한다.Subsequently, as shown in FIG. 4B, the source / drain electrodes 221a and 221b and the n + amorphous silicon pattern 231 of the thin film transistor connected to a part of the pixel electrode 251 are formed and the pixel electrode ( The storage lower electrode 223 and the data pad 225 connected to the 251 are formed together.
그 다음, 도 4c에 도시한 바와 같이, 소스 및 드레인전극(221a,221b)을 포함하는 기판(220) 상에 비정질실리콘, 절연막 및 게이트전극물질을 순차적으로 증착한 다음, 이를 패터닝하여 박막트랜지스터의 오믹접촉층(233), 액티브층(237), 게이트절연막(139) 및 게이트전극(141)을 형성함과 동시에 스토리지 상부전극(243) 및 게이트패드(244)를 함께 형성한다.Next, as shown in FIG. 4C, amorphous silicon, an insulating film, and a gate electrode material are sequentially deposited on the substrate 220 including the source and drain electrodes 221a and 221b, and then patterned to form a thin film transistor. The ohmic contact layer 233, the active layer 237, the gate insulating layer 139, and the gate electrode 141 are formed together with the storage upper electrode 243 and the gate pad 244 together.
상기와 같이, 본 발명은 오믹접촉층, 액티브층, 게이트절연막 및 게이트전극을 1회 마스크 공정을 통하여 형성하고, 보호막 형성을 생략함에 따라, 종래에 비하여 공정을 더욱 단순활 할 수 있다.As described above, according to the present invention, the ohmic contact layer, the active layer, the gate insulating film, and the gate electrode are formed through a single mask process, and the protective film is omitted, thereby simplifying the process.
한편, 발명은 도면에 도시하진 않았지만, 박막트랜지스터 상부에 보호막을 형성할 수도 있다. 이와 같이 보호막을 형성하게 되면, 마스크 공정수가 1회 추가되어 종래와 동일해 지지만, 본 발명에서는 회절마스크를 사용하지 않기 때문에 재료비 측면에서 더욱 유리하다.On the other hand, although the invention is not shown in the drawings, it is also possible to form a protective film on the thin film transistor. When the protective film is formed in this way, the number of mask steps is added once, which is the same as in the prior art. However, in the present invention, since the diffraction mask is not used, it is more advantageous in terms of material cost.
또한, 본 발명은 액티브층이 기판의 뒷면에 노출되어 있기 때문에 투과형 모드시 백라이트광 차단이 이루어지지 않아 광누설전류(photo current leakage)가 커지게 되는 문제점을 야기하게 된다. 따라서, 본 발명은 백라이트가 사용되지 않는 반사형 액정표시소자에 적합한 구조이다. 그러나, 상기 액티브층에 대응하는 기판의 뒷면에 블랙매트릭스와 같이 빛을 차단할 수 있는 수단을 형성하여 투과형 모드에 적용할 수도 있다.In addition, in the present invention, since the active layer is exposed to the back side of the substrate, backlight light blocking is not performed in the transmissive mode, thereby causing a problem of increasing photo current leakage. Therefore, the present invention is a structure suitable for a reflective liquid crystal display device in which no backlight is used. However, it may be applied to the transmissive mode by forming a means for blocking light, such as a black matrix on the back of the substrate corresponding to the active layer.
상술한 바와 같이, 본 발명은 소스/드레인 전극을 먼저 형성한 후, 오믹콘택층, 액티브층, 게이트절연막 및 게이트전극을 1회의 마스크를 통하여 형성한 다음, 화소전극을 형성하는 3마스크 공정을 통하여 액정표시소자를 제작함으로써, 생산성을 향상시킬 수 있다.As described above, according to the present invention, a source / drain electrode is first formed, and then an ohmic contact layer, an active layer, a gate insulating layer, and a gate electrode are formed through one mask, and then a pixel mask is formed to form a pixel electrode. By manufacturing a liquid crystal display element, productivity can be improved.
또한 본 발명은 소스/드레인 전극을 먼저 형성한 후, 오믹콘택층, 액티브층, 게이트절연막 및 게이트전극을 1회의 마스크를 통하여 형성한 다음, 화소전극 및 보호막을 형성하으로써, 회절마스크를 사용하지 않고도 4마스크를 통하여 액정표시소자를 제작할 수 있으며, 이에 따라 재료비를 절감할 수 있다.In addition, according to the present invention, the source / drain electrodes are first formed, the ohmic contact layer, the active layer, the gate insulating layer, and the gate electrode are formed through one mask, and then the pixel electrode and the protective layer are formed, thereby eliminating the use of a diffraction mask. It is possible to manufacture the liquid crystal display device through the four masks, thereby reducing the material cost.
도 1은 일반적인 액정표시소자의 개략적인 단면도.1 is a schematic cross-sectional view of a general liquid crystal display device.
도 2는 종래 4마스크 공정을 통한 액정표시소자의 제조방법을 도시한 공정수순도.2 is a process flowchart showing a method of manufacturing a liquid crystal display device through a conventional four mask process.
도 3은 본 발명에 따른 액정표시소자의 제조방법을 도시한 공정수순도.3 is a process flowchart showing the manufacturing method of the liquid crystal display device according to the present invention.
도 4는 본발명의 다른 실시예.4 is another embodiment of the present invention.
*** 도면의 주요부분에 대한 부호의 설명 ****** Explanation of symbols for main parts of drawing ***
121a, 221a: 소스전극 121b, 221b: 드레인전극121a, 221a: source electrode 121b, 221b: drain electrode
123, 223: 스토리지 하부전극 125, 225: 데이터패드123, 223: storage lower electrode 125, 225: data pad
133, 233: 오믹접촉층 137, 237: 액티브층133 and 233: ohmic contact layer 137 and 237: active layer
139, 239: 게이트절연막 141, 241: 게이트전극139 and 239 gate insulating films 141 and 241 gate electrodes
144, 244: 게이트패드 151, 251: 화소전극144 and 244 gate pads 151 and 251 pixel electrodes
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| KR101050351B1 (en) * | 2004-09-24 | 2011-07-19 | 엘지디스플레이 주식회사 | Thin film transistor and its manufacturing method |
| KR20060100872A (en) | 2005-03-18 | 2006-09-21 | 삼성전자주식회사 | Transflective liquid crystal display panel and manufacturing method thereof |
| KR101241138B1 (en) * | 2006-06-20 | 2013-03-18 | 엘지디스플레이 주식회사 | Organic Thin Film Transistor Liquid Crystal Display Device and the method for fabricating thereof |
| KR101350408B1 (en) * | 2006-12-18 | 2014-01-10 | 엘지디스플레이 주식회사 | Array substrate for liquid crystal display device and method for fabricating the same |
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2002
- 2002-12-27 KR KR10-2002-0085620A patent/KR100511353B1/en active IP Right Grant
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