KR100489531B1 - Method for manufacturing capacitor - Google Patents

Method for manufacturing capacitor Download PDF

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KR100489531B1
KR100489531B1 KR10-2002-0037074A KR20020037074A KR100489531B1 KR 100489531 B1 KR100489531 B1 KR 100489531B1 KR 20020037074 A KR20020037074 A KR 20020037074A KR 100489531 B1 KR100489531 B1 KR 100489531B1
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film
dielectric
si3n4
metal film
metal
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KR20040001754A (en
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이영성
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동부아남반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7687—Thin films associated with contacts of capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

본 발명은 MIM 캐패시터(Metal-Insulator-Metal capacitor)를 제조하는 방법에 관한 것이다. 종래의 기술에 있어서는 MIM 캐패시터의 유전체로서 PE-Si3N4의 장점을 극대화 할 수 없었다. 본 발명은 MIM 캐패시터에 7.0 이상의 고유전율을 갖는 PE-Si3N4 유전체를 적용하여 PE-Si3N4 막을 제조하는 경우 NH3 플라즈마(plasma) 열처리를 적용해서 Si-H의 질화 반응을 유도하여 Si-H 결합을 제거한다. 따라서, PE-Si3N4 막의 절연 특성이 향상되는 효과가 있다.The present invention relates to a method for manufacturing a MIM capacitor (Metal-Insulator-Metal capacitor). In the prior art, the advantages of PE-Si3N4 as the dielectric of the MIM capacitor could not be maximized. In the present invention, when a PE-Si3N4 film is manufactured by applying a PE-Si3N4 dielectric having a high dielectric constant of 7.0 or higher to a MIM capacitor, an NH3 plasma heat treatment is applied to induce a nitriding reaction of Si-H to remove Si-H bonds. do. Therefore, there is an effect that the insulating properties of the PE-Si3N4 film are improved.

Description

캐패시터의 제조 방법{METHOD FOR MANUFACTURING CAPACITOR}Manufacturing method of a capacitor {METHOD FOR MANUFACTURING CAPACITOR}

본 발명은 캐패시터(capacitor)의 제조 방법에 관한 것으로, 특히, MIM 캐패시터(Metal-Insulator-Metal capacitor)를 제조하는 방법에 관한 것이다.The present invention relates to a method of manufacturing a capacitor, and more particularly, to a method of manufacturing a MIM capacitor (Metal-Insulator-Metal capacitor).

최근들어 반도체장치(semiconductor device)는 멀티미디어 기능의 향상을 위하여 칩내에 메모리 셀 어레이부 및 주변회로가 함께 장착된 형태로 개발되고 있으며, 고용량 정보의 고속 처리에 적합한 캐패시터의 구현이 핵심 기술로서 대두되고 있다.Recently, a semiconductor device has been developed in which a memory cell array unit and a peripheral circuit are mounted together in a chip to improve multimedia functions. The implementation of a capacitor suitable for high-speed processing of high-capacity information is emerging as a core technology. have.

한편, PIP 캐패시터(Polysilicon-Insulator-Polysilicon capacitor)의 경우 상, 하부전극을 폴리실리콘(polysilicon)으로 사용하기 때문에 비저항이 크고 디플리션(depletion) 현상에 의한 기생 캐패시턴스가 작용하는 문제점이 있는 반면 MIM 캐패시터의 경우에는 상기의 문제점을 유발하지 않으므로 고속, 고집적 복합반도체의 구현에 매우 적합한 것으로 평가되고 있다.On the other hand, in the case of PIP capacitors (Polysilicon-Insulator-Polysilicon capacitors), the upper and lower electrodes are used as polysilicon, so there is a problem that the parasitic capacitance due to the depletion phenomenon is large while the MIM Since the capacitor does not cause the above problem, it is evaluated to be very suitable for the implementation of high speed, high density composite semiconductor.

MIM 캐패시터에서 유전막은 전하 저장의 역할을 담당하는 부분으로서 소자 특성에 부합하기 위해서는 일정 수준 이상의 유전률 및 절연성의 확보가 필수적이다. 특히, 절연성의 경우 막질의 결함에 크게 영향을 받으므로, 절연성의 향상을 위해서는 막의 제조 및 후처리 시 결함을 최소화하기 위한 공정 조건의 적용이 고려되어야 한다.In the MIM capacitor, the dielectric layer plays a role of charge storage, and it is necessary to secure a dielectric constant and insulation level above a certain level in order to meet device characteristics. In particular, in the case of insulation is greatly affected by defects in the film quality, in order to improve the insulation, the application of process conditions for minimizing the defects during the manufacture and post-treatment of the film should be considered.

아날로그 복합 반도체소자의 MIM용 유전체는 PECVD 방법을 이용한 SiO2, Si3N4 등이 혼용되고 있으나 1.0fF/μm2 이상의 고 유전밀도 구현을 위해서는 7.0 이상의 유전률을 갖는 PE-Si3N4의 적용이 바람직하다.As the dielectric for MIM of the analog composite semiconductor device, SiO2, Si3N4, etc. are mixed by PECVD, but PE-Si3N4 having a dielectric constant of 7.0 or higher is preferable to achieve high dielectric density of 1.0fF / μm 2 or higher.

한편, MIM 캐패시터용 유전체로 적용되기 위해서는 고유전률 뿐 아니라 소자 특성에 부합하는 절연성이 확보되어야 하는데, PE-Si3N4의 경우 막질 내의 높은 결함 밀도로 인하여 절연성이 취약하므로 적용에 많은 어려움이 있다.On the other hand, in order to be applied as a dielectric for MIM capacitors, the insulation must be secured according to the device characteristics as well as the high dielectric constant. PE-Si3N4 has many difficulties in application because the insulation is weak due to the high defect density in the film.

종래의 PE-Si3N4의 절연성 개선을 위한 기술로는 PE-SiO2와 PE-Si3N4의 적층형 유전체를 형성하는 방법 및 PE-Si3N4를 O3 등의 산화 분위기에서 열처리하여 표면 산화를 유도하는 방법 등이 개발되어 왔다. MIM 캐패시터로서 PE-SiO2 및 PE-Si3N4의 적층형 유전체를 적용할 경우 절연성의 개선이 가능하나 단일 PE-Si3N4 막을 적용하는 경우에 비하여 상대적으로 낮은 유전 밀도를 나타내는 단점이 있다. PE-Si3N4의 표면 산화를 유도하는 방법을 적용하는 경우 전하의 계면 트랩(trap) 억제를 통하여 유전 밀도의 감소 없이 절연성 향상이 가능하나 막질 자체 결함을 완화시킨 것이 아니므로 부분적 개선 효과만을 기대할 수 있다.As a technique for improving insulation of conventional PE-Si3N4, a method of forming a multilayer dielectric of PE-SiO2 and PE-Si3N4 and a method of inducing surface oxidation by heat-treating PE-Si3N4 in an oxidizing atmosphere such as O 3 are developed. Has been. In the case of applying a multilayer dielectric of PE-SiO2 and PE-Si3N4 as a MIM capacitor, insulation can be improved, but it has a disadvantage of showing a relatively low dielectric density compared to the case of applying a single PE-Si3N4 film. In case of applying the method of inducing surface oxidation of PE-Si3N4, it is possible to improve insulation without reducing dielectric density by suppressing interface trap of charge, but only partial improvement can be expected because it does not alleviate the defect of the film quality itself. .

따라서, 이와 같은 종래의 기술에 있어서는 MIM 캐패시터의 유전체로서 PE-Si3N4의 장점을 극대화 할 수 없었다.Therefore, in this conventional technique, the advantages of PE-Si3N4 as the dielectric of the MIM capacitor could not be maximized.

상기한 바에 의하여 안출된 본 발명은, MIM 캐패시터에 7.0 이상의 고유전율을 갖는 PE-Si3N4 유전체를 적용하여 PE-Si3N4 막을 제조하는 경우 NH3 플라즈마(plasma) 열처리를 적용해서 Si-H의 질화 반응을 유도하여 Si-H 결합을 제거하는 캐패시터 제조 방법을 제공하는 데 그 목적이 있다.The present invention devised as described above, in the case of manufacturing a PE-Si3N4 film by applying a PE-Si3N4 dielectric having a high dielectric constant of 7.0 or more to the MIM capacitor induces the nitriding reaction of Si-H by applying an NH3 plasma heat treatment It is an object of the present invention to provide a method for manufacturing a capacitor to remove the Si-H bond.

캐패시터용 유전체의 절연 특성은 전극으로부터 유전체에 주입된 전하의 트랩 내성으로 표현된다. 유전체 내 전하의 트랩은 주로 에너지 상태가 높은 결함부에서 발생하는데, 이러한 결함은 전극과의 계면 스트레스(stress)에 의하여 발생하는 구조 결함 및 막질 자체의 고유 결함으로 구분된다. 따라서, 절연 특성의 향상을 위해서는 결함의 제어가 요구되며, 유전체 제조의 단일 공정 측면에서 볼 때 막질의 고유 결함을 감소시키는 것이 가장 중요하다.The insulating property of the capacitor dielectric is expressed by the trap resistance of the charge injected from the electrode to the dielectric. The trap of charge in the dielectric occurs mainly in defects of high energy state, and these defects are classified into structural defects caused by interfacial stress with the electrode and inherent defects in the film quality itself. Therefore, control of defects is required to improve insulation characteristics, and it is most important to reduce intrinsic defects of film quality in view of a single process of dielectric manufacturing.

한편, PE-Si3N4는 SiH4, NH3 원료 가스가 플라즈마 활성 상태에서 형성되며 Si-N 결합 이외에 Si-H, N-H 결합 구조를 가진다. Si-H 및 N-H는 다양한 결합 상태를 나타내는데, 일반적으로 N-H 결합의 경우 후속 열처리에 의하여 안정한 상태로 존재하는 반면 Si-H 결합의 경우에는 위크 본딩(weak bonding)의 상태로 잔류하게 된다. PE-Si3N4에 전압이 인가될 경우 Si-H 결합의 Si 원자는 쉽게 여기되어 전하의 트랩 사이트(trap site)로 작용하며 하핑(hopping) 현상에 의하여 전류 누설을 유발한다. 즉, PE-Si3N4의 절연성 향상을 위하여 막질 내 결함으로 작용하는 Si-H 결합의 수를 감소시켜야 한다.On the other hand, PE-Si3N4 has a SiH4, NH3 source gas is formed in a plasma active state and has a Si-H, N-H bond structure in addition to the Si-N bond. Si-H and N-H exhibit various bonding states. In general, N-H bonds remain stable by subsequent heat treatment, whereas Si-H bonds remain in a state of weak bonding. When a voltage is applied to PE-Si3N4, the Si atoms of the Si-H bond are easily excited to act as trap sites of charge and cause current leakage by a hopping phenomenon. That is, in order to improve the insulation of PE-Si3N4, the number of Si-H bonds acting as defects in the film should be reduced.

이하, 첨부된 도면을 참조하여 본 발명에 따른 실시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1 내지 도 5는 본 발명에 따른 캐패시터의 제조 방법의 일 실시예를 단계별로 나타낸 단면도이다.1 to 5 are cross-sectional views showing one embodiment of a method of manufacturing a capacitor according to the present invention.

먼저, 도 1과 같이 반도체 소자 및 일부 금속 배선층이 형성된 기판의 상부에 층간 절연막(20), 제 1 금속막(21), 및 ARC Ti/TiN(또는 TiN)(22)을 순차적으로 적층한다. 이때, TiN의 적층 방법으로는 PVD, TiCl4를 이용한 CVD가 있으나 MIM의 하부전극으로 적용되기 위해서는 유전체의 특성 저하를 유발하는 Cl 성분이 배제되어야 하므로 PVD 방법의 적용이 바람직하다.First, as shown in FIG. 1, an interlayer insulating film 20, a first metal film 21, and an ARC Ti / TiN (or TiN) 22 are sequentially stacked on an upper portion of a substrate on which a semiconductor device and some metal wiring layers are formed. At this time, the deposition method of TiN includes CVD using PVD and TiCl 4 , but in order to be applied as a lower electrode of MIM, Cl component causing deterioration of dielectric properties should be excluded, and thus, PVD method is preferable.

도 2와 같이 표면에 포토레지스트(Photo Resist : PR)를 패터닝(patterning)하고 건식 식각 공정을 적용해서 ARC Ti/TiN(또는 TiN)(22)을 선택적으로 제거하여 MIM 하부전극(21-1) 및 하부 금속 배선층(21-2)을 형성한다. HDP oxide CVD 방법을 사용하여 전표면에 절연층(23) 형성한 후, CMP 공정을 실시하여 절연층(23)을 평탄화시킨다. 이때, MIM 하부 전극(21-1)을 이루는 ARC 층은 절연층(23)에 매립되기 전까지 전면 노출되므로 노치 효과에 의한 계면 분리 현상이 발생하지 않는다.As shown in FIG. 2, ARC Ti / TiN (or TiN) 22 is selectively removed by patterning a photoresist (PR) on a surface and applying a dry etching process to the MIM lower electrode 21-1. And the lower metal wiring layer 21-2. After the insulating layer 23 is formed on the entire surface using the HDP oxide CVD method, the CMP process is performed to planarize the insulating layer 23. At this time, the ARC layer constituting the MIM lower electrode 21-1 is entirely exposed until it is embedded in the insulating layer 23, so that the interface separation phenomenon due to the notch effect does not occur.

도 3과 같이 절연층(23)의 불필요한 부분을 제거하여 MIM 유전체 및 제 2 금속막이 매립될 콘택홀(contact hole)을 형성한다.As shown in FIG. 3, an unnecessary portion of the insulating layer 23 is removed to form a contact hole in which the MIM dielectric and the second metal film are embedded.

도 4와 같이 콘택홀의 표면에 PE-Si3N4 유전체(24)를 증착한다. 증착시 플라즈마를 이용하여 SiH4, NH3 가스를 반응시키며 증착된 막의 Si-H 결합을 질화시켜 Si-H 결합을 제거하기 위하여 NH3 플라즈마 열처리를 실시한다. 플라즈마 열처리 시 N 원자의 침투 깊이는 100Å 미만이므로 2.0fF/μm2의 유전 밀도를 얻고자 하는 경우(~400Å) 증착 완료 이후 열처리를 적용하는 방식으로는 충분한 열처리 효과를 기대할 수 없다. 따라서, 10 내지 100Å 두께의 막 증착을 반복 실시하며 각 단계의 진행 이후 플라즈마 열처리 과정을 적용하여 목표 두께의 막을 형성하는 다단계 증착법을 적용한다. 증착 및 NH3 플라즈마 열처리의 반복 진행을 통하여 전극과의 계면 부위 뿐 아니라 막 내부 Si-H 결합의 밀도를 감소시킬 수 있으므로 절연성 향상에 매우 효과적이다.As shown in FIG. 4, a PE-Si 3 N 4 dielectric material 24 is deposited on the surface of the contact hole. SiH4 and NH3 gases are reacted using plasma during deposition, and NH3 plasma heat treatment is performed to remove Si-H bonds by nitriding Si-H bonds in the deposited film. Since the penetration depth of N atoms during the plasma heat treatment is less than 100 kW, when the dielectric density of 2.0 fF / μm 2 (~ 400 kW) is applied, a sufficient heat treatment effect cannot be expected by applying the heat treatment after the deposition is completed. Accordingly, a multi-step deposition method of repeatedly forming a film having a thickness of 10 to 100 mW and applying a plasma heat treatment process after each step is performed is applied. It is very effective to improve the insulation since the density of Si-H bonds in the film as well as the interface region with the electrode can be reduced through the repeated progress of deposition and NH3 plasma heat treatment.

PE-Si3N4 막에는 다량의 모빌 하이드로겐(mobile hydrogen)이 존재하며 이는 유전체의 초기 절연 특성을 저하시키는 원인이 된다. 따라서, 유전체의 형성 이후 모빌 하이드로겐을 제거하기 위한 열처리를 실시한다. 열처리 온도는 300 내지 400℃, 분위기는 N2 혹은 O2, 유지 시간은 10 내지 30분 가량이 적절하다.There is a large amount of mobile hydrogen in the PE-Si3N4 film, which causes a decrease in the initial insulating properties of the dielectric. Therefore, heat treatment is performed to remove the mobile hydrogen after the formation of the dielectric. The heat treatment temperature is 300 to 400 ° C., the atmosphere is appropriately N 2 or O 2 , and the holding time is about 10 to 30 minutes.

콘택홀에 제 2 금속막(25)을 매립한다. 상부 전극으로 적용될 제 2 금속막(25)의 재질로는 TiN, Ti/TiN, W 등이 적합하며 금속 층간에 내장되는 이유로 두께 제한이 있으므로 이를 고려하여 재질을 선택하여야 한다.The second metal film 25 is buried in the contact hole. As the material of the second metal film 25 to be applied as the upper electrode, TiN, Ti / TiN, W, and the like are suitable, and since the thickness is limited because of being embedded between the metal layers, the material should be selected in consideration of this.

표면에 CMP 공정을 실시하여 평탄화시킨다. CMP 공정은 콘택홀을 제외한 부위의 제 2 금속막(25)의 제거 및 PE-Si3N4 유전체(24) 제거의 제 2 단계로 수행된다. PE-Si3N4 유전체(24) 제거시 절연층(23)의 일부가 연마되는데, 이 때 본 공정 진행 이전 절연층(23)의 두께는 PE-Si3N4 유전체(24) 및 절연층(23)의 상대적 연마 속도를 고려하여 설정되어야 한다.The surface is subjected to a CMP process to planarize. The CMP process is performed in the second step of removing the second metal film 25 and removing the PE-Si 3 N 4 dielectric material 24 in the portions excluding the contact holes. When the PE-Si3N4 dielectric 24 is removed, a part of the insulating layer 23 is polished. At this time, the thickness of the insulating layer 23 before the process proceeds is relative to the polishing of the PE-Si3N4 dielectric 24 and the insulating layer 23. It should be set in consideration of speed.

도 6과 같이 PE-oxide CVD를 이용하여 전 표면에 층간 절연막(26)을 증착한다. 층간 절연막(26)을 선택적으로 식각하여 비아홀(via hole)을 형성한다. 비아홀에 금속을 채워 비아 전극(27)을 형성한다. CMP 공정을 실시하여 표면을 평탄화시킨다. 전 표면에 제 3 금속막(28) 및 ARC(29)를 증착한다. 불필요한 ARC(29) 및 제 3 금속막(28)을 제거해서 상부 금속 배선층을 형성하여 금속 배선층간 내장된 MIM 캐패시터를 완성된다.As shown in FIG. 6, the interlayer insulating layer 26 is deposited on the entire surface by using PE-oxide CVD. The interlayer insulating layer 26 is selectively etched to form via holes. Via electrodes 27 are formed by filling the via holes with metal. A CMP process is performed to planarize the surface. The third metal film 28 and the ARC 29 are deposited on the entire surface. Unnecessary ARC 29 and the third metal film 28 are removed to form an upper metal wiring layer to complete the built-in MIM capacitor between the metal wiring layers.

이상에서 설명한 바와 같이, 본 발명은 MIM 캐패시터에 7.0 이상의 고유전율을 갖는 PE-Si3N4 유전체를 적용하여 PE-Si3N4 막을 제조하는 경우 NH3 플라즈마 열처리를 적용해서 Si-H의 질화 반응을 유도하여 Si-H 결합을 제거한다. 따라서, PE-Si3N4 막의 절연 특성이 향상되는 효과가 있다.As described above, in the present invention, when a PE-Si3N4 film is manufactured by applying a PE-Si3N4 dielectric having a high dielectric constant of 7.0 or higher to a MIM capacitor, Si-H is induced by applying an NH3 plasma heat treatment to induce a nitride reaction of Si-H. Remove the bond. Therefore, there is an effect that the insulating properties of the PE-Si3N4 film are improved.

도 1 내지 도 5는 본 발명에 따른 캐패시터의 제조 방법의 일 실시예를 단계별로 나타낸 단면도.1 to 5 are cross-sectional views showing one embodiment of a method of manufacturing a capacitor according to the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

20 : 층간 절연막 21, 25, 28 : 제 1, 제 2, 제 3 금속막20: interlayer insulating film 21, 25, 28: first, second, third metal film

21-1 : MIM 하부전극 21-1 : 하부 금속 배선층21-1: MIM lower electrode 21-1: Lower metal wiring layer

22 : ARC Ti/TiN 23 : 절연층22: ARC Ti / TiN 23: insulating layer

24 : PE-Si3N4 유전체 26 : 층간 절연막24: PE-Si3N4 dielectric material 26: interlayer insulating film

27 : 비아 전극 29 : ARC27: via electrode 29: ARC

Claims (10)

캐패시터 제조방법으로서,As a capacitor manufacturing method, 기판의 상부에 층간 절연막, 제 1 금속막, 및 ARC Ti/TiN을 순차적으로 적층하는 제 1 단계와,A first step of sequentially laminating an interlayer insulating film, a first metal film, and ARC Ti / TiN on the substrate; 상기 ARC Ti/TiN을 선택적으로 제거하여 MIM 하부전극 및 하부 금속 배선층을 형성하는 제 2 단계와,Selectively removing the ARC Ti / TiN to form a MIM lower electrode and a lower metal wiring layer; 전표면에 절연층을 형성한 후, 표면을 평탄화시키는 제 3 단계와,A third step of planarizing the surface after forming the insulating layer on the entire surface, 상기 절연층의 불필요한 부분을 제거하여 콘택홀을 형성하는 제 4 단계와,A fourth step of forming a contact hole by removing an unnecessary portion of the insulating layer; 상기 콘택홀의 표면에 PE-Si3N4 유전체를 증착하는 제 5 단계와,Depositing a PE-Si3N4 dielectric on the surface of the contact hole; 상기 콘택홀에 제 2 금속막을 매립하는 제 6 단계와,A sixth step of embedding a second metal film in the contact hole; 표면을 평탄화시키는 제 7 단계와,A seventh step of flattening the surface, 전 표면에 층간 절연막을 형성하는 제 8 단계와,An eighth step of forming an interlayer insulating film on the entire surface; 상기 층간 절연막을 선택적으로 제거하여 비아홀을 형성하는 제 9 단계와,A ninth step of selectively removing the interlayer insulating film to form a via hole; 상기 비아홀에 금속을 채워 비아 전극을 형성하는 제 10 단계와,A tenth step of forming a via electrode by filling a metal in the via hole; 표면을 평탄화시키는 제 11 단계와,An eleventh step of flattening the surface, 전 표면에 제 3 금속막 및 ARC를 차례로 적층하는 제 12 단계와,A twelfth step of sequentially laminating the third metal film and the ARC on the entire surface; 불필요한 상기 ARC 및 상기 제 3 금속막을 제거해서 상부 금속 배선층을 형성하는 제 13 단계를 포함하는 캐패시터의 제조 방법.And removing the unnecessary ARC and the third metal film to form an upper metal wiring layer. 제 1 항에 있어서, 상기 제 1 단계는 PVD 방법으로 적층하는 것을 특징으로 하는 캐패시터의 제조 방법.The method of claim 1, wherein the first step is to laminate by PVD method. 제 1 항에 있어서, 상기 제 3 단계는 HDP oxide CVD 방법을 사용하여 전표면에 절연층을 형성하는 것을 특징으로 하는 캐패시터의 제조 방법.The method of claim 1, wherein the third step is to form an insulating layer on the entire surface by using the HDP oxide CVD method. 제 1 항에 있어서, 상기 제 3 단계는 CMP 공정을 실시하여 표면을 평탄화시키는 것을 특징으로 하는 캐패시터의 제조 방법.The method of claim 1, wherein the third step is to perform a CMP process to planarize the surface. 제 1 항에 있어서, 상기 제 5 단계는 플라즈마를 이용하여 SiH4, NH3 가스를 반응시키고 NH3 플라즈마 열처리를 실시하여 상기 콘택홀의 표면에 PE-Si3N4 유전체를 증착하는 것을 특징으로 하는 캐패시터의 제조 방법.The method of claim 1, wherein the fifth step comprises depositing a PE-Si 3 N 4 dielectric on the surface of the contact hole by reacting SiH 4 and NH 3 gas using plasma and performing NH 3 plasma heat treatment. 제 5 항에 있어서, 상기 PE-Si3N4 유전체의 증착은 10 내지 100Å 두께의 막 증착을 반복 실시하며 각 단계의 진행 이후 플라즈마 열처리 과정을 적용하여 목표 두께의 막을 형성하는 다단계 증착법을 적용하는 것을 특징으로 하는 캐패시터의 제조 방법.6. The method of claim 5, wherein the deposition of the PE-Si3N4 dielectric is performed by repeatedly depositing a film having a thickness of 10 to 100 하며 and applying a multi-step deposition method to form a film having a target thickness by applying a plasma heat treatment process after each step. The manufacturing method of a capacitor. 제 6 항에 있어서, 상기 열처리 온도는 300 내지 400℃, 분위기는 N2 혹은 O2, 유지 시간은 10 내지 30분으로 설정되는 것을 특징으로 하는 캐패시터의 제조 방법.The method of claim 6, wherein the heat treatment temperature is 300 to 400 ℃, the atmosphere is N 2 or O 2 , the holding time is set to 10 to 30 minutes. 제 1 항에 있어서, 상기 제 2 금속막은 TiN, Ti/TiN, W 중에 적어도 하나인 것을 특징으로 하는 캐패시터의 제조 방법.The method of claim 1, wherein the second metal film is at least one of TiN, Ti / TiN, and W. 제 1 항에 있어서, 상기 제 7 단계는 CMP 공정을 실시하여 표면을 평탄화시키는 것을 특징으로 하는 캐패시터의 제조 방법.The method of claim 1, wherein the seventh step is performed by a CMP process to planarize the surface. 제 9 항에 있어서, 상기 CMP 공정은 상기 콘택홀을 제외한 부위의 상기 제 2 금속막을 제거하고 상기 PE-Si3N4 유전체를 제거하는 단계로 수행되는 것을 특징으로 하는 캐패시터의 제조 방법.The method of claim 9, wherein the CMP process is performed by removing the second metal film except for the contact hole and removing the PE-Si 3 N 4 dielectric.
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