KR100434553B1 - A single electron transistor using granular nano cry stais and a fabricating method thereof - Google Patents

A single electron transistor using granular nano cry stais and a fabricating method thereof Download PDF

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KR100434553B1
KR100434553B1 KR1019970041593A KR19970041593A KR100434553B1 KR 100434553 B1 KR100434553 B1 KR 100434553B1 KR 1019970041593 A KR1019970041593 A KR 1019970041593A KR 19970041593 A KR19970041593 A KR 19970041593A KR 100434553 B1 KR100434553 B1 KR 100434553B1
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island layer
island
grains
transistor
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KR19990018417A (en
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이조원
김병만
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삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
    • H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Abstract

PURPOSE: A single electron transistor and a manufacturing method thereof are provided to improve the easiness of fabrication and to sustain a tunnel barrier without degradation for a long time at room temperature by forming an island layer using metal grains. CONSTITUTION: An oxidized surface(102) is formed on a semiconductor substrate(101). An island layer(103) made of metallic grains is formed on the oxidized surface of the substrate. The diameter of the metallic grain is 5 nm or less. A source(104) and a drain(105) are spaced apart from each other on the island layer. A tunnel barrier of the island layer is formed with a vacant space between metallic grains. The width of the vacant space is 5 nm or less.

Description

단일 전자 트랜지스터 및 그 제조 방법{A single electron transistor using granular nano cry stais and a fabricating method thereof}A single electron transistor using granular nano cry stais and a fabricating method

본발명은 단일 전자 트랜지스터에 관한 것으로, 상세하게는 증착을 통해 얻은 나노 미터 단위의 결정립들을 응용하여 제조된 단일 전자 트랜지스터(single electron transistor) 및 그 제조 방법에 관한 것이다.The present invention relates to a single electron transistor, and more particularly, to a single electron transistor (single electron transistor) manufactured by applying the nanometer grains obtained through deposition and a method of manufacturing the same.

도 1a 및 도 1b는 종래의 단일 전자 트랜지스터들의 개략적 수직 단면도이다. 종래의 단일 전자 트랜지스터는, 도 1a에 도시된 바와 같이, 실리콘 기판(11) 상에 소스(source)(12)와 드레인(drain)(13) 사이에 2개의 터널 장벽(tunnel barrier)(14)을 만들어 아일런드(island)(15)를 형성시킨 구조이거나, 혹은 도 1b에 도시된 바와 같이, 실리콘 기판(21) 상에 SiO2 절연막(22)를 형성하고, 그 상면에 소스(23)와 드레인(24)을 형성한 후, 유전체(25) 속에 금속이나 반도체를 물리적 혹은 화학적인 증착을 통해 나노미터(nm) 크기인 알갱이 모양의 아일런드(15)를 형성시킨 구조이다.1A and 1B are schematic vertical cross-sectional views of a conventional single electronic transistor. A conventional single electron transistor has two tunnel barriers 14 between a source 12 and a drain 13 on a silicon substrate 11, as shown in FIG. 1A. To form an island 15, or as shown in FIG. 1B, the SiO 2 insulating film 22 is formed on the silicon substrate 21, and the source 23 and the drain are formed on the upper surface thereof. After forming (24), a grain-shaped island 15 having a nanometer size is formed by physical or chemical vapor deposition of a metal or semiconductor in the dielectric 25.

그러나, 참고 문헌 T.Wada etal Jpn.J.Appl.Phys 34,12B(1995)6961 및 K.Matsumoto etal Appl.Phys.Lett 68(1996)34에 따르면, 도 1a에 도시된 바와 같은 단일 전자 트랜지스터의 경우 아일런드(15)의 크기를 나노미터 크기로 균일하게 제어하는 것이 매우 어렵다. 특히, SPM(scanning probe microscopy)을 응용할 경우 터널 장벽이 공기중에서 열화되기 때문에 단일 전자 트랜지스터의 작동 재현성이 전혀없다. 그리고 참고문헌 W.Chen etal Appl.Phys.Lett 66(1995)3383 및 A.Dutta etal Jpn.J.Appl.Phys 36,6B(1997)4038에 의하면, 도면 1b에 도시된 바와 같은 단일 전자 트랜지스터의 경우, 또한 여러 번의 복잡한 공정을 거쳐야 하므로 제조상어려움이 따른다.However, according to references T. Wada et al Jpn. J. Appl. Phys 34,12B (1995) 6961 and K. Matsmoto et al Appl. Phys. Lett 68 (1996) 34, a single electronic transistor as shown in FIG. In this case, it is very difficult to uniformly control the size of the island 15 to a nanometer size. In particular, SPM (scanning probe microscopy) applications have no operational reproducibility of single-electron transistors because tunnel barriers are degraded in air. And according to references W. Chen et al Appl. Phys. Lett 66 (1995) 3383 and A. Dutta et al Jpn. J. Appl. Phys 36,6B (1997) 4038, a single electronic transistor as shown in FIG. In this case, it also has to go through several complicated processes, which leads to manufacturing difficulties.

따라서 재현성있는 상온 작동 단일 전자 트랜지스터를 구현하기 위해서는 공정이 간단하며 아일런드의 크기를 나노미터 크기로 쉽게 제어할 수 있는 새로운 구조 및 제조 방법이 요구된다.Thus, implementing reproducible, room temperature operated single-electron transistors requires a simple process and a new structure and fabrication method that can easily control the size of the island to nanometers.

본 발명은 상기와 같은 문제점을 개선하고자 창안된 것으로, 차세대 초고집적(1 Tb) 메모리 및 로직에 응용할 수 있도록, 298°K 이상의 상온에서 작동이 가능한 단일 전자 트랜지스터 및 그 제조 방법을 제공하는데 그 목적이 있다.The present invention was devised to improve the above problems, and to provide a single electronic transistor capable of operating at room temperature of 298 ° K or higher and a method of manufacturing the same, which can be applied to next generation ultra high density (1 Tb) memory and logic. There is this.

도 1a 및 도 1b는 각각 종래의 단일 전자 트랜지스터의 개략적인 수직 단면도이고,1A and 1B are schematic vertical cross-sectional views of a conventional single electron transistor, respectively,

도 2는 본 발명에 따른 단일 전자 트랜지스터의 개략적인 수직 단면도이다.2 is a schematic vertical cross-sectional view of a single electron transistor according to the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

11. 실리콘 기판 12. 소스11. Silicon substrate 12. Source

13. 드레인 14. 터널 장벽13. Drain 14. Tunnel Barrier

15. 아일런드15. Island

21. 실리콘 기판 22. SiO2 산화층21. Silicon substrate 22. SiO2 oxide layer

23. 소스 24. 드레인23. Source 24. Drain

25. 유전체 26. 금속 결정립25. Dielectric 26. Metal Grain

101. 실리콘 기판 102. SiO2 산화층101. Silicon Substrate 102. SiO2 Oxide Layer

103. 아일런드층(금속 결정립) 104. 소스103. Island layer (metal grain) 104. Source

105. 드레인105. Drain

상기와 같은 목적을 달성하기 위하여 본 발명에 따른 단일 전자 트랜지스터는, 그 상부가 산화된 반도체 기판; 상기 기판의 산화면 상에 증착된 5nm 이하의 금속 결정립들을 갖으며 결정립들 사이에 빈 공간이 형성된 아일런드층; 및 상기 아일런드층 상에 일정한 간격을 두고 형성된 소스 및 드레인;을 구비한 것을 특징으로 한다.In order to achieve the above object, a single electronic transistor according to the present invention includes a semiconductor substrate oxidized thereon; An island layer having metal grains of 5 nm or less deposited on the oxide surface of the substrate and having empty spaces formed between the grains; And a source and a drain formed at regular intervals on the island layer.

본 발명에 있어서, 상기 아일런드층의 아일런드의 터널 장벽은 결정립과 결정립 사이의 폭 5nm 이하의 빈공간을 이용하고, 상기 아일런드층은 두께가 10 nm 이하이며, 5nm 이하의 반도체 결정립으로 형성된 것이 바람직하다.In the present invention, the tunnel barrier of the island of the island layer uses an empty space having a width of 5 nm or less between the crystal grains and the grains, and the island layer has a thickness of 10 nm or less and formed of semiconductor grains of 5 nm or less. It is preferable.

또한, 상기와 같은 목적을 달성하기 위하여 본 발명에 따른 단일 전자 트랜지스터의 제조 방법은, (가) 표면이 소정의 두께로 산화된 반도체 기판 상에 금속을 증착하여 5nm 이하의 결정립들을 갖으며 결정립들 사이에 빈 공간이 형성된 두께 10 nm 이하의 아일런드층을 형성하는 단계; 및 (나) 상기 아일런드층 상에 서로 일정한 간격을 갖는 소스 및 드레인을 형성하는 단계;를 포함하는 것을 특징으로 한다.In addition, in order to achieve the above object, a method of manufacturing a single electronic transistor according to the present invention includes (a) depositing a metal on a semiconductor substrate whose surface is oxidized to a predetermined thickness, and having crystal grains of 5 nm or less; Forming an island layer having a thickness of 10 nm or less having an empty space formed therebetween; And (b) forming a source and a drain having a predetermined distance from each other on the island layer.

본 발명에 있어서, 상기 (가) 단계는 물리적 증착법 혹은 화학 기상 증착법에 의해 이루어지되, 상기 화학 기상 증착법은 금속 콜로이덜 증착법 혹은 랭뮤어 블로젯(LB; Langmuir-Blodgett)법 까지 포함하며, 상기 (나) 단계는 스캔닝 프로브 마이크로스코피(SPM; scanning probe microscopy)법에 의해 이루어지는 것이 바람직하다.In the present invention, the step (a) is performed by physical vapor deposition or chemical vapor deposition, the chemical vapor deposition method includes a metal colloidal deposition method or Langmuir-Blodgett (LB) method, the ( B) The step is preferably performed by a scanning probe microscopy (SPM) method.

이하 도면을 참조하면서 본 발명에 따른 단일 전자 트랜지스터 및 그 제조 방법을 상세하게 설명한다.Hereinafter, a single electronic transistor and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명에 따른 단일 전자 트랜지스터의 수직 단면도이다. 도시된 바와 같이, 본 발명에 따른 단일 전자 트랜지스터는 그 상부에 SiO2 절연막(102)이 형성된 실리콘 기판(101) 상에 5nm 이하의 금속 혹은 반도체 결정립(103)이 적층되고, 이 금속 결정립으로 이루어진 아일런드층(103) 상에 소스(104)와 드레인(105)이 일정한 간격을 두고 형성된 구조를 갖는다. 여기서, 아일런드층(103)의 두께는 10 nm 이하이고, 아일런드(결정립)의 크기는 5 nm 이하이다. 이와 같이 결정립의 크기를 5nm 이하로 제한해야 289°K 이상의 상온에서 단일 전자 트랜지스터가 동작한다. 이는 아일런드의 캐패시턴스가 작을수록 높은 온도에서 트랜지스터가 동작하기 때문인데, 아일런드의 결정립이 작을수록 캐패시턴스가 작아지는 이유에서 이다.2 is a vertical sectional view of a single electron transistor according to the present invention. As shown in the figure, a single electron transistor according to the present invention is a 5 nm or less metal or semiconductor crystal grains 103 stacked on a silicon substrate 101 having an SiO 2 insulating film 102 thereon, and an isle composed of the metal crystal grains. The source 104 and the drain 105 are formed on the run layer 103 at regular intervals. Here, the thickness of the island layer 103 is 10 nm or less, and the size of the island (crystal grain) is 5 nm or less. As such, the size of the grain should be limited to 5 nm or less to operate a single electronic transistor at room temperature of 289 ° K or more. This is because the smaller the capacitance of the island, the higher the transistor operates at a higher temperature. The smaller the grain size of the island, the smaller the capacitance.

이와 같은 구조의 단일 전자 트랜지스터의 제조 방법은 다음과 같다.The manufacturing method of the single electron transistor of such a structure is as follows.

먼저, 두께 10 nm 이하의 금속 혹은 반도체 박막을 표면이 임의 두께로 산화층(102)이 형성된 실리콘 기판(101) 위에 물리적 기상증착(PVD; physical vapor deposition) 혹은 화학적 기상증착(CVD; chemical vapor deposition) 방법에의해 증착한다. 이 때 증착 조건을 조절하여 5 nm 이하의 결정립들을 형성시키며, 이 5나노미터 이하 크기의 결정립들을 단일 전자 트랜지스터의 아일런드로 이용한다. 여기서, 화학적 기상증착(CVD)법은 금속 콜로이덜(colloidal) 에 의한 증착법 및 LB(Langmuir-Blodgett)법 까지 포함된다.First, a metal or semiconductor thin film having a thickness of 10 nm or less is deposited on a silicon substrate 101 on which an oxide layer 102 is formed to have an arbitrary thickness. It is deposited by the method. At this time, the deposition conditions are controlled to form grains of 5 nm or less, and the grains of 5 nanometers or less are used as islands of a single electron transistor. Here, the chemical vapor deposition (CVD) method includes a deposition method by a metal colloidal and a Langmuir-Blodgett (LB) method.

다음에, 소스(104)와 드레인(105) 및 게이트(gate)(미도시)를 SPM에 의한 증착법으로 증착시킨다. 이 경우 아일런드와 아일런드 사이는 약 5 nm 이하의 빈공간(hole)이 있다. 이 빈공간이 터널 장벽으로 작용하게 되며 유전 물질은 공기이므로 유전 상수가 1에 가까우므로 동일한 크기의 결정립을 가지는 경우에 있어서 거의 최소한의 캐패시턴스를 갖게된다.Next, the source 104, the drain 105, and a gate (not shown) are deposited by the deposition method by SPM. In this case, there is a hole of about 5 nm or less between the island and the island. This void acts as a tunnel barrier, and since the dielectric material is air, the dielectric constant is close to 1, so that when the grains have the same size, they have almost the minimum capacitance.

이와 같이 제작된 단일 전자 트랜지스터의 동작원리는 다음과 같다.The operation principle of the single electron transistor manufactured as described above is as follows.

소스와 드레인 사이에 전압을 가하면 임의의 전압에 이르러서야 전류가 흐른다. 이 때의 임의의 전압을 쿨롱 차폐 전압(Coulomb blockade voltage)이라 부르며 전류가 흐르지 않는 것은 전자 하나가 소스에서 아일런드로 터널링됨에 따라 아일런드에 충전이일어나 더 이상의 전자를 받아 들일 수 없기 때문이다. 만약 이 충전 에너지 보다 큰 에너지를 게이트를 이용하여 공급하면 쿨롱 차폐는 일어나지 않게 되어 임의의 전류가 흐른다. 그러므로 소스와 드레인 사이의 전압을 쿠울롬 부록케이드 갭 전압 이하로 고정시키고 게이트 전압을 조절하면 기존의 3단자 트랜지스터 와 유사하게 스위칭 시킬 수 있다.When a voltage is applied between the source and the drain, current flows only when a certain voltage is reached. The random voltage at this time is called the Coulomb blockade voltage and no current flows because one electron is tunneled from the source to the island, causing the island to charge and not accept any more electrons. If more than this charging energy is supplied through the gate, the Coulomb shielding does not occur, and a random current flows. Therefore, if the voltage between the source and drain is fixed below the Kuloum appendice gap voltage and the gate voltage is adjusted, it can be switched similarly to the conventional three-terminal transistor.

이상 설명한 바와 같이, 본 발명에 따른 단일 전자 트랜지스터는 그 상부가 산화된 실리콘 기판 상에 5nm 이하여 금속 혹은 반도체 결정립을 증착하고, 그 위에 소스 및 드레인을 형성함으로써, 종래의 단일 전자 트랜지스터들 보다 제작이 용이하고 또한 증착에 의해 자연적으로 생긴 빈공간을 터널 장벽으로 이용하기 때문에 제작 후 공기중에 노출시켜도 터널 장벽의 열화가 전혀 없으므로 오랫동안 상온에서 작동시켜도 재현성 및 트랜지스터의 열화 문제가 전혀 발생하지 않는다. 따라서 본 발명에 따른 단일 전자 트랜지스터는 1 Tb 급 메모리 및 로직 소자에 응용이 가능한 장점이 있다.As described above, the single-electron transistor according to the present invention is fabricated more than conventional single-electron transistors by depositing metal or semiconductor grains of 5 nm or less on an oxidized silicon substrate and forming a source and a drain thereon. Since the hollow space naturally generated by vapor deposition is used as a tunnel barrier, there is no degradation of the tunnel barrier even when exposed to air after fabrication, so there is no problem of reproducibility and transistor degradation even when operated at room temperature for a long time. Therefore, the single electronic transistor according to the present invention has an advantage that can be applied to 1 Tb-class memory and logic devices.

Claims (13)

그 상부가 산화된 반도체 기판;A semiconductor substrate whose upper portion is oxidized; 상기 기판의 산화면 상에 증착된 5nm 이하의 금속 결정립들로 형성된 아일런드층; 및An island layer formed of metal grains of 5 nm or less deposited on an oxide surface of the substrate; And 상기 아일런드층 상에 일정한 간격을 두고 형성된 소스 및 드레인을 포함하되,It includes a source and a drain formed on the island layer at regular intervals, 상기 아일런드층에서의 아일런드 터널 장벽은 결정립과 결정립 사이의 빈 공간으로 형성된 것을 특징으로 하는 단일 전자 트랜지스터.The island tunnel tunnel in the island layer is formed of a single electron transistor, characterized in that the empty space between the crystal grains. 제2항에 있어서,The method of claim 2, 상기 빈공간은 폭이 5nm 이하인 것을 특징으로 하는 단일 전자 트랜지스터.The empty space is a single electronic transistor, characterized in that less than 5nm in width. 제1항에 있어서,The method of claim 1, 상기 소스 및 드레인은 상기 아일런드층을 형성시킨 후 SPM 을 이용하여 형성한 것을 특징으로 하는 단일 전자 트랜지스터.The source and drain are formed using the SPM after forming the island layer. 제1항에 있어서,The method of claim 1, 상기 아일런드층은 두께가 10 nm 이하인 것을 특징으로 하는 단일 전자 트랜지스터.The island layer has a thickness of less than 10 nm single electron transistor. 제1항에 있어서,The method of claim 1, 상기 아일런드층은 두께가 10nm 이하이고, 5nm 이하의 반도체 결정립으로 형성된 것을 특징으로 하는 단일 전자 트랜지스터.The island layer has a thickness of 10nm or less, single electron transistor, characterized in that formed of semiconductor grains of 5nm or less. (가) 표면이 소정의 두께로 산화된 반도체 기판 상에 금속을 증착하여 5nm 이하의 결정립들을 갖으며 상기 결정립들 사이에 빈 공간이 형성된 두께 10 nm 이하의 아일런드층을 형성하는 단계; 및(A) depositing a metal on a semiconductor substrate whose surface is oxidized to a predetermined thickness to form an island layer having a thickness of 10 nm or less having crystal grains of 5 nm or less and having an empty space therebetween; And (나) 상기 아일런드층 상에 서로 일정한 간격을 갖는 소스 및 드레인을 형성하는 단계;를(B) forming a source and a drain having a predetermined distance from each other on the island layer; 포함하는 것을 특징으로 하는 단일 전자 트랜지스터의 제조 방법.A method of manufacturing a single electronic transistor, characterized in that it comprises a. 제6항에 있어서,The method of claim 6, 상기 (가) 단계는 물리적 증착법 혹은 화학 기상 증착법에 의해 이루어지는 것을 특징으로 하는 단일 전자 트랜지스터의 제조 방법.The step (a) is a method of manufacturing a single electronic transistor, characterized in that by physical vapor deposition or chemical vapor deposition. 제7항에 있어서,The method of claim 7, wherein 상기 화학 기상 증착법은 금속 콜로이덜 증착법 혹은 Langmuir-Blodgett법을 포함하는 것을 특징으로 하는 단일 전자 트랜지스터의 제조 방법.The chemical vapor deposition method includes a metal colloidal deposition method or a Langmuir-Blodgett method. 제6항에 있어서,The method of claim 6, 상기 (나) 단계는 SPM법에 의해 이루어지는 것을 특징으로 하는 단일 전자 트랜지스터의 제조 방법.The step (b) is performed by the SPM method. (가) 표면이 소정의 두께로 산화된 반도체 기판 상에 반도체를 증착하여 5nm 이하의 결정립을 갖는 두께 10 nm 이하의 아일런드층을 형성하는 단계; 및(A) depositing a semiconductor on a semiconductor substrate whose surface is oxidized to a predetermined thickness to form an island layer having a thickness of 10 nm or less having grains of 5 nm or less; And (나) 상기 아일런드층 상에 서로 일정한 간격을 갖는 소스 및 드레인을 형성하는 단계;를(B) forming a source and a drain having a predetermined distance from each other on the island layer; 포함하는 것을 특징으로 하는 단일 전자 트랜지스터의 제조 방법.A method of manufacturing a single electronic transistor, characterized in that it comprises a. 제10항에 있어서,The method of claim 10, 상기 (가) 단계는 물리적 증착법 혹은 화학 기상 증착법에 의해 이루어지는 것을 특징으로 하는 단일 전자 트랜지스터의 제조 방법.The step (a) is a method of manufacturing a single electronic transistor, characterized in that by physical vapor deposition or chemical vapor deposition. 제11항에 있어서,The method of claim 11, 상기 화학 기상 증착법은 금속 콜로이덜 증착법 혹은 Langmuir-Blodgett법을 포함하는 것을 특징으로 하는 단일 전자 트랜지스터의 제조 방법.The chemical vapor deposition method includes a metal colloidal deposition method or a Langmuir-Blodgett method. 제10항에 있어서,The method of claim 10, 상기 (나) 단계는 SPM법에 의해 이루어지는 것을 특징으로 하는 단일 전자 트랜지스터의 제조 방법.The step (b) is performed by the SPM method.
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