KR100415542B1 - Forming method of contact for semiconductor - Google Patents
Forming method of contact for semiconductor Download PDFInfo
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- KR100415542B1 KR100415542B1 KR10-2001-0037508A KR20010037508A KR100415542B1 KR 100415542 B1 KR100415542 B1 KR 100415542B1 KR 20010037508 A KR20010037508 A KR 20010037508A KR 100415542 B1 KR100415542 B1 KR 100415542B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
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Abstract
본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 반도체 소자의 콘택 형성 방법에 관한 것이다. 본 발명은 자체 평탄성이 우수한 SOG 계열을 절연막으로 사용하면서, 콘택 형성후 N2또는 NH3플라즈마 처리를 통해 노출된 표면을 질화시킨 후 콘택 저면의 질화막을 제거 및 열처리를 통해 금속 콘택시 공극 및 잔류물의 형성에 의한 콘택 저항 및 누설전류의 증가를 방지하기 위한 콘택 형성 방법을 제공하기 위한 것으로, 이를 위해 본 발명은, 소정 공정이 완료된 기판 상에 제1전도층을 형성하는 단계; 상기 제1전도층 상에 SOG(Spin On Glass) 계열의 절연막을 형성하는 단계; 상기 절연막을 선택적으로 식각하여 상기 제1전도층 표면을 노출시키는 콘택홀을 형성하는 단계; 플라즈마 처리를 실시하여 노출된 상기 제1전도층 표면 및 전체 구조 표면을 따라 질화막을 형성하는 단계; 상기 콘택홀 저면의 상기 질화막을 제거하는 단계; 상기 질화막이 제거된 전체 구조 표면을 따라 제1배리어막을 형성하는 단계; 상기 제1배리어막 표면을 질화시켜 제2배리어막을 형성하는 단계; 및 상기 제2배리어막 상에 제2전도층을 형성하는 단계를 포함하여 이루어지는 반도체 소자의 콘택 형성 방법을 제공한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact of a semiconductor device. According to the present invention, the SOG series having excellent self-flatness is used as an insulating film. After contact formation, the exposed surface is nitrided through N 2 or NH 3 plasma treatment, the nitride film on the bottom of the contact is removed, and the voids and residues during metal contact are removed through heat treatment. The present invention provides a method for forming a contact for preventing an increase in contact resistance and leakage current due to water formation. Forming a spin on glass (SOG) -based insulating film on the first conductive layer; Selectively etching the insulating layer to form a contact hole exposing a surface of the first conductive layer; Performing a plasma treatment to form a nitride film along the exposed first conductive layer surface and the entire structure surface; Removing the nitride film on the bottom of the contact hole; Forming a first barrier film along the entire structure surface from which the nitride film is removed; Nitriding a surface of the first barrier film to form a second barrier film; And forming a second conductive layer on the second barrier film.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로 특히, 반도체 소자의 콘택 형성 방법에 관한 것으로, 더욱 상세하게는 플라즈마 처리에 의한 반도체 소자의 콘택 안정화 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact of a semiconductor device, and more particularly, to a method for stabilizing a contact of a semiconductor device by plasma treatment.
반도체 소자 제조시 소자간의 분리 또는 층간 절연 등의 목적으로 절연막을 사용하고 있는 바, 절연막은 반도체 소자에 있어서, 필수 불가결한 요소라 할 수 있다.In the manufacture of semiconductor devices, insulating films are used for the purpose of separation or interlayer insulation between the devices, and the insulating films are indispensable for semiconductor devices.
한편, 반도체 소자의 고집적화에 따라 이러한 절연막의 저유전 특성, 막 평탄성 및 갭-필 특성 등의 요건이 더욱 까다로와 지고 있는 실정이다.On the other hand, with the higher integration of semiconductor devices, the requirements such as low dielectric properties, film flatness, and gap-fill characteristics of these insulating films are becoming more demanding.
도 1a 및 도 1b는 통상적인 절연막 형성 공정을 도시한 단면도로서, 이를 참조하여 절연막 형성 공정을 살펴 본다.1A and 1B are cross-sectional views illustrating a conventional insulating film forming process, which will be described with reference to the insulating film forming process.
먼저, 도 1a에 도시된 바와 같이 기판(10) 상에 전도층(11)을 형성한 다음, HDP 계열의 절연막(12)을 형성한 다음, 산화막 계열의 절연막(13)을 형성한다. 절연막(13)은 막 균일도를 향상시키기 위해 별도로 실시하는 화학 기계적 연마(Chemical Mechanical Polishing; 이하 CMP라 함)을 위한 연마 타겟으로 사용된다.First, as illustrated in FIG. 1A, the conductive layer 11 is formed on the substrate 10, and then an HDP-based insulating film 12 is formed, and then an oxide-based insulating film 13 is formed. The insulating film 13 is used as a polishing target for chemical mechanical polishing (hereinafter referred to as CMP) which is performed separately to improve film uniformity.
여기서, 전도층은, 소스/드레인 접합, 플러그 또는 금속배선 등을 모두 포함한다.Here, the conductive layer includes all of the source / drain junction, the plug or the metal wiring.
도 1b에 도시된 바와 같이, CMP 공정을 실시하여 절연막(13) 전체와 절연막(12) 일부를 제거하여 상부가 평탄한 절연막(12)을 형성한다.As shown in FIG. 1B, a CMP process is performed to remove the entire insulating film 13 and a part of the insulating film 12 to form an insulating film 12 having a flat top surface.
따라서, 후속 공정 예컨대, 감광막 패턴 형성 등의 공정 진행을 위한 절연막(12)의 평탄화는 이룰 수 있으나, CMP 공정은 비용이 많이 드는 단점이 있으며, CMP 공정의 특성 상 하지막의 긁힘 등의 문제점을 내포하게 된다.Accordingly, the planarization of the insulating film 12 for the subsequent process such as the formation of the photoresist pattern may be achieved, but the CMP process may be costly, and the characteristics of the CMP process may include scratches of the underlying film. Done.
또한, 현재 반도체 양산 공정에서 절연막으로 사용하고 있는 BPSG(Boro Phospho Silicate Glass)막은 갭-필(Gap-fill)을 위하여 750℃ 이상의 후속 열공정을 필요로 하며, HDP(High Density Plasma) 산화막 또는 USG(Undoped Silicate Glass)막 등은 하부의 타폴로지(Topology)에 따라 갭-필 특성이 좌우되기 때문에 차세대 0.1㎛ 이하의 소자에 적용하기에는 어려운 실정이다.In addition, the BPSG (Boro Phospho Silicate Glass) film, which is currently used as an insulating film in the semiconductor mass production process, requires a subsequent thermal process of 750 ° C. or higher for gap-fill, and a high density plasma (HDP) oxide film or USG. (Undoped Silicate Glass) film is difficult to apply to next-generation 0.1㎛ or less devices because the gap-fill characteristics depend on the topology of the lower (Topology).
한편, 상기한 바와 같은 문제점을 해결하기 위해 자체 평탄화가 가능한 물질로 SOG(Spin On Glass) 계열의 물질을 절연막으로 사용하게 되었는 바, 도 2a 및 도 2b는 이러한 SOG 계열의 물질을 절연막으로 이용한 종래의 콘택 형성 공정을 도시한 단면도이다.Meanwhile, in order to solve the problems described above, a material that is capable of self-planarization has been used as an insulating film based on a SOG (Spin On Glass) -based material. It is sectional drawing which shows the contact formation process.
먼저, 도 2a에 도시된 바와 같이 기판(20) 상에 전도층(21)을 형성한 다음, 후속 SOG 계열의 절연막을 보호하기 위한 하부 산화막(22)과 SOG 계열의 절연막(23) 및 SOG 계열의 절연막(23)을 보호하기 위한 상부 산화막(24)을 차례로 형성한다.First, as shown in FIG. 2A, the conductive layer 21 is formed on the substrate 20. Then, the lower oxide film 22 and the SOG-based insulating film 23 and SOG-based for protecting the subsequent SOG-based insulating film are formed. The upper oxide film 24 for protecting the insulating film 23 is formed in this order.
다음으로 도 2b에 도시된 바와 같이, 감광막 패턴(도시하지 않음)을 형성 한 후, 상부 산화막(24), 절연막(23) 및 하부 산화막(22)을 선택적으로 식각하여 전도층 표면을 노출시키는 콘택홀(도시하지 않음)을 형성한 다음, 상기 노출된 전도층(21)에 콘택되는 예컨대, 금속배선(25)을 형성한다.Next, as shown in FIG. 2B, after forming a photoresist pattern (not shown), a contact for selectively etching the upper oxide layer 24, the insulating layer 23, and the lower oxide layer 22 to expose the conductive layer surface is exposed. A hole (not shown) is formed, and then, for example, a metal wiring 25 is formed to contact the exposed conductive layer 21.
한편, SOG 계열의 물질은 금속배선(25) 형성을 위한 공정시 고온 공정에 따른 막 자체의 특성상 아웃-개싱(Out-gassing)에 의한 소스로 인하여 금속배선의 형성이 방해되는 공극(Void, 26) 등이 발생하며, H2O성 레지듀(Residu, 27)가 남게 되어 누설전류 및 콘택 저항을 증가시키는 요인으로 작용하게 되는 바, 이러한 소스는 주로 공기 중 노출과 후속 공정의 증착시 SOG막에서의 H2O 또는 수소 이온에 의한 것으로 알려져 있다.On the other hand, SOG-based materials are voids that prevent the formation of metal wiring due to the source by out-gassing due to the characteristics of the film itself according to the high temperature process in the process for forming the metal wiring 25 (Void, 26) ), And H 2 O-resist (Residu, 27) is left to act as a factor to increase the leakage current and contact resistance, these sources are mainly SOG film during exposure to air and deposition of subsequent processes It is known to be due to H 2 O or hydrogen ions.
따라서, 이러한 SOG 계열의 절연막 형성에 따른 공극 및 H2O성 레지듀의 형성을 근본적으로 방지하기 위한 기술이 필요하게 된다.Therefore, there is a need for a technique for fundamentally preventing the formation of voids and H 2 O-based residues due to the formation of SOG-based insulating films.
상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 본 발명은, 자체 평탄성이 우수한 SOG 계열을 절연막으로 사용하면서, 콘택 형성후 N2또는 NH3플라즈마 처리를 통해 노출된 표면을 질화시킨 후 콘택 저면의 질화막을 제거 및 열처리를 통해 금속 콘택시 공극 및 잔류물의 형성에 의한 콘택 저항 및 누설전류의 증가를 방지하기 위한 콘택 형성 방법을 제공하는데 그 목적이 있다.The present invention proposed to solve the problems of the prior art as described above, using the SOG series having excellent self-flatness as the insulating film, after the contact is formed, the contact surface after nitriding the exposed surface through N 2 or NH 3 plasma treatment It is an object of the present invention to provide a method for forming a contact for preventing an increase in contact resistance and leakage current due to the formation of voids and residues during metal contact through removal and heat treatment of a nitride film.
도 1a 및 도 1b는 통상적인 절연막 형성 공정을 도시한 단면도,1A and 1B are cross-sectional views showing a conventional insulating film forming process;
도 2a 및 도 2b는 이러한 SOG 계열의 물질을 절연막으로 이용한 종래의 콘택 형성 공정을 도시한 단면도,2A and 2B are cross-sectional views illustrating a conventional contact forming process using such an SOG-based material as an insulating film;
도 3a 내지 도 3d는 본 발명의 일실시예에 따른 콘택 형성 공정을 도시한 단면도.3A to 3D are cross-sectional views illustrating a contact forming process according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
30 : 기판 31 : 제1전도층30 substrate 31 first conductive layer
32 : 하부 산화막 33 : 절연막32: lower oxide film 33: insulating film
34 : 상부 산화막 35 : 질화막34: upper oxide film 35: nitride film
36 : 제1배리어막 37 : 제2배리어막36: first barrier film 37: second barrier film
38 : 제2전도층38: second conductive layer
상기와 같은 문제점을 해결하기 위해 본 발명은, 소정 공정이 완료된 기판 상에 제1전도층을 형성하는 단계; 상기 제1전도층 상에 SOG(Spin On Glass) 계열의 절연막을 형성하는 단계; 상기 절연막을 선택적으로 식각하여 상기 제1전도층 표면을 노출시키는 콘택홀을 형성하는 단계; 플라즈마 처리를 실시하여 노출된 상기 제1전도층 표면 및 전체 구조 표면을 따라 질화막을 형성하는 단계; 상기 콘택홀 저면의 상기 질화막을 제거하는 단계; 상기 질화막이 제거된 전체 구조 표면을 따라 제1배리어막을 형성하는 단계; 상기 제1배리어막 표면을 질화시켜 제2배리어막을 형성하는 단계; 및 상기 제2배리어막 상에 제2전도층을 형성하는 단계를 포함하여 이루어지는 반도체 소자의 콘택 형성 방법을 제공한다.In order to solve the above problems, the present invention comprises the steps of forming a first conductive layer on a substrate is completed a predetermined process; Forming a spin on glass (SOG) -based insulating film on the first conductive layer; Selectively etching the insulating layer to form a contact hole exposing a surface of the first conductive layer; Performing a plasma treatment to form a nitride film along the exposed first conductive layer surface and the entire structure surface; Removing the nitride film on the bottom of the contact hole; Forming a first barrier film along the entire structure surface from which the nitride film is removed; Nitriding a surface of the first barrier film to form a second barrier film; And forming a second conductive layer on the second barrier film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 첨부한 도면을 참조하여 상세하게 설명한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can more easily implement the present invention.
도 3a 내지 도 3d는 본 발명의 일실시예에 따른 콘택 형성 공정을 도시한 단면도로서, 이하 이를 참조하여 상세하게 설명한다.3A to 3D are cross-sectional views illustrating a contact forming process according to an embodiment of the present invention, which will be described in detail with reference to the following.
먼저, 도 3a에 도시된 바와 같이 기판(30) 상에 전도층(31)을 형성한 다음, 후속 SOG 계열의 절연막을 보호하기 위한 하부 산화막(32)과 SOG 계열의 절연막(33) 및 SOG 계열의 절연막(33)을 보호하기 위한 상부 산화막(34)을 차례로 형성한다. 여기서, 전도층(31)은, 소스/드레인 접합, 플러그 또는 금속배선 등을 모두 포함하며, SOG 계열의 절연막(33)은 자체 평탄화 공정이 우수하여 CMP 공정을 생략할 수 있다.First, as shown in FIG. 3A, the conductive layer 31 is formed on the substrate 30, and then the lower oxide layer 32, the SOG-based insulating layer 33, and the SOG-based layer are used to protect the SOG-based insulating layer. The upper oxide film 34 for protecting the insulating film 33 is formed in turn. Here, the conductive layer 31 includes all of the source / drain junction, the plug or the metal wiring, and the SOG-based insulating layer 33 has excellent self-planarization process, and thus the CMP process may be omitted.
다음으로 도 3b에 도시된 바와 같이, 감광막 패턴(도시하지 않음)을 형성 한 후, 상부 산화막(34), 절연막(33) 및 하부 산화막(32)을 선택적으로 식각하여 전도층 표면을 노출시키는 콘택홀(도시하지 않음)을 형성한 다음, 플라즈마 처리를 통해 전체 구조의 표면을 따라 10Å 내지 30Å의 두께의 얇은 질화막(35)을 형성한다.질화막(35)은 SOG 계열의 절연막(33)에서 발생되는 수소 등의 아웃 개싱 소스가 N2또는 NH3가스에 의해 NH3화된 질화막(35)이 형성되는 원리를 이용한 것으로, 질화막(35)은 SOG 계열의 절연막(33)에서의 아웃 개싱을 차단하는 역할을 하게 된다.Next, as shown in FIG. 3B, after forming a photoresist pattern (not shown), a contact for selectively etching the upper oxide film 34, the insulating film 33, and the lower oxide film 32 to expose the conductive layer surface is exposed. After the hole (not shown) is formed, a thin nitride film 35 having a thickness of 10 to 30 Å is formed along the surface of the entire structure through plasma treatment. The nitride film 35 is generated in the SOG-based insulating film 33. to outgassing sources, such as hydrogen that using NH 3 qualified principles nitride film 35 is formed by the N 2 or NH 3 gas, the nitride layer 35 is to block the outgassing in the SOG-based insulating film 33 It will play a role.
이 때, N2또는 NH3를 적절히 혼합한 가스 분위기의 플라즈마를 이용하여 5초 내지 10초 동안 50W ∼ 3KW의 파워를 이용한다.At this time, using the plasma of the N 2 or an appropriate mixture of NH 3 gas atmosphere is used the power of 50W ~ 3KW for 5 seconds to 10 seconds.
이어서, 플라즈마 처리에 따른 잔여물을 제거하기 위해 HF 또는 완충 산화막 식각제(Buffered Oxide Etchant; 이하 BOE라 함)를 이용하여 세정 공정을 실시한다.Subsequently, a cleaning process is performed using HF or a buffered oxide etchant (hereinafter referred to as BOE) in order to remove residues generated by plasma treatment.
다음으로 도 3c에 도시된 바와 같이, 콘택홀 저면에 상기 질화막(35)이 남아 있을 경우 콘택 저항이 증가하기 때문에 콘택홀 저면 상의 질화막(35)을 제거한다.이는 He, Ne, Ar 또는 Xe 등의 비활성 가스를 적절히 사용한 스퍼터링을 통해 이루어지며, 이 때 100W ∼ 2KW의 기판 바이어스를 이용하여 2초 ∼ 5초 동안 실시한다.Next, as shown in FIG. 3C, when the nitride film 35 remains on the bottom of the contact hole, the contact resistance increases, so that the nitride film 35 on the bottom of the contact hole is removed. This is performed by He, Ne, Ar, or Xe. It is made through sputtering using an inert gas of appropriately, at this time using a substrate bias of 100W ~ 2KW for 2 seconds to 5 seconds.
이어서, 결과물 표면을 따라 Ti 등의 배리어막(36)을 형성하는 바,배리어막(36)의 형성은 질화막(35) 식각시 동시에 즉, 인-시튜의 공정으로 진행된다. 이 때, 100W ∼ 2KW의 기판 바이어스 및 1KW ∼ 3KW의 파워를 이용한다.Subsequently, a barrier film 36 such as Ti is formed along the surface of the resultant, and the formation of the barrier film 36 proceeds at the same time as the nitride film 35 is etched, that is, in-situ. At this time, a substrate bias of 100W to 2KW and a power of 1KW to 3KW are used.
다음으로 도 3d에 도시된 바와 같이, 배리어막(36) 표면을 질화시켜 배리어막(37) 예컨대, TiN을 형성시키는 바, 종래의 경우 Ti/TiN을 형성함으로써, 그 두께 증가에 따라 콘택 영역이 좁아지게 되어 후속 전도층 형성시 콘택홀 내부에서의 갭-필 문제가 발생하게 되며, 만일 Ti만을 단독으로 하는 경우 막의 폭발이 발생하는 문제가 발생하게 된다.Next, as shown in FIG. 3D, the surface of the barrier film 36 is nitrided to form the barrier film 37, for example, TiN. In the conventional case, by forming Ti / TiN, a contact region is formed as the thickness thereof increases. As a result, the gap-fill problem occurs when the conductive layer is subsequently formed, and if only Ti is used, a film explosion may occur.
따라서, 본 발명은 급속질화 열처리(Rapid Thermal Nitrization; 이하 RTN이라 함)를 통해 100Å ∼ 300Å의 두께의 얇은 TiN 등의 배리어막(37)을 형성함으로써, 넓은 콘택 사이즈를 확보할 수 있게되므로 콘택 저항을 감소시킬 수 있게 된다.Accordingly, the present invention forms a thin barrier film 37 such as thin TiN having a thickness of 100 kPa to 300 kPa through Rapid Thermal Nitrization (hereinafter referred to as RTN), thereby making it possible to secure a wide contact size. Can be reduced.
여기서 RTN은, 950℃ 내지 1000℃의 온도와 N2또는 NH3를 적절히 혼합한 가스 분위기에서 20초 내지 50초 동안 실시한다.The RTN is carried out at a temperature of 950 ℃ to 1000 ℃ and N 2 gas atmosphere or a mixture of NH 3 as appropriate for about 20 seconds to 50 seconds.
이어서, 전체 구조 상부에 전도층(38) 형성함으로써, 콘택 형성 공정이 완료되는 바, 전도층(38)은 W 또는 폴리실리콘 등을 이용한 금속배선, 비트라인 또는 스토리지노드 등을 포함할 수 있다.Subsequently, by forming the conductive layer 38 over the entire structure, the contact forming process is completed. The conductive layer 38 may include a metal wiring, a bit line, a storage node, or the like using W or polysilicon.
상기한 바와 같이 이루어지는 본 발명은, SOG 계열의 절연막을 선택적으로 식각하여 콘택홀 을 형성한 다음, 막 표면에 N2또는 NH3등의 플라즈마 처리를 통해 얇은 질화막을 형성하여 콘택 형성 후 SOG막에서 기인하는 아웃 개싱의 표면 확산을 막을 수 있도록 함과 동시에 Ti막 형성 후 RTN 처리에 의해 TiN막을 형성함으로써, 넓은 콘택 사이즈를 얻을 수 있도록 하여 콘택저항 및 누설전류를 감소시킬 수 있음을 실시예를 통해 알아 보았다.According to the present invention as described above, the SOG-based insulating film is selectively etched to form a contact hole, and then a thin nitride film is formed on the surface of the film by plasma treatment such as N 2 or NH 3 to form a contact. By preventing the surface diffusion caused by out-gassing and forming a TiN film by RTN treatment after forming the Ti film, a wide contact size can be obtained to reduce contact resistance and leakage current. I tried to find out.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
전술한 본 발명은, 콘택 저항 및 누설전류를 감소시켜 소자의 특성 열화를 방지함으로써, 궁극적으로 제품 수율 및 전기적 특성을 향상시킬 수 있는 탁월한 효과를 기대할 수 있다.The present invention described above, by reducing the contact resistance and leakage current to prevent the deterioration of the characteristics of the device, it can be expected that the excellent effect that can ultimately improve the product yield and electrical properties.
Claims (14)
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05114656A (en) * | 1991-10-21 | 1993-05-07 | Matsushita Electron Corp | Manufacture of semiconductor device |
| KR100220935B1 (en) * | 1995-12-15 | 1999-09-15 | 김영환 | Process for forming metal contact |
| KR20000065373A (en) * | 1999-04-02 | 2000-11-15 | 김영환 | Diffusion barrier in semiconductor device and fabrication method thereof |
| KR20010038050A (en) * | 1999-10-21 | 2001-05-15 | 윤종용 | Method for forming a contact hole with plasma treatment in semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05114656A (en) * | 1991-10-21 | 1993-05-07 | Matsushita Electron Corp | Manufacture of semiconductor device |
| KR100220935B1 (en) * | 1995-12-15 | 1999-09-15 | 김영환 | Process for forming metal contact |
| KR20000065373A (en) * | 1999-04-02 | 2000-11-15 | 김영환 | Diffusion barrier in semiconductor device and fabrication method thereof |
| KR20010038050A (en) * | 1999-10-21 | 2001-05-15 | 윤종용 | Method for forming a contact hole with plasma treatment in semiconductor device |
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