KR100404171B1 - Method for forming pattern on silicon surface having nea characteristic - Google Patents

Method for forming pattern on silicon surface having nea characteristic Download PDF

Info

Publication number
KR100404171B1
KR100404171B1 KR1019960073530A KR19960073530A KR100404171B1 KR 100404171 B1 KR100404171 B1 KR 100404171B1 KR 1019960073530 A KR1019960073530 A KR 1019960073530A KR 19960073530 A KR19960073530 A KR 19960073530A KR 100404171 B1 KR100404171 B1 KR 100404171B1
Authority
KR
South Korea
Prior art keywords
silicon substrate
nea
silicon
pattern
oxide film
Prior art date
Application number
KR1019960073530A
Other languages
Korean (ko)
Other versions
KR19980054382A (en
Inventor
전동렬
고태영
이인숙
Original Assignee
엘지전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘지전자 주식회사 filed Critical 엘지전자 주식회사
Priority to KR1019960073530A priority Critical patent/KR100404171B1/en
Publication of KR19980054382A publication Critical patent/KR19980054382A/en
Application granted granted Critical
Publication of KR100404171B1 publication Critical patent/KR100404171B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane

Abstract

PURPOSE: A method for forming a pattern on a silicon surface having NEA(Negative Electron Affinity) characteristic is provided to be capable of easily carrying out the manufacturing process and reducing fabrication cost. CONSTITUTION: An oxide layer is formed on a silicon substrate(1). A patterning process is performed on the oxide layer for partially exposing the silicon substrate. A predetermined pattern is formed by removing the exposed silicon substrate to a predetermined depth using the oxide layer as an etching mask. A metal thin film is formed on the entire surface of the resultant structure. The metal thin film is selectively patterned. Then, a protection layer is formed on the silicon substrate. The protection layer is removed by heating the entire surface of the resultant structure. Alkali metal grains are formed on the surface of the resultant structure. Then, oxygen is implanted in the resultant structure.

Description

엔이에이(NEA) 성질을 갖는 실리콘 표면의 패턴 형성방법Pattern formation method of silicon surface having NEA properties

본 발명은 NEA(Negative Electron Affinity) 성질을 갖는 물질 표면의 패턴 형성방법에 관한 것으로, 특히 NEA 성질을 갖는 실리콘 표면의 패턴 형성방법에 관한 것이다.The present invention relates to a method of forming a pattern on the surface of a material having NEA (Negative Electron Affinity) properties, and more particularly to a method of forming a pattern on a silicon surface having NEA properties.

일반적으로, 단결정 실리콘이나 GaAs 화합물 반도체의 표면에 알칼리 금속과 소량의 산소를 흡착하면 진공의 에너지 준위가 반도체의 전도대 에너지 준위보다 낮은 곳에 위치하는 NEA 현상이 발생한다.In general, when an alkali metal and a small amount of oxygen are adsorbed onto the surface of a single crystal silicon or GaAs compound semiconductor, the NEA phenomenon occurs where the energy level of the vacuum is lower than the energy level of the conduction band of the semiconductor.

NEA 표면에서는 빛 주사나 가열에 의해 가전자대(valence band)에서 전도대(conduction band)로 여기된 전자가 쉽게 진공으로 방출된다.On the surface of the NEA, electrons excited from the valence band to the conduction band by light scanning or heating are easily released into the vacuum.

패턴이 없는 NEA 표면에 빛을 쪼이면 NEA 표면 전체에서 전자가 나오지만, NEA 성질을 가진 표면에 패턴을 만들어 원하는 곳에만 NEA 성질을 갖게 하면 빛을 쪼였을 때, 표면의 특정한 곳에서만 전자가 방출된다.When light is irradiated on an NEA surface without a pattern, electrons are emitted from the entire surface of the NEA. However, when a pattern is formed on a surface having NEA properties and the NEA property is only where desired, light is emitted only at a specific place on the surface.

따라서, 패턴이 형성된 NEA 표면을 리소그라피용 전자총이나 영상표시장치 등의 전자원으로 이용할 수 있다.Therefore, the patterned NEA surface can be used as an electron source such as an electron gun for lithography or an image display device.

종래에는 패턴된 GaAs 화합물 반도체의 표면에 시지움(cesium)과 같은 알칼리 금속과 산소를 코팅하여 NEA 성질을 갖게 함으로써, 패턴의 모양대로 전자를 방출하게 하는 방법을 사용하였다.Conventionally, an alkali metal such as cesium and oxygen are coated on a surface of a patterned GaAs compound semiconductor to have NEA properties, thereby emitting electrons in the shape of a pattern.

그러나, GaAs 화합물 반도체가 고가일 뿐만 아니라, 제조 공정도 어려워 값이 싼 단결정 실리콘을 이용하여 패턴된 NEA 표면을 만드는 기술이 필요하게 되었다.However, not only the GaAs compound semiconductor is expensive, but also the manufacturing process is difficult, so that a technique for making a patterned NEA surface using inexpensive single crystal silicon is required.

종래 기술에 따른 NEA 성질을 갖는 표면의 패턴 형성방법에 있어서는 다음과 같은 문제점이 있었다.The method of forming a pattern of a surface having NEA properties according to the prior art has the following problems.

패턴된 GaAs 화합물 반도체의 표면에 NEA 성질을 갖게 함으로써, 재료비가 상승되고 제조 공정이 복잡하다.By having NEA properties on the surface of the patterned GaAs compound semiconductor, the material cost is increased and the manufacturing process is complicated.

본 발명은 이와 같은 문제점을 해결하기 위한 것으로, NEA 성질을 갖는 실리콘 표면에 패턴을 형성하여 재료비가 저렴하고 공정처리가 용이한 NEA 성질을 갖는 실리콘 표면의 패턴 형성 방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method of forming a pattern on a silicon surface having a NEA property which is inexpensive in material cost and easy to process by forming a pattern on the silicon surface having a NEA property.

도 1a 내지 1f는 본 발명에 따른 NEA 성질을 갖는 실리콘 표면의 패턴 형성공정을 보여주는 공정단면도1A to 1F are cross-sectional views showing a pattern forming process of a silicon surface having NEA properties according to the present invention.

도 2은 본 발명에 따른 패턴이 있는 실리콘 NEA 소자를 형광판과 결합하여 영상 표시에 응용한 장치의 개략도2 is a schematic diagram of a device in which a patterned silicon NEA device according to the present invention is applied to an image display in combination with a fluorescent plate;

도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings

1 : 실리콘 기판 2 : 산화막1: silicon substrate 2: oxide film

3 : 몰리브데늄 박막 4 : 보호용 산화막3: molybdenum thin film 4: protective oxide film

5 : 실리콘 (100) 단결정면5: silicon 100 single crystal surface

본 발명에 따른 N2A 성질을 갖는 실리콘 표면의 패턴 형성 방법은 실리콘 기판상에 산화막을 형성하고 패터닝하여 실리콘 기판의 일정영역을 노출시키고, 패터닝된 산화막을 마스크로 노출된 실리콘 기판을 일정깊이로 제거하여 일정 모양의 패턴을 형성한 후, 산화막 희생층 및 실리콘 기판상에 몰리브데늄 박막을 증착하고, 산화막을 리프트오프하여 산화막상의 몰리브데늄 박막을 제거하고 노출된 실리콘 기판표면을 화학처리하여 얇은 산화막을 형성하고, 실리콘 기판 전면을 진공조안에서 가열하여 산화막을 제거한 다음, 실리콘 기판의 패턴 표면상에 알칼리 금속을 증착하고 소량의 산소를 주입하는데 그 특징이 있다.According to the present invention, a method of forming a pattern of silicon surface having N2A properties is performed by forming and patterning an oxide film on a silicon substrate to expose a predetermined region of the silicon substrate, and removing the patterned oxide film with a mask to a predetermined depth. After forming a predetermined pattern, a molybdenum thin film is deposited on the oxide sacrificial layer and the silicon substrate, the oxide film is lifted off to remove the molybdenum thin film on the oxide film, and the exposed silicon substrate surface is chemically treated to form a thin oxide film. Is formed, the entire surface of the silicon substrate is heated in a vacuum bath to remove the oxide film, and then an alkali metal is deposited and a small amount of oxygen is injected onto the pattern surface of the silicon substrate.

상기와 같은 특징을 갖는 본 발명에 따른 NEA 성질을 갖는 실리콘 표면의 패턴 형성 방법을 첨부된 도면을 참조하여 설명하면 다음과 같다.Referring to the accompanying drawings, a method for forming a pattern of a silicon surface having NEA properties according to the present invention having the above characteristics will be described below.

도 1a 내지 1f는 본 발명에 따른 NEA 성질을 갖는 실리콘 표면의 패턴 형성공정을 보여주는 공정단면도로서, 도 1a에 도시된 바와 같이, 결정 방향이 (100)이고 비저항이 0.1Ωcm 미만이 되도록 헤비(heavy) 도핑된 p형 실리콘 기판(1)상에 산화막(2)을 산화로에서 성장시키고, 산화막(2)을 패터닝하여 일정영역의 실리콘 기판(1)을 노출시킨다.1A to 1F are process cross-sectional views showing a pattern forming process of a silicon surface having NEA properties according to the present invention. As shown in FIG. 1A, a heavy crystal has a crystal direction of (100) and a specific resistance of less than 0.1? Cm. The oxide film 2 is grown on the doped p-type silicon substrate 1 in an oxidation furnace, and the oxide film 2 is patterned to expose the silicon substrate 1 in a predetermined region.

이어, 도 1b에 도시된 바와 같이, 패터닝된 산화막(2)을 마스크로 노출된 실리콘 기판(1)을 일정깊이로 제거하여 패턴을 형성한다.Subsequently, as shown in FIG. 1B, the patterned oxide film 2 is removed to form a pattern by removing the silicon substrate 1 exposed by a mask to a predetermined depth.

그리고, 도 1c에 도시된 바와 같이, 산화막(2) 및 실리콘 기판(1)상에 산에 강한 금속인 몰리브데늄 박막(3)을 스퍼터링 또는 전자빔 증착법으로 형성한다.As shown in FIG. 1C, the molybdenum thin film 3, which is an acid resistant metal, is formed on the oxide film 2 and the silicon substrate 1 by sputtering or electron beam deposition.

이어, 도 1d에 도시된 바와 같이, 리프트 오프(lift-off) 공정으로 산화막(2) 및 산화막(2)상의 몰리브데늄 박막(3)을 제거하고, 노출된 실리콘 기판(1) 표면을 질산, 암모니아, 염산, 불산 등으로 습식 식각하여 두꺼운 자연 산화막을 선택적으로 제거한 후, 노출된 실리콘 기판(1) 표면상에는 원자층 몇 개 정도의 얇은 보호용 산화막(4)을 남긴다.Subsequently, as shown in FIG. 1D, the oxide film 2 and the molybdenum thin film 3 on the oxide film 2 are removed by a lift-off process, and the exposed silicon substrate 1 surface is nitric acid. After wet etching with, ammonia, hydrochloric acid, hydrofluoric acid and the like to selectively remove the thick natural oxide film, a thin protective oxide film 4 of several atomic layers is left on the exposed silicon substrate 1 surface.

이때, 몰리브데늄 박막(3)은 습식식각시 사용되는 용액들에 잘 녹지 않으므로 실리콘 기판 표면의 패턴이 유지된다.At this time, since the molybdenum thin film 3 is not soluble in the solutions used during wet etching, the pattern of the surface of the silicon substrate is maintained.

그리고, 도 1e에 도시된 바와 같이, 실리콘 기판(1)을 진공 챔버에 넣고 800℃로 가열하면 얇은 보호용 산화막(4)이 증발하여 패턴이 새겨진 실리콘(100)단결정면(5)이 만들어 지고, 도 1f에 도시된 바와 같이, 실리콘 기판(1)의 패턴 표면상에 포타시움, 시지움, 소디움 등의 알칼리 금속을 증착하고 0.5 Langmuir의 산소를 주입하여 패턴된 실리콘 NEA 표면을 완성한다.As shown in FIG. 1E, when the silicon substrate 1 is placed in a vacuum chamber and heated to 800 ° C., the thin protective oxide film 4 is evaporated to form the silicon 100 single crystal surface 5 having the pattern engraved thereon. As shown in FIG. 1F, an alkali metal such as potassium, sisium, sodium, etc. is deposited on the patterned surface of the silicon substrate 1, and 0.5 Langmuir of oxygen is injected to complete the patterned silicon NEA surface.

이때, 상온에서 실리콘 단결정 면의 알칼리 금속 포화 증착량은 1 원자층(약 1015원자/㎠)미만 이므로 알칼리 금속을 충분히 증착하여 실리콘 표면에 포화되게 한다.At this time, since the alkali metal saturation deposition amount of the silicon single crystal surface at room temperature is less than one atomic layer (about 10 15 atoms / cm 2), the alkali metal is sufficiently deposited to saturate the silicon surface.

또한, 몰리브데늄 박막위에서는 알칼리 금속이 증착되더라도 일함수가 충분히 내려가지 않으므로 NEA 현상은 생기지 않는다.In addition, even if alkali metal is deposited on the molybdenum thin film, the work function does not sufficiently decrease, so that the NEA phenomenon does not occur.

도 2은 본 발명에 따른 패턴이 있는 실리콘 NEA 소자를 형광판과 결합하여 영상 표시에 응용한 장치의 개략도이다.2 is a schematic diagram of a device in which a patterned silicon NEA device according to the present invention is combined with a fluorescent plate and applied to an image display.

도 2에 도시된 바와 같이, 패턴이 만들어진 실리콘 NEA 표면에 빛을 주사하면 NEA 현상이 생긴 패턴의 표면에서만 전자가 방출된다.As shown in FIG. 2, when light is injected onto the silicon NEA surface on which the pattern is formed, electrons are emitted only from the surface of the pattern on which the NEA phenomenon occurs.

방출된 전자를 형광판에 부딪치게 하면 패턴대로 영상을 만들 수 있으므로 패턴이 된 실리콘 NEA 표면을 화면 표시 장치에 이용할 수 있다.When the emitted electrons strike the fluorescent plate, the image can be made in a pattern, and thus the patterned silicon NEA surface can be used for the display device.

본 발명에 따른 NEA 성질을 갖는 실리콘 표면의 패턴 형성 방법에 있어서는 다음과 같은 효과가 있다.In the method for forming a pattern of a silicon surface having NEA properties according to the present invention, the following effects are obtained.

첫째, 값이 싼 실리콘 기판을 사용하므로 화합물 반도체 기판에 비해 전체적인 공정가가 낮아지고 제조 공정이 수월하다.First, the use of inexpensive silicon substrates lowers the overall process cost and facilitates the manufacturing process compared to compound semiconductor substrates.

둘째, 패턴된 NEA 실리콘 소자를 전자원으로 이용하여 영상 표시 장치와 같이 여러 분야에 응용될 수 있어 산업상 이용 분야가 넓다.Second, since the patterned NEA silicon device is used as an electron source, it can be applied to various fields such as an image display device, and thus the industrial use field is wide.

Claims (5)

실리콘 기판상에 산화막을 형성하고 패터닝하여 상기 실리콘 기판의 일정영역을 노출시키는 스텝;Forming and patterning an oxide film on a silicon substrate to expose a predetermined region of the silicon substrate; 상기 패터닝된 산화막을 마스크로 노출된 실리콘 기판을 일정깊이로 제거하여 일정 모양의 패턴을 형성하는 스텝;Removing the patterned oxide film using a mask to expose a silicon substrate to a predetermined depth to form a pattern having a predetermined shape; 상기 산화막 및 실리콘 기판상에 금속 박막을 형성하는 스텝;Forming a metal thin film on the oxide film and the silicon substrate; 상기 산화막 및 산화막상의 금속 박막을 제거하고 상기 금속 박막을 마스크로 실리콘 기판 표면상에 얇은 보호막을 형성하는 스텝;Removing the oxide film and the metal thin film on the oxide film and forming a thin protective film on the surface of the silicon substrate using the metal thin film as a mask; 상기 실리콘 기판 전면을 가열하여 상기 보호막을 제거하는 스텝; 그리고Heating the entire surface of the silicon substrate to remove the protective film; And 상기 실리콘 기판의 패턴 표면상에 알칼리 금속을 형성하고 소량의 산소를 주입하는 스텝으로 이루어짐을 특징으로 하는 NEA 성질을 갖는 실리콘 표면의 패턴 형성 방법.And forming an alkali metal on the pattern surface of the silicon substrate and injecting a small amount of oxygen into the silicon surface. 제 1 항에 있어서, 상기 금속 박막은 산에 강한 금속임을 특징으로 하는 NEA 성질을 갖는 실리콘 표면의 패턴 형성 방법.The method of claim 1, wherein the metal thin film is an acid resistant metal. 제 2 항에 있어서, 상기 산에 강한 금속은 몰리브데늄임을 특징으로 하는 NEA 성질을 갖는 실리콘 표면의 패턴 형성 방법.The method of claim 2, wherein the acid resistant metal is molybdenum. 제 1 항에 있어서, 상기 보호막은 산화막임을 특징으로 하는 NEA 성질을 갖는 실리콘 표면의 패턴 형성 방법.The method of claim 1, wherein the protective layer is an oxide layer. 제 1 항에 있어서, 상기 실리콘 기판 가열시, 온도는 700∼900℃임을 특징으로 하는 NEA 성질을 갖는 실리콘 표면의 패턴 형성 방법.The method of claim 1, wherein the silicon substrate is heated at a temperature of 700 ° C. to 900 ° C. 3.
KR1019960073530A 1996-12-27 1996-12-27 Method for forming pattern on silicon surface having nea characteristic KR100404171B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960073530A KR100404171B1 (en) 1996-12-27 1996-12-27 Method for forming pattern on silicon surface having nea characteristic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960073530A KR100404171B1 (en) 1996-12-27 1996-12-27 Method for forming pattern on silicon surface having nea characteristic

Publications (2)

Publication Number Publication Date
KR19980054382A KR19980054382A (en) 1998-09-25
KR100404171B1 true KR100404171B1 (en) 2004-03-18

Family

ID=37422588

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960073530A KR100404171B1 (en) 1996-12-27 1996-12-27 Method for forming pattern on silicon surface having nea characteristic

Country Status (1)

Country Link
KR (1) KR100404171B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101377170B1 (en) * 2013-02-13 2014-03-27 포항공과대학교 산학협력단 Method of removing silicon oxide layer and laminated structure

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5525910A (en) * 1978-08-12 1980-02-25 Hamamatsu Denshi Kogaku Shiyoureikai Multiple cold emission cathode
JPH02142041A (en) * 1988-09-23 1990-05-31 Thomson Csf Diode, triode or element such as flat integrated cathode ray liminescence display unit and manufacture thereof
US5199918A (en) * 1991-11-07 1993-04-06 Microelectronics And Computer Technology Corporation Method of forming field emitter device with diamond emission tips
KR960009060A (en) * 1994-08-05 1996-03-22 김준성 Field emitter device and method of manufacturing the same
KR960042851A (en) * 1995-05-12 1996-12-21 김준성 Field emission device having a porous gate electrode and method of manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5525910A (en) * 1978-08-12 1980-02-25 Hamamatsu Denshi Kogaku Shiyoureikai Multiple cold emission cathode
JPH02142041A (en) * 1988-09-23 1990-05-31 Thomson Csf Diode, triode or element such as flat integrated cathode ray liminescence display unit and manufacture thereof
US5199918A (en) * 1991-11-07 1993-04-06 Microelectronics And Computer Technology Corporation Method of forming field emitter device with diamond emission tips
KR960009060A (en) * 1994-08-05 1996-03-22 김준성 Field emitter device and method of manufacturing the same
KR960042851A (en) * 1995-05-12 1996-12-21 김준성 Field emission device having a porous gate electrode and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101377170B1 (en) * 2013-02-13 2014-03-27 포항공과대학교 산학협력단 Method of removing silicon oxide layer and laminated structure

Also Published As

Publication number Publication date
KR19980054382A (en) 1998-09-25

Similar Documents

Publication Publication Date Title
US4405710A (en) Ion beam exposure of (g-Gex -Se1-x) inorganic resists
US4072768A (en) Method for making patterned gold metallization
Steckl et al. Photoluminescence from stain‐etched polycrystalline Si thin films
US4720469A (en) Method for diffusing aluminum
GB2101353A (en) Radiation lithography mask and method of manufacturing same
GB2091170A (en) Selectively etched bodies
KR100404171B1 (en) Method for forming pattern on silicon surface having nea characteristic
US5264077A (en) Method for producing a conductive oxide pattern
KR20090065825A (en) Shadow mask and method for fabricating of the same
US5348909A (en) Manufacture of printhead with diamond resistors
CN111399343B (en) Sb doping based on laser direct writing metal 2 Self-interference exposure method of Te thin film
EP0518545A1 (en) Dry lithographic etching with gaseous mixtures of oxygen and chlorine
US20020119663A1 (en) Method for forming a fine structure on a surface of a semiconductor material, semiconductor materials provided with such a fine structure, and devices made of such semiconductor materials
US3471291A (en) Protective plating of oxide-free silicon surfaces
JPS63133629A (en) Manufacture of integrated circuit device
JPH08307011A (en) Light emitting element and its manufacturing method
JPS6024933B2 (en) Electron sensitive inorganic resist
JPH05109670A (en) Dry etching method
Kumar et al. Photon and electron beam induced chemical solubility changes in amorphous P–Ge–Se thin films
JPH06295889A (en) Formation of fine pattern
JPH0247848B2 (en)
JPH0452613B2 (en)
KR100245098B1 (en) Method of manufacturing nitrogen doped diamond
Yavas et al. Pulsed Laser Deposition of Diamond-Like Carbon Films on Gated Si Field Emitter Arrays for Improved Electron Emission
JPS5615045A (en) Formation of pattern

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
N231 Notification of change of applicant
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20070918

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee