KR100400763B1 - Method for manufacturing capacitor of semiconductor device - Google Patents
Method for manufacturing capacitor of semiconductor device Download PDFInfo
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- KR100400763B1 KR100400763B1 KR1019960058107A KR19960058107A KR100400763B1 KR 100400763 B1 KR100400763 B1 KR 100400763B1 KR 1019960058107 A KR1019960058107 A KR 1019960058107A KR 19960058107 A KR19960058107 A KR 19960058107A KR 100400763 B1 KR100400763 B1 KR 100400763B1
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- insulating layer
- polysilicon layer
- layer
- polysilicon
- insulating
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 239000003990 capacitor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 58
- 229920005591 polysilicon Polymers 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 230000008021 deposition Effects 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims 1
- 125000006850 spacer group Chemical group 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 59
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 150000004767 nitrides Chemical class 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체소자 제조방법에 관한 것으로 특히, 캐패시터의 정전용량을 최대화하여 고집적에 적당하도록 한 반도체소자의 캐패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device in which the capacitance of the capacitor is maximized and suitable for high integration.
이하, 종래 반도체소자의 캐패시터 제조방법을 첨부된 도면을 참조하여 설명하면 다음과 같다.Hereinafter, a method of manufacturing a capacitor of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a 내지 1f는 종래 반도체소자의 캐패시터 제조방법을 나타낸 공정단면도이다.1A to 1F are cross-sectional views illustrating a method of manufacturing a capacitor of a conventional semiconductor device.
도 1a에 도시한 바와같이 복수의 소자(도면에 도시되지 않음)들이 형성된 반도체기판(1)상에 층간절연막으로서 제 1 산화막(2)온 증착한 후 상기 제 1 산화막(2)상에 제 1 질화막(3)을 증착한다.As shown in FIG. 1A, a first oxide film 2 is deposited as an interlayer insulating film on a semiconductor substrate 1 on which a plurality of elements (not shown) are formed, and then a first oxide film 2 is deposited on the first oxide film 2. The nitride film 3 is deposited.
여기서 상기 제 1 질화막(3)은 후공정시 에치 스톱층(etch stop-layer)으로 사용한다.In this case, the first nitride film 3 is used as an etch stop layer in a later process.
이어 도 1b에 도시한 바와같이 상기 제 1 질화막(3)상에 포토레지스트(도면에 도시하지 않음)를 도포한 후 포토리소그래피(photolithography)공정을 통해 패터닝한다.Subsequently, as shown in FIG. 1B, a photoresist (not shown) is applied on the first nitride film 3 and then patterned through a photolithography process.
상기 패터닝된 포토레지스트를 마스크로 이용하여 상기 제 1 질화막(3)과 제 1 산화막(2)을 선택적으로 제거하여 반도체기판(1)이 노출되도록 콘택홀을 형성한다.By using the patterned photoresist as a mask, the first nitride layer 3 and the first oxide layer 2 are selectively removed to form a contact hole so that the semiconductor substrate 1 is exposed.
그리고 상기 콘택홀을 포함한 반도체기판(1)전면에 제 1 폴리실리콘층(4)을 형성한다.The first polysilicon layer 4 is formed on the entire surface of the semiconductor substrate 1 including the contact hole.
이때 상기 제 1 폴리실리콘층(4)의 두께는 약 3000Å으로한다,At this time, the thickness of the first polysilicon layer 4 is about 3000 kPa,
이어 도 1c에 도시한 바와같이 상기 제 1 폴리실리콘층(4)상에 제 2 산화막(5)을 증착하고 상기 제 2 산화막(5)상에 포토레지스트(도면에 도시하지 않음)를 도포한다.Subsequently, as illustrated in FIG. 1C, a second oxide film 5 is deposited on the first polysilicon layer 4, and a photoresist (not shown) is applied on the second oxide film 5.
그리고 상기 포토레지스트를 패터닝한 후 패터닝된 포토레지스트를 마스크로 이용하여 상기 제 2 산화막(5)을 선택적으로 제거한다.After patterning the photoresist, the second oxide film 5 is selectively removed using the patterned photoresist as a mask.
여기서 상기 제 2 신화막(5) 제거시, 상기 콘택홀과 그 주변의 제 1 폴리실리콘층(4)상에만 남도록 선택적으로 제거한다.In this case, the second myth film 5 is selectively removed to remain only on the contact hole and the first polysilicon layer 4 in the vicinity thereof.
이어 도 1d에 도시한 바와같이 상기 제 2 산화막(5)을 포함한 반도체기판(1) 전면에 제 2 폴리실리콘층(6)과 제 3 산화막을 차례로 형성한 후 상기 제 3 산화막을 에치백(etch back)하여 측벽(sidewall spacer)(7)을 형성한다.Subsequently, as shown in FIG. 1D, a second polysilicon layer 6 and a third oxide film are sequentially formed on the entire surface of the semiconductor substrate 1 including the second oxide film 5, and then the back oxide is etched back. back to form sidewall spacers 7.
이때 상기 제 2 폴리실리콘층(6)의 두께는 약 1000Å으로 한다.At this time, the thickness of the second polysilicon layer 6 is about 1000 kPa.
그리고 도 1e에 도시한 바와같이 상기 측벽(7)을 마스크로하여 제 2 폴리실리콘층(6)과 제 2 폴리실리콘층(4)을 식각한다.As shown in FIG. 1E, the second polysilicon layer 6 and the second polysilicon layer 4 are etched using the sidewall 7 as a mask.
이때 상기 제 1 질화막(3)을 에치스톱층으로 이용하여 제 1 질화막(3)의 표면이 노출될 때까지 식각한다.At this time, using the first nitride film 3 as an etch stop layer, the first nitride film 3 is etched until the surface of the first nitride film 3 is exposed.
그리고 참조부호 "가" 부분은 상기 제 1 폴리실리콘층(4)의 증착두께가 상기 제 2 산화막(5)의 증착두께보다 더 크므로 인해서 상기 제 2 폴리실리콘층(6)식각후 제 1 폴리실리콘층(4)까지 연속하여 식각되기 때문이다.The reference numeral “a” indicates that the first polysilicon layer 4 is etched because the deposition thickness of the first polysilicon layer 4 is greater than the deposition thickness of the second oxide film 5. This is because the silicon layer 4 is continuously etched.
이어 도 1f에 도시한 바와같이 상기 제 3 산화막으로 형성된 측벽(7)과 상기 제 1 폴리실리콘층(4)상의 제 2 산화막(5)을 식각하여 제거하면 실린더 형상의 캐패시터 하부전극(8)이 형성된다.Subsequently, as shown in FIG. 1F, when the sidewall 7 formed of the third oxide film and the second oxide film 5 on the first polysilicon layer 4 are etched and removed, the cylindrical capacitor lower electrode 8 is removed. Is formed.
그러나 이와같은 종래 반도체소자의 캐패시터 제조방법은 다음과 같은 문제가 있었다.However, the conventional method of manufacturing a capacitor of a semiconductor device has the following problems.
즉, 셀 콘택홀이 폴리실리콘으로 매립되어 있으므로 콘택홀 안쪽에는 캐패시터의 하부전극으로 사용할 수 없으므로 정전용량이 그 만큼 줄어들게 된다.In other words, since the cell contact hole is filled with polysilicon, the capacitance cannot be reduced because the cell contact hole cannot be used as a lower electrode of the capacitor.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로서 콘택홀 안쪽에 불필요하게 매립되어 있는 폴리실리콘을 제거하므로서 정전용량을 최대한 확보하는데 적당한 반도체소자의 캐패시터 제조방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor device suitable for securing the maximum capacitance by eliminating the polysilicon that is unnecessarily embedded in the contact hole as a solution to solve the above problems.
도 1a 내지 1f는 종래 반도체소자의 캐패시터 제조방법을 나타낸 공정단면도1A to 1F are cross-sectional views illustrating a method of manufacturing a capacitor of a conventional semiconductor device.
도 2a 내지 2f는 본 발명의 반도체소자의 캐패시터 제조방법을 나타낸 공정단면도2A through 2F are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
21 : 반도체기판 22 : 제 1 절연막21 semiconductor substrate 22 first insulating film
23 : 제 2 절연막 24 : 제 1 폴리실리콘층23: second insulating film 24: first polysilicon layer
25 : 포토레지스트 26 : 셀 콘택홀25 photoresist 26 cell contact hole
27 : 제 2 폴리실리콘층 28 : 제 3 절연막27: second polysilicon layer 28: third insulating film
29 : 제 3 폴리실리콘층 30 : 측벽29: third polysilicon layer 30: side wall
31 : 캐패시터 하부전극31: capacitor lower electrode
상기의 목적을 달성하기 위한 본 발명의 반도체소자의 캐패시터 제조방법은 실린더 형상의 캐패시터 제조에 있어서, 반도체기판상에 제 1, 제 2 절연층을 차례로 형성하는 공정과, 상기 제 2 절연층상에 제 1 폴리실리콘층을 형성하고 셀 영역의 반도체기판이 노출치도록 상기 제 1 폴리실리콘층과, 제 2, 제 1 절연층을 선택적으로 제거하여 셀 콘택홀을 형성하는 공정과, 상기 콘택홀을 포함한 전면에 제 2 폴리실리콘층과 제 3 절연층을 차례로 형성하는 공정과, 상기 제 3 절연층을 선택적으로 제거하여 상기 콘택홀보다 넓은 폭으로 패터닝하고 상기 제 3 절연층을 포함한 전면에 제 3 폴리실리콘층과 제 4 절연층을 차례로 형성하는 공전과, 상기 제 4 절연층을 선택적으로 제거하여 제 3 폴리실리콘층의 양측면에 측벽을 형성하고 이를 마스크로하여 제 3, 제 2, 제 1 폴리실리콘층을 선택적으로 제거하는 공정과, 상기 제 3 절연층과 제 4 절연층을 제거하여 캐패시터 하부전극을 형성하는 공정을 포함하여 이루어진다.In order to achieve the above object, a method of manufacturing a capacitor of a semiconductor device according to the present invention includes the steps of forming a first and a second insulating layer on a semiconductor substrate in order to manufacture a capacitor of a cylindrical shape, and Forming a cell contact hole by selectively removing the first polysilicon layer and the second and first insulating layers so as to form a polysilicon layer and expose the semiconductor substrate in the cell region; and a front surface including the contact hole Forming a second polysilicon layer and a third insulating layer in turn, selectively removing the third insulating layer, patterning the film to a wider width than the contact hole, and forming a third polysilicon on the entire surface including the third insulating layer A layer and a fourth insulating layer are sequentially formed, and the fourth insulating layer is selectively removed to form sidewalls on both sides of the third polysilicon layer, and the third and And selectively removing the second and first polysilicon layers, and removing the third and fourth insulating layers to form a capacitor lower electrode.
이하, 본 발명의 반도체소자의 캐패시터 제조방법을 첨부된 도면을 참조하여 설명하면 다음과 같다.Hereinafter, a method of manufacturing a capacitor of a semiconductor device of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 2f는 본 발명의 반도체소자의 캐패시터 제조방법을 나타낸 공정 단면도이다.2A to 2F are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device of the present invention.
먼저, 도 2a에 도시한 바와같이 반도체기판(21)상에 층간절연막으로서 제 1 절연막(22)을 증착한 후 상기 제 1 절연막(22)상에 제 2 절연막(23)을 차례로 증착한다.First, as shown in FIG. 2A, the first insulating film 22 is deposited on the semiconductor substrate 21 as an interlayer insulating film, and then the second insulating film 23 is sequentially deposited on the first insulating film 22.
그리고 상기 제 2 절연막(23)상에 제 1 폴리실리콘층(24)을 형성하고 상기 제 1 폴리실리콘층(24)상에 포토레지스트(25)를 도포한다.The first polysilicon layer 24 is formed on the second insulating layer 23, and the photoresist 25 is coated on the first polysilicon layer 24.
이어 셀 콘택형성을 위해 상기 포토레지스트(25)를 패터닝한다.The photoresist 25 is then patterned for cell contact formation.
이때 상기 제 1 절연막(22)은 산화막이고 제 2 절연막(23)은 질화막이다.In this case, the first insulating film 22 is an oxide film and the second insulating film 23 is a nitride film.
그리고 상기 제 1 폴리실리콘층(24)의 두께는 약 2500Å으로 한다.The thickness of the first polysilicon layer 24 is about 2500 kPa.
이어서, 도 2b에 도시한 바와같이 상기 패터닝된 포토레지스트(25)를 마스크로 이용하여 그 하부의 제 1 폴리실리콘층(24)과 제 2 절연막(23) 그리고 제 1 절연막(22)을 선택적으로 제거하여 셀 영역의 반도체기판(21)의 표면을 노출시켜 셀 콘택홀(26)을 형성한다.Subsequently, as shown in FIG. 2B, the patterned photoresist 25 is used as a mask to selectively select the first polysilicon layer 24, the second insulating film 23, and the first insulating film 22 thereunder. The cell contact hole 26 is formed by exposing the surface of the semiconductor substrate 21 in the cell region.
그리고 도 2c에 도시한 바와같이 상기 포토레지스트(25)를 제거한 다음, 노출된 반도체기판(21)을 포함한 전면에 제 2 폴리실리콘층(27)을 형성한다.As shown in FIG. 2C, the photoresist 25 is removed, and then a second polysilicon layer 27 is formed on the entire surface including the exposed semiconductor substrate 21.
이때 상기 제 2 폴리실리콘층(27)의 두께는 약 700Å으로 한다.At this time, the thickness of the second polysilicon layer 27 is about 700 kPa.
다음, 상기 제 2 폴리실리콘층(27)상에 제 3 절연막(28)을 증착한 후 상기셀 콘택홀(26)을 포함한 그 주변의 제 2 폴리실리콘층(27)상에만 남도록 선택적으로 제거한다.Next, a third insulating film 28 is deposited on the second polysilicon layer 27 and then selectively removed so as to remain only on the second polysilicon layer 27 surrounding the cell contact hole 26. .
이때 상기 제 3 절연막(28)은 산화막이다.At this time, the third insulating film 28 is an oxide film.
이어서, 도 2d에 도시한 바와같이 상기 제 3 절연막(28)을 포함한 제 2 폴리실리콘층(27)상에 제 3 폴리실리콘층(29)을 형성하고 상기 제 3 폴리실리콘층(29) 상에 제 4 절연막을 증착한다.Subsequently, as shown in FIG. 2D, a third polysilicon layer 29 is formed on the second polysilicon layer 27 including the third insulating layer 28 and on the third polysilicon layer 29. A fourth insulating film is deposited.
이때 상기 제 3 폴리실리콘층(29)의 두께는 약 1000Å이며 상기 제 4 절연막은 산화막이다.At this time, the thickness of the third polysilicon layer 29 is about 1000 kPa and the fourth insulating film is an oxide film.
이어, 상기 제 4 절연막을 에치백(etch back)하여 상기 제 3 폴리실리콘층(29)의 측면에 측벽(sidewall spacer)(30)을 형성한다.Next, the fourth insulating layer is etched back to form sidewall spacers 30 on the side surfaces of the third polysilicon layer 29.
그리고 도 2e에 도시한 바와같이 상기 측벽(30)을 마스크로하여 제 3, 제 2 폴리실리콘층(29,27) 그리고 제 1 폴리실리콘층(24)을 선택적으로 제거한다.As shown in FIG. 2E, the third and second polysilicon layers 29 and 27 and the first polysilicon layer 24 are selectively removed using the sidewall 30 as a mask.
이때 상기 에치스톱층으로 사용되는 제 2 절연막(23)의 표면이 노출될 때까지 상기 폴리실리콘층들을 건식식각한다.In this case, the polysilicon layers are dry-etched until the surface of the second insulating layer 23 used as the etch stop layer is exposed.
그리고 참조부호 "나" 부분은 상기 제 1 폴리실리콘층(4)의 증착두께가 상기 제 3 절연막(28)의 증착두께보다 더 크므로 인해서 상기 제 3 폴리실리콘층(29)식각 후 제 2, 제 1 폴리실리콘층(27,24)까지 연속하여 식각되기 때문이다.The reference symbol “B” denotes a second thickness after etching the third polysilicon layer 29 because the deposition thickness of the first polysilicon layer 4 is greater than the deposition thickness of the third insulating layer 28. This is because the first polysilicon layers 27 and 24 are continuously etched.
이어서, 도 1f에 도시한 바와같이 상기 제 4 절연막으로 형성된 측벽(30)과 상기 제 2 폴리실리콘층(24)상의 제 3 절연막(28)을 제거하여 실린더 형상의 캐패시터 하부전극(31)을 형성된다.Subsequently, as shown in FIG. 1F, the sidewall 30 formed of the fourth insulating film and the third insulating film 28 on the second polysilicon layer 24 are removed to form the capacitor lower electrode 31 having a cylindrical shape. do.
이상 상술한 바와같이 본 발명의 반도체소자의 캐패시터 제조방법은 다음과 같은 효과가 있다.As described above, the method of manufacturing the capacitor of the semiconductor device of the present invention has the following effects.
셀 콘택홀 안쪽을 캐패시터의 하부전극으로 사용하여 단면적을 크게 하므로서 정전용량을 증가시킬 수 있다.By using the inside of the cell contact hole as the lower electrode of the capacitor, the capacitance can be increased by increasing the cross-sectional area.
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| KR1019960058107A KR100400763B1 (en) | 1996-11-27 | 1996-11-27 | Method for manufacturing capacitor of semiconductor device |
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| KR1019960058107A KR100400763B1 (en) | 1996-11-27 | 1996-11-27 | Method for manufacturing capacitor of semiconductor device |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5026659A (en) * | 1989-08-23 | 1991-06-25 | Gold Star Electron Co., Ltd. | Process for fabricating stacked trench capacitors of dynamic ram |
| KR940010343A (en) * | 1992-10-16 | 1994-05-26 | 문정환 | Method for manufacturing storage node electrode of semiconductor device |
| JPH06302764A (en) * | 1993-04-12 | 1994-10-28 | Nec Corp | Manufacture of thin film capacitor |
| KR960026661A (en) * | 1994-12-30 | 1996-07-22 | 김주용 | Method of forming charge storage electrode of capacitor |
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1996
- 1996-11-27 KR KR1019960058107A patent/KR100400763B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5026659A (en) * | 1989-08-23 | 1991-06-25 | Gold Star Electron Co., Ltd. | Process for fabricating stacked trench capacitors of dynamic ram |
| KR940010343A (en) * | 1992-10-16 | 1994-05-26 | 문정환 | Method for manufacturing storage node electrode of semiconductor device |
| JPH06302764A (en) * | 1993-04-12 | 1994-10-28 | Nec Corp | Manufacture of thin film capacitor |
| KR960026661A (en) * | 1994-12-30 | 1996-07-22 | 김주용 | Method of forming charge storage electrode of capacitor |
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