KR100400301B1 - A method for forming a field oxide of semiconductor device - Google Patents
A method for forming a field oxide of semiconductor device Download PDFInfo
- Publication number
- KR100400301B1 KR100400301B1 KR10-1999-0066322A KR19990066322A KR100400301B1 KR 100400301 B1 KR100400301 B1 KR 100400301B1 KR 19990066322 A KR19990066322 A KR 19990066322A KR 100400301 B1 KR100400301 B1 KR 100400301B1
- Authority
- KR
- South Korea
- Prior art keywords
- oxide film
- forming
- film
- semiconductor device
- trench
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 98
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000002955 isolation Methods 0.000 claims abstract description 38
- 230000003647 oxidation Effects 0.000 claims abstract description 24
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 24
- 150000004767 nitrides Chemical class 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000001039 wet etching Methods 0.000 claims abstract description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910001873 dinitrogen Inorganic materials 0.000 claims abstract description 5
- 238000011049 filling Methods 0.000 claims abstract description 5
- 238000000206 photolithography Methods 0.000 claims abstract description 5
- 238000004140 cleaning Methods 0.000 claims abstract description 4
- 238000000137 annealing Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 238000002156 mixing Methods 0.000 claims description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 2
- 239000011800 void material Substances 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000007598 dipping method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009918 complex formation Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000009271 trench method Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Element Separation (AREA)
Abstract
본 발명은 반도체소자의 소자분리막 형성방법에 관한 것으로, 반도체기판 상부에 패드산화막을 건식산화시켜 형성하고 그 상부에 패드질화막을 형성한 다음, 소자분리마스크를 이용한 사진식각공정으로 상기 패드질화막과 패드산화막 및 일정깊이의 반도체기판을 식각하여 트렌치를 형성하고 상기 트렌치 표면에 희생산화막을 건식산화방법으로 형성한 다음, 이를 습식방법으로 제거하고 상기 트렌치 측벽에 월 산화막을 건식산화방법으로 형성한 다음, 이를 습식방법으로 제거하고 전체표면상부에 라이너 산화막을 형성한 다음, 상기 트렌치를 매립하는 HDP 산화막을 형성하고 질소가스 분위기에서 어닐링한 다음, 상기 HDP 산화막을 CMP 방법으로 평탄화식각하고 상기 패드질화막을 제거한 다음, 상기 게이트산화막 전의 세정 공정을 습식 식각방법으로 실시하는 공정으로 턱짐 ( moat )을 작게 형성함으로써 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 기술이다.The present invention relates to a method of forming a device isolation film of a semiconductor device, which is formed by dry oxidation of a pad oxide film on an upper surface of a semiconductor substrate, a pad nitride film is formed thereon, and then the pad nitride film and the pad by a photolithography process using a device isolation mask. After etching the oxide film and the semiconductor substrate of a predetermined depth to form a trench, a sacrificial oxide film is formed on the surface of the trench by dry oxidation method, then removed by a wet method and a month oxide film is formed on the sidewall of the trench by dry oxidation method, This method is removed by a wet method, and a liner oxide film is formed on the entire surface. Then, an HDP oxide film filling the trench is formed and annealed in a nitrogen gas atmosphere. Then, the HDP oxide film is flattened by a CMP method and the pad nitride film is removed. Next, the cleaning process before the gate oxide film is performed by a wet etching method. It is a technique that can improve the characteristics and reliability of the semiconductor device by forming a small moat (Moat) by the process performed by.
Description
본 발명은 반도체소자의 소자분리막 형성방법에 관한 것으로, 특히 트렌치형 소자분리막과 활성영역의 경계 부분에 형성되는 턱짐 ( moat ) 현상으로 인한 소자의 특성 열화를 방지하기 위하여 턱짐현상을 최소화시킬 수 있도록 하는 기술에 관한 것이다.The present invention relates to a method of forming a device isolation film of a semiconductor device, and in particular to minimize the phenomenon of the device to prevent deterioration of the device due to the moat phenomenon formed in the boundary between the trench type device isolation film and the active region. It is about technology to do.
고집적화라는 관점에서 소자의 집적도를 높이기 위해서는 각각의 소자 디맨젼 ( dimension ) 을 축소하는 것과, 소자간에 존재하는 분리영역 ( isolation region ) 의 폭과 면적을 축소하는 것이 필요하며, 이 축소정도가 셀의 크기를 좌우한다는 점에서 소자분리기술이 메모리 셀 사이즈 ( memory cell size ) 를 결정하는 기술이라고 할 수 있다.In order to increase the integration of devices from the viewpoint of high integration, it is necessary to reduce each device dimension and to reduce the width and area of isolation regions existing between devices. Device isolation technology determines the memory cell size in terms of size.
소자분리절연막을 제조하는 종래기술로는 절연물 분리방식의 로코스 ( LOCOS : LOCal Oxidation of Silicon, 이하에서 LOCOS 라 함 ) 방법, 실리콘기판상부에 산화막, 다결정실리콘층, 질화막순으로 적층한 구조의 피.비.엘. ( Poly - Buffed LOCOS, 이하에서 PBL 이라 함 ) 방법, 기판에 홈을 형성한 후에 절연물질로 매립하는 트렌치 ( trench ) 방법 등이 있다.Conventional techniques for manufacturing device isolation insulating films include LOCOS (LOCOS: LOCOS) method, an oxide film, a polysilicon layer, and a nitride film on a silicon substrate. B.L. (Poly-Buffed LOCOS, hereinafter referred to as PBL) method, a trench method of embedding an insulating material after forming a groove in the substrate, and the like.
그러나, 상기 LOCOS 방법으로 소자분리산화막을 미세화할 때 공정상 또는 전기적인 문제가 발생한다. 그중의 하나는, 소자분리절연막만으로는 전기적으로 소자를 완전히 분리할 수 없다는 것이다.However, a process or electrical problem occurs when the device isolation oxide film is miniaturized by the LOCOS method. One of them is that the device isolation insulating film alone cannot completely separate the device.
그리고, 상기 PBL 을 사용하는 경우, 필드산화시에 산소의 측면확산에 의하여 버즈빅이 발생한다. 즉, 활성영역이 작아져 활성영역을 효과적으로 활용하지 못하며, 필드산화막의 두께가 두껍기 때문에 단차가 형성되어 후속공정에 어려움을 준다. 그리고, 기판상부의 다결정실리콘층으로 인하여 필드산화시 기판내부로 형성되는 소자분리절연막이 타기법에 비하여 상대적으로 작기 때문에 타기법에 비해 신뢰성을 약화시킬 수 있다.In the case of using the above-mentioned PBL, buzz big is generated by side diffusion of oxygen during field oxidation. In other words, the active area is small, so that the active area is not effectively utilized, and because the thickness of the field oxide film is thick, a step is formed, which causes difficulty in subsequent processes. Further, due to the polysilicon layer on the substrate, the device isolation insulating film formed inside the substrate during field oxidation is relatively smaller than that of the hitting method, thereby reducing the reliability of the hitting method.
이상에서 설명한 LOCOS 방법과 PBL 방법은 반도체기판 상부로 볼록한 소자분리절연막을 형성하여 단차를 갖게 됨으로써 후속공정을 어렵게 하는 단점이 있다.The LOCOS method and the PBL method described above have a disadvantage in that a subsequent step is made difficult by forming a convex element isolation insulating film on the semiconductor substrate and having a step.
이러한 단점을 해결하기 위하여, 반도체기판을 식각하여 트렌치를 형성하고 상기 트렌치를 매립한 다음, CMP 방법을 이용하여 상부면을 평탄화시키고 후속공정을 평탄화시킴으로써 후속공정을 용이하게 실시할 수 있도록 하였다.In order to solve this disadvantage, the semiconductor substrate is etched to form a trench, and the trench is buried, and then the CMP method is used to planarize the top surface and to planarize the subsequent process so that the subsequent process can be easily performed.
상기 트렌치 식각후에 식각 손상은 고온 산화공정으로 산화막을 형성하고, 상기 산화막을 제거하여 보상한다. 이때, 활성영역에 존재하는 패드 산화막의 일부가 함께 제거되어 소자분리영역, 즉 트렌치 매립시 보이드 생성을 유발하게 된다.The etching damage after the trench etching is compensated for by forming an oxide film by a high temperature oxidation process and removing the oxide film. At this time, a part of the pad oxide layer existing in the active region is removed together to cause the void formation during the isolation region, that is, the trench filling.
현재 사용되는 트렌치형 소자분리막 형성공정에서 상기 보이드 생성을 방지하기 위하여 라이너 산화막 ( liner oxide ) 을 증착한다.In order to prevent the generation of the voids, a liner oxide is deposited in a trench type device isolation film forming process currently used.
그러나, 상기 라이너 산화막과 상기 라이너 산화막 증착공정후 형성되는 소자분리막과의 산화막 제거용 습식 용액에 대한 식각 선택비 차이로 인하여 후속 공정진행시 필드 산화막의 프로파일은 상측 끝부분이 상측 중앙부분보다 꺼지는 턱짐 현상이 발생하게 되고, 이 현상은 소자의 동작과 특성에 악영향을 끼치게 된다.However, due to the difference in the etch selectivity of the oxide solution removal solution between the liner oxide layer and the device isolation layer formed after the deposition process of the liner oxide layer, the profile of the field oxide layer during the subsequent process is lower than that of the upper center portion. This phenomenon occurs, which adversely affects the operation and characteristics of the device.
상기한 종래기술의 문제점을 해결하기 위하여 최근에는, 트렌치 프로파일의 개선을 위해 실시하는 열 측벽 산화공정을 실시하였다.In order to solve the above problems of the prior art, a thermal sidewall oxidation process has recently been carried out to improve the trench profile.
그러나, 상기 열 측벽 산화공정은 활성영역 부분의 패드 산화막을 두껍게 형성하였고 특히 좁은 활성영역 쪽에 심하게 발생하는데 이는 라이너 산화막 증착 조건과 함께 소자분리영역의 끝부분을 복잡하게 형성하는 원인으로 작용한다.However, the thermal sidewall oxidation process forms a thick pad oxide layer in the active region, particularly in the narrow active region, which causes a complex formation of the end of the device isolation region together with the liner oxide deposition conditions.
종래의 방법대로 위의 사항을 고려하지 않고 패드산화막의 두께를 너무 두껍게 형성하면 월 산화공정시 패드 산화막의 두께는 더 두꺼워져 최종적으로 패드 산화막을 제거할때 활성영역 끝부분의 프로파일이 평탄하지 않고 비스듬하게 되며, 라이너 산화막의 두께가 너무 두껍거나 습식 세정에 대한 식각선택비가 소자분리막과 크게 차이나면 소자분리막의 끝부분 높이가 중앙쪽과 다른 프로파일을 갖게 된다.If the thickness of the pad oxide film is made too thick without considering the above matters according to the conventional method, the thickness of the pad oxide film becomes thicker during the month oxidation process, so that the profile of the end of the active region is not flat when the pad oxide film is finally removed. If the thickness of the liner oxide is too thick or the etching selectivity for wet cleaning is significantly different from that of the device isolation layer, the tip height of the device isolation layer has a profile different from that of the center side.
따라서, 상기한 원리를 고려하지 않고 공정을 진행하면 턱짐 프로파일의 발생을 억제할 수 없게 되어 후속 이온주입공정에 있어서 셀 어레이 지역에 균일한 이온 도핑 프로파일의 형성 저해로 인해 소자의 트랜지스터 동작에 오류를 가져오게 되며, 특히 셀 문턱전압이 다이(die) 간 또는 웨이퍼(wafer) 간에 재현성있는 값을 유지하지 못하도록 하여 소자의 특성과 수율을 저하시키는 문제점이 있다.Therefore, if the process is carried out without considering the above-mentioned principle, it is impossible to suppress the occurrence of the jaw profile, and thus the transistor operation of the device is prevented due to the inhibition of formation of uniform ion doping profile in the cell array region in the subsequent ion implantation process. In particular, there is a problem in that the cell threshold voltage does not maintain a reproducible value between dies or wafers, thereby degrading device characteristics and yield.
또한, 턱짐 프로파일은 워드라인 식각공정후 폴리실리콘성 잔유물을 유발하여 전극과 전극 사이를 쇼트 ( short ) 시켜 반도체소자의 수율을 저하시키는 문제점이 있다.In addition, the jaw profile causes a polysilicon residue after the word line etching process to shorten the electrode and the electrode, thereby lowering the yield of the semiconductor device.
본 발명은 상기한 종래기술의 문제점을 해결하기위하여, 패드산화막 두께, 월 산화막 두께, 보이드 방지 산화막인 라이너 산화막 증착 조건 및 상기 라이너 산화막의 습식식각조건 등을 조절하여 턱짐 현상을 억제할 수 있는 소자분리막을 형성함으로써 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 소자분리막 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the problems of the prior art, the pad oxide film thickness, the thickness of the wall oxide film, the anti-void oxide film liner oxide deposition conditions and the wet etching conditions of the liner oxide film by adjusting the device can be suppressed It is an object of the present invention to provide a method for forming a device isolation film of a semiconductor device by improving the characteristics and reliability of the semiconductor device by forming the separation film, thereby enabling high integration of the semiconductor device.
도 1 은 본 발명에 따른 소자분리막 형성공정후 형성되는 트랜지스터의 전류특성을 도시한 그래프도.1 is a graph showing the current characteristics of the transistor formed after the device isolation film forming process according to the present invention.
도 2 는 본 발명에 따른 소자분리막 형성공정후 형성되는 트랜지스터의 문턱전압 특성을 도시한 그래프도.2 is a graph showing the threshold voltage characteristics of a transistor formed after the device isolation film forming process according to the present invention.
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 소자분리막 형성방법은,In order to achieve the above object, a device isolation film forming method of a semiconductor device according to the present invention,
반도체기판 상부에 패드산화막을 건식산화시켜 형성하고 그 상부에 패드질화막을 형성하는 공정과,Forming a pad oxide film on the semiconductor substrate by dry oxidation and forming a pad nitride film on the top;
소자분리마스크를 이용한 사진식각공정으로 상기 패드질화막과 패드산화막 및 일정깊이의 반도체기판을 식각하여 트렌치를 형성하는 공정과,Forming a trench by etching the pad nitride layer, the pad oxide layer, and a semiconductor substrate having a predetermined depth by a photolithography process using an element isolation mask;
상기 트렌치 표면에 희생산화막을 건식산화방법으로 형성하고 이를 습식방법으로 제거하는 공정과,Forming a sacrificial oxide film on the surface of the trench by a dry oxidation method and removing the sacrificial oxide film by a wet method;
상기 트렌치 측벽에 월 산화막을 건식산화방법으로 형성하고 이를 습식방법으로 제거하는 공정과,Forming a monthly oxide film on the sidewalls of the trench by a dry oxidation method and removing the wet oxide film by a wet method;
전체표면상부에 라이너 산화막을 형성하고 상기 트렌치를 매립하는 HDP 산화막을 형성한 다음, 질소가스 분위기에서 어닐링하는 공정과,Forming a liner oxide film over the entire surface, forming an HDP oxide film filling the trench, and then annealing in a nitrogen gas atmosphere;
상기 HDP 산화막을 CMP 방법으로 평탄화식각하고 상기 패드질화막을 제거한 다음, 상기 게이트산화막 전의 세정 공정을 습식 식각방법으로 실시하는 공정을 포함하는 것을 특징으로한다.And planarization etching the HDP oxide film by the CMP method, removing the pad nitride film, and performing a wet etching method before the gate oxide film by a wet etching method.
한편, 이상의 목적을 달성하기 위한 본 발명의 원리는, 월 산화공정시 패드산화막이 두꺼워지는 현상을 고려하여 패드산화막과 월 산화막의 두께를 적절히 조절하여 패드산화막 제거공정시 활성영역 끝부분이 심하게 기울어 지는 현상을 막는 것과 라이너 산화막의 두께를 적절히 조절하여 보이드 방지의 일차적인 목적과 소자분리막 내에서 차지하는 비중을 조절하여 턱짐 프로파일이 발생 가능한 범위를 줄이는 것, 라이너 산화막과 소자분리막 간의 습식 식각 선택비 차이를 없애기 위하여 적절한 온도로 어닐링 공정을 진행하는 것, 그리고 소자분리막 형성공정후 실시되는 산화막 제거공정의 적절한 시간조절을 통하여 소자분리막의 전체 높이를 활성영역과 같거나 100 ∼ 200 Å 두께 높게 조절하여 턱짐 프로파일의 발생을 억제하는 것이다.On the other hand, the principle of the present invention for achieving the above object, in consideration of the phenomenon that the pad oxide film is thickened during the month oxidation process, by adjusting the thickness of the pad oxide film and the month oxide film properly, the end of the active region is severely inclined during the pad oxide film removal process To prevent loss and to control the thickness of the liner oxide film properly, to reduce the range of protruding profiles by controlling the primary purpose of void prevention and the specific gravity of the device isolation film, and the difference in wet etching selectivity between the liner oxide film and the device isolation film. Through the annealing process at an appropriate temperature to remove the temperature, and by appropriately adjusting the oxide removal process performed after the device isolation film forming process, the overall height of the device isolation film is adjusted to be equal to the active area or to a thickness of 100 to 200 Å thick. It is to suppress the occurrence of the profile.
도 1 및 도 2 는 본 발명에 따라 턱짐이 작은 소자분리막을 형성하고 후속공정으로 트랜지스터의 전류 특성 및 문턱전압 특성을 도시한 그래프도이다.1 and 2 are graphs showing current characteristics and threshold voltage characteristics of transistors in a subsequent step of forming a device isolation film having a small jaw according to the present invention.
이하, 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail.
먼저, 반도체기판 상부에 패드산화막을 800 ∼ 1000 ℃ 온도에서 건식산화방법으로 30 ∼ 70 Å 두께 형성한다.First, a pad oxide film is formed on the semiconductor substrate at a thickness of 30 to 70 Å by dry oxidation at 800 to 1000 ° C.
이때, 상기 패드산화막의 두께를 최소화함으로써 트렌치 식각공정시 유발된 결함을 보상하는 희생산화공정이나 월 산화막 형성공정시 패드 산화막의 재 산화을 억제하고 질화막의 제거공정흐 습식 용액에 디핑하는 시간을 최소화시켜 턱짐 ( moat ) 크기를 최소화 시키기 위한 것이다.In this case, by minimizing the thickness of the pad oxide film, the sacrificial oxidation process for compensating for defects caused during the trench etching process or the month oxide film forming process is suppressed to re-oxidize the pad oxide film and minimizes the time for dipping into the wet solution of the nitride film removal process. This is to minimize the moat size.
그 다음, 상기 패드산화막 상부에 패드질화막을 1100 ∼ 1300 Å 정도의 두께로 형성한다.Next, a pad nitride film is formed on the pad oxide film to a thickness of about 1100 to 1300 mm 3.
그리고, 소자분리마스크를 이용한 사진식각공정으로 상기 패드질화막과 패드산화막 및 일정깊이의 반도체기판을 식각하여 트렌치를 형성한다.In addition, a trench is formed by etching the pad nitride layer, the pad oxide layer, and the semiconductor substrate having a predetermined depth by a photolithography process using a device isolation mask.
그리고, 상기 사진식각공정시 소상된 트렌치 표면에 희생산화시켜 희생산화막을 형성한다. 이때, 상기 희생산화공정은 1000 ∼ 1100 ℃ 온도에서 건식산화방법으로 140 ∼ 160 Å 정도의 두께로 형성한다.In addition, the sacrificial oxide film is formed by sacrificial oxidation on the surface of the trench that is burned during the photolithography process. At this time, the sacrificial oxidation process is formed to a thickness of about 140 ~ 160 Pa by dry oxidation method at a temperature of 1000 ~ 1100 ℃.
그리고, 상기 희생산화막은 습식방법으로 모두 제거하되, 습식용액에 디핑 ( dipping ) 하는 시간을 감소시켜 후속공정에서의 턱짐현상을 감소시킬 수 있다.In addition, the sacrificial oxide film may be removed by a wet method, but dipping in the wet solution may be reduced to reduce jaw phenomenon in a subsequent process.
그 다음, 트렌치 하부의 프로파일을 라운딩하고 턱짐 프로파일을 억제하기위하여 월 산화막을 건식산화방법으로 100 ∼ 150 Å 두께 형성하되, 두께를 증가시켜 상기 턱짐 현상을 감소시킬 수 있다.Then, in order to round the profile of the lower portion of the trench and suppress the jaw profile, the wall oxide film may be formed to have a thickness of 100 to 150 kPa by a dry oxidation method, and the jaw phenomenon may be reduced by increasing the thickness.
그리고, 상기 희생산화막을 습식방법으로 제거할때 패드산화막의 손실로 인하여 유발되는 보이드의 발생을 억제하기 위하여 라이너 산화막을 100 ∼ 150 Å 정도 증착한다.When the sacrificial oxide film is removed by a wet method, a liner oxide film is deposited to have a thickness of about 100 to 150 Pa in order to suppress the generation of voids caused by the loss of the pad oxide film.
이때, 상기 라이너 산화막은 순수한 물과의 혼합비가 50 : 1 인 HF 용액에서 식각선택비가 HDP 산화막보다 낮은 1.6 Å/sec 이하가 되도록 형성한다.In this case, the liner oxide layer is formed in an HF solution having a mixing ratio of 50: 1 with pure water so that the etching selectivity is 1.6 Å / sec or less lower than that of the HDP oxide layer.
그 다음, 상기 트렌치를 매립하는 HDP 산화막을 5000 ∼ 7000 Å 두께 증착한다.Next, an HDP oxide film filling the trench is deposited to have a thickness of 5000 to 7000 GPa.
그리고, 1000 ∼ 1100 ℃ 질소가스 분위기에서 25 ∼ 35 분 동안 어닐링한다.And annealing for 25 to 35 minutes in 1000-1100 degreeC nitrogen gas atmosphere.
그 다음, 상기 HDP 산화막을 CMP 방법으로 평탄화식각한다.Next, the HDP oxide film is planarized by CMP.
그리고, 상기 패드질화막 제거후 게이트산화막 전의 세정 공정까지의 공정중 습식 식각방법에 의한 산화막 손상을 최소화하여 턱짐을 개선한다.In addition, it is possible to minimize the damage of the oxide film by the wet etching method from the pad nitride film removal process to the cleaning process before the gate oxide film, thereby improving the jaw.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 소자분리막 형성방법은, 패드산화막 두께, 희생산화막의 습식식각조건, 월 산화막 두께, 보이드 방지를 위한 라이너 산화막 증착 조건, 질화막 제거후 습식 용액에 의한 산화막 식각조건을 적절하게 수정하여 턱짐 프로파일의 발생을 억제함으로써 반도체소자의 특성 및 신뢰성을 향상시키는 효과를 제공한다.As described above, the method of forming a device isolation film of a semiconductor device according to the present invention includes a pad oxide film thickness, a wet etching condition of a sacrificial oxide film, a monthly oxide film thickness, a liner oxide deposition condition for void prevention, and an oxide film by a wet solution after removing the nitride film. By appropriately modifying the etching conditions to suppress the occurrence of the jaw profile provides an effect of improving the characteristics and reliability of the semiconductor device.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1999-0066322A KR100400301B1 (en) | 1999-12-30 | 1999-12-30 | A method for forming a field oxide of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1999-0066322A KR100400301B1 (en) | 1999-12-30 | 1999-12-30 | A method for forming a field oxide of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010058946A KR20010058946A (en) | 2001-07-06 |
| KR100400301B1 true KR100400301B1 (en) | 2003-10-01 |
Family
ID=19633461
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-1999-0066322A KR100400301B1 (en) | 1999-12-30 | 1999-12-30 | A method for forming a field oxide of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100400301B1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030056388A (en) * | 2001-12-28 | 2003-07-04 | 주식회사 하이닉스반도체 | Method for forming trench isolation in semiconductor device |
| KR101616004B1 (en) * | 2014-11-27 | 2016-04-27 | 주식회사 우진 | Apparatus and Method for Confirming Position of Control Rod in Nuclear Reactor |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0521591A (en) * | 1991-07-12 | 1993-01-29 | Fujitsu Ltd | Manufacture of semiconductor device |
| US5786263A (en) * | 1995-04-04 | 1998-07-28 | Motorola, Inc. | Method for forming a trench isolation structure in an integrated circuit |
| KR19990010757A (en) * | 1997-07-18 | 1999-02-18 | 윤종용 | Device Separation Method of Semiconductor Device |
| KR19990025534A (en) * | 1997-09-12 | 1999-04-06 | 윤종용 | How to form trench isolation region |
| KR19990025197A (en) * | 1997-09-11 | 1999-04-06 | 윤종용 | Trench element isolation |
| KR19990025195A (en) * | 1997-09-11 | 1999-04-06 | 윤종용 | Trench element isolation |
| KR19990055165A (en) * | 1997-12-27 | 1999-07-15 | 김영환 | Device isolation film formation method using trench |
| KR19990065028A (en) * | 1998-01-05 | 1999-08-05 | 윤종용 | Method for removing a trench element of a semiconductor device |
| KR19990066239A (en) * | 1998-01-23 | 1999-08-16 | 윤종용 | Semiconductor device with shallow trench isolation and method of manufacturing the same |
-
1999
- 1999-12-30 KR KR10-1999-0066322A patent/KR100400301B1/en not_active IP Right Cessation
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0521591A (en) * | 1991-07-12 | 1993-01-29 | Fujitsu Ltd | Manufacture of semiconductor device |
| US5786263A (en) * | 1995-04-04 | 1998-07-28 | Motorola, Inc. | Method for forming a trench isolation structure in an integrated circuit |
| KR19990010757A (en) * | 1997-07-18 | 1999-02-18 | 윤종용 | Device Separation Method of Semiconductor Device |
| KR19990025197A (en) * | 1997-09-11 | 1999-04-06 | 윤종용 | Trench element isolation |
| KR19990025195A (en) * | 1997-09-11 | 1999-04-06 | 윤종용 | Trench element isolation |
| KR19990025534A (en) * | 1997-09-12 | 1999-04-06 | 윤종용 | How to form trench isolation region |
| KR19990055165A (en) * | 1997-12-27 | 1999-07-15 | 김영환 | Device isolation film formation method using trench |
| KR19990065028A (en) * | 1998-01-05 | 1999-08-05 | 윤종용 | Method for removing a trench element of a semiconductor device |
| KR19990066239A (en) * | 1998-01-23 | 1999-08-16 | 윤종용 | Semiconductor device with shallow trench isolation and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010058946A (en) | 2001-07-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100316221B1 (en) | Novel shallow trench isolation technique | |
| US6350662B1 (en) | Method to reduce defects in shallow trench isolations by post liner anneal | |
| JP2005197643A (en) | Method for manufacturing flash memory devices | |
| JP2682529B2 (en) | Method for forming element isolation insulating film of semiconductor element | |
| US6107140A (en) | Method of patterning gate electrode conductor with ultra-thin gate oxide | |
| US7301207B2 (en) | Semiconductor device capable of threshold voltage adjustment by applying an external voltage | |
| KR100400301B1 (en) | A method for forming a field oxide of semiconductor device | |
| KR100950749B1 (en) | Method for forming element isolation film of semiconductor device | |
| KR100523920B1 (en) | Method of manufacturing a flash device | |
| KR101077014B1 (en) | Method for forming the isolation layer of semiconductor device | |
| KR100839894B1 (en) | Semiconductor device and fabrication method therefor | |
| KR100473732B1 (en) | Method of forming an isolation layer in a semiconductor device | |
| KR100429678B1 (en) | A method for forming a field oxide of semiconductor device | |
| KR100419754B1 (en) | A method for forming a field oxide of a semiconductor device | |
| KR20040005230A (en) | Method for manufacturing flash memory | |
| KR100663609B1 (en) | Method for manufacturing isolation layer in semiconductor device | |
| KR100557533B1 (en) | Method for Forming Device Isolation Film of Semiconductor Device | |
| KR20050049840A (en) | Method of isolation in semiconductor device | |
| KR100571413B1 (en) | Device Separator Formation Method of Semiconductor Device | |
| KR20030094440A (en) | Method of forming a isolation layer in a semiconductor device and manufacturing a flash memory cell using the same | |
| KR20010061041A (en) | Forming method for a field oxide of semiconductor device | |
| KR20060075424A (en) | Method for manufacturing semiconductor device | |
| KR20040001224A (en) | Method for manufacturing isolation layer in semiconductor device | |
| KR20050059750A (en) | Method of manufacturing semiconductor device | |
| KR20040007950A (en) | Method of manufacture semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100825 Year of fee payment: 8 |
|
| LAPS | Lapse due to unpaid annual fee |