KR100394809B1 - 반도체 패키지 및 그 제조 방법 - Google Patents
반도체 패키지 및 그 제조 방법 Download PDFInfo
- Publication number
- KR100394809B1 KR100394809B1 KR10-2001-0047910A KR20010047910A KR100394809B1 KR 100394809 B1 KR100394809 B1 KR 100394809B1 KR 20010047910 A KR20010047910 A KR 20010047910A KR 100394809 B1 KR100394809 B1 KR 100394809B1
- Authority
- KR
- South Korea
- Prior art keywords
- wiring board
- reinforcing ring
- semiconductor chip
- adhesive
- hole
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 238000000034 method Methods 0.000 title claims description 19
- 238000004519 manufacturing process Methods 0.000 title abstract description 12
- 230000003014 reinforcing effect Effects 0.000 claims abstract description 67
- 239000000853 adhesive Substances 0.000 claims abstract description 48
- 230000001070 adhesive effect Effects 0.000 claims abstract description 48
- 239000000463 material Substances 0.000 claims description 5
- 239000003822 epoxy resin Substances 0.000 claims description 4
- 229920000647 polyepoxide Polymers 0.000 claims description 4
- 230000008569 process Effects 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- 230000002787 reinforcement Effects 0.000 description 4
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 239000013464 silicone adhesive Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 229920006332 epoxy adhesive Polymers 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000004850 liquid epoxy resins (LERs) Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000003351 stiffener Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims (9)
- 상부면과, 상기 상부면에 반대되는 하부면을 갖는 배선기판과;상기 배선기판의 상부면에 플립 칩 본딩되는 반도체 칩과;상기 배선기판 상부면의 가장자리 둘레에 불연속적으로 도포되는 접착제와;상기 반도체 칩이 플립 칩 본딩된 상기 배선기판의 외곽에 부착되는 보강 링으로, 상기 배선기판에 플립 칩 본딩된 상기 반도체 칩 보다는 크게 개방부가 형성되어 있고, 상기 접착제가 도포된 영역에 대응되게 다수개의 구멍이 형성된 보강 링과;상기 반도체 칩의 후면에 형성된 열 매개 물질과;상기 구멍으로 올라온 접착제와 상기 열 매개 물질에 의해 상기 보강 링과 상기 반도체 칩에 부착되는 방열판; 및상기 배선기판의 하부면에 형성되며, 상기 반도체 칩과 전기적으로 연결되는 복수개의 외부접속단자;를 포함하는 것을 특징으로 하는 반도체 패키지.
- 제 1항에 있어서, 상기 보강 링은 상기 배선기판에 플립 칩 본딩된 반도체 칩의 두께에 대응되는 두께를 갖는 것을 특징으로 하는 반도체 패키지.
- 제 2항에 있어서, 상기 보강 링의 구멍은 상기 배선기판에 도포된 접착제의 면적보다는 작게 형성된 것을 특징으로 하는 반도체 패키지.
- 제 3항에 있어서, 상기 보강 링의 구멍은, "L"자, 일자, 원형 또는 타원형 형태로 형성되는 것을 특징으로 하는 반도체 패키지.
- (a) 상부면과, 상기 상부면에 반대되는 하부면을 갖는 배선기판을 준비하는 단계와;(b) 상기 배선기판의 상부면에 반도체 칩을 플립 칩 본딩하는 단계와;(c) 상기 배선기판 상부면의 가장자리 둘레에 불연속적으로 접착제를 도포하는 단계와;(d) 상기 배선기판에 플립 칩 본딩된 상기 반도체 칩보다는 크게 개방부가 형성되어 있고, 상기 접착제가 도포된 영역에 대응되게 다수개의 구멍이 형성된 보강 링을 상기 배선기판에 부착하는 단계와;(e) 상기 반도체 칩의 후면에 열 매개 물질을 도포하는 단계와;(f) 상기 구멍으로 올라온 접착제와 상기 열 매개 물질에 방열판을 부착하는 단계; 및(g) 상기 반도체 칩과 전기적으로 연결되는 복수개의 외부접속단자를 상기 배선기판의 하부면에 형성하는 단계;를 포함하는 것을 특징으로 하는 반도체 패키지 제조 방법.
- 제 5항에 있어서, 상기 (b) 단계 후에, 플립 칩 본딩된 부분을 에폭시 수지를 도포하여 언더필 방법으로 봉합하는 단계;를 더 포함하는 것을 특징으로 하는 반도체 패키지 제조 방법.
- 제 5항에 있어서, 상기 보강 링은 상기 배선기판에 플립 칩 본딩된 반도체 칩의 두께에 대응되는 두께를 갖는 것을 특징으로 하는 반도체 패키지 제조 방법.
- 제 5항에 있어서, 상기 보강 링의 구멍은 상기 배선기판에 도포된 접착제의 면적보다는 작게 형성된 것을 특징으로 하는 반도체 패키지 제조 방법.
- 제 8항에 있어서, 상기 보강 링의 구멍은, "L"자, 일자, 원형 또는 타원형 형태로 형성되는 것을 특징으로 하는 반도체 패키지 제조 방법.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0047910A KR100394809B1 (ko) | 2001-08-09 | 2001-08-09 | 반도체 패키지 및 그 제조 방법 |
US10/199,343 US7211889B2 (en) | 2001-08-09 | 2002-07-19 | Semiconductor package and method for manufacturing the same |
JP2002230875A JP2003068931A (ja) | 2001-08-09 | 2002-08-08 | 半導体パッケージ及びその製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0047910A KR100394809B1 (ko) | 2001-08-09 | 2001-08-09 | 반도체 패키지 및 그 제조 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20030013737A KR20030013737A (ko) | 2003-02-15 |
KR100394809B1 true KR100394809B1 (ko) | 2003-08-14 |
Family
ID=19713017
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR10-2001-0047910A KR100394809B1 (ko) | 2001-08-09 | 2001-08-09 | 반도체 패키지 및 그 제조 방법 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7211889B2 (ko) |
JP (1) | JP2003068931A (ko) |
KR (1) | KR100394809B1 (ko) |
Families Citing this family (38)
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US6825556B2 (en) * | 2002-10-15 | 2004-11-30 | Lsi Logic Corporation | Integrated circuit package design with non-orthogonal die cut out |
US7094966B2 (en) * | 2002-10-22 | 2006-08-22 | International Business Machines Corporation | Packaging integrated circuits with adhesive posts |
TWI315094B (en) * | 2003-04-25 | 2009-09-21 | Advanced Semiconductor Eng | Flip chip package |
TWI247395B (en) * | 2004-03-09 | 2006-01-11 | Siliconware Precision Industries Co Ltd | Semiconductor package with heatsink and method for fabricating the same and stiffener |
KR100765478B1 (ko) | 2005-08-12 | 2007-10-09 | 삼성전자주식회사 | 구멍이 형성된 테이프 배선기판과, 그를 이용한 테이프패키지 및 평판 표시 장치 |
US8174114B2 (en) * | 2005-12-15 | 2012-05-08 | Taiwan Semiconductor Manufacturing Go. Ltd. | Semiconductor package structure with constraint stiffener for cleaning and underfilling efficiency |
TWI309879B (en) * | 2006-08-21 | 2009-05-11 | Advanced Semiconductor Eng | Reinforced package and the stiffener thereof |
JP4846019B2 (ja) * | 2007-02-27 | 2011-12-28 | 富士通株式会社 | プリント基板ユニットおよび半導体パッケージ |
US20080237855A1 (en) * | 2007-03-28 | 2008-10-02 | Powertech Technology Inc. | Ball grid array package and its substrate |
JP5224784B2 (ja) * | 2007-11-08 | 2013-07-03 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
KR100963617B1 (ko) | 2007-11-30 | 2010-06-16 | 주식회사 하이닉스반도체 | 반도체 패키지 및 이의 제조 방법 |
US8017436B1 (en) | 2007-12-10 | 2011-09-13 | Amkor Technology, Inc. | Thin substrate fabrication method and structure |
US8952511B2 (en) * | 2007-12-18 | 2015-02-10 | Intel Corporation | Integrated circuit package having bottom-side stiffener |
US7605018B2 (en) * | 2008-01-04 | 2009-10-20 | Powertech Technology Inc. | Method for forming a die-attach layer during semiconductor packaging processes |
US7968999B2 (en) * | 2008-02-28 | 2011-06-28 | Lsi Corporation | Process of grounding heat spreader/stiffener to a flip chip package using solder and film adhesive |
US8259454B2 (en) * | 2008-04-14 | 2012-09-04 | General Electric Company | Interconnect structure including hybrid frame panel |
US8115303B2 (en) * | 2008-05-13 | 2012-02-14 | International Business Machines Corporation | Semiconductor package structures having liquid coolers integrated with first level chip package modules |
US20090321925A1 (en) * | 2008-06-30 | 2009-12-31 | Gealer Charles A | Injection molded metal ic package stiffener and package-to-package interconnect frame |
US7842541B1 (en) * | 2008-09-24 | 2010-11-30 | Amkor Technology, Inc. | Ultra thin package and fabrication method |
US20110084375A1 (en) * | 2009-10-13 | 2011-04-14 | Freescale Semiconductor, Inc | Semiconductor device package with integrated stand-off |
US8237275B2 (en) | 2010-06-21 | 2012-08-07 | Aeroflex Colorado Springs Inc. | Tungsten stiffener for flexible substrate assembly |
US8679900B2 (en) | 2011-12-14 | 2014-03-25 | Stats Chippac Ltd. | Integrated circuit packaging system with heat conduction and method of manufacture thereof |
US8786075B1 (en) * | 2012-04-27 | 2014-07-22 | Amkor Technology, Inc. | Electrical circuit with component-accommodating lid |
JP6036083B2 (ja) * | 2012-09-21 | 2016-11-30 | 株式会社ソシオネクスト | 半導体装置及びその製造方法並びに電子装置及びその製造方法 |
US9385091B2 (en) * | 2013-03-08 | 2016-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reinforcement structure and method for controlling warpage of chip mounted on substrate |
US10032692B2 (en) | 2013-03-12 | 2018-07-24 | Nvidia Corporation | Semiconductor package structure |
US9355966B2 (en) * | 2013-07-08 | 2016-05-31 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Substrate warpage control using external frame stiffener |
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US10020236B2 (en) * | 2014-03-14 | 2018-07-10 | Taiwan Semiconductar Manufacturing Campany | Dam for three-dimensional integrated circuit |
KR102243287B1 (ko) | 2014-10-15 | 2021-04-23 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
JP6728363B2 (ja) | 2016-01-07 | 2020-07-22 | ザイリンクス インコーポレイテッドXilinx Incorporated | 改良された補剛材を有する積層シリコンパッケージアセンブリ |
US10163816B2 (en) | 2016-06-13 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of chip package with lid |
WO2019066801A1 (en) * | 2017-09-27 | 2019-04-04 | Intel Corporation | INTEGRATED CIRCUIT BOXES WITH PATTERNED PROTECTIVE MATERIAL |
KR102419893B1 (ko) * | 2018-01-15 | 2022-07-12 | 삼성전자주식회사 | 보호 부재를 가지는 인쇄 회로 기판 및 이를 포함하는 반도체 패키지 제조 방법 |
WO2020045241A1 (ja) * | 2018-08-31 | 2020-03-05 | 富士フイルム株式会社 | 撮像ユニット及び撮像装置 |
KR20220007246A (ko) * | 2020-07-10 | 2022-01-18 | 삼성전자주식회사 | 반도체 패키지 |
KR20220008097A (ko) * | 2020-07-13 | 2022-01-20 | 삼성전자주식회사 | 반도체 패키지 |
US11699668B2 (en) * | 2021-05-12 | 2023-07-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device package having warpage control and method of forming the same |
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JP3219043B2 (ja) * | 1998-01-07 | 2001-10-15 | 日本電気株式会社 | 半導体装置のパッケージ方法および半導体装置 |
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2001
- 2001-08-09 KR KR10-2001-0047910A patent/KR100394809B1/ko active IP Right Grant
-
2002
- 2002-07-19 US US10/199,343 patent/US7211889B2/en not_active Expired - Lifetime
- 2002-08-08 JP JP2002230875A patent/JP2003068931A/ja active Pending
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JPH11177000A (ja) * | 1997-12-08 | 1999-07-02 | Sumitomo Corp | 集積回路チップを搭載した半導体基板を覆う放熱用成形板 |
JPH11284097A (ja) * | 1998-03-30 | 1999-10-15 | Fujitsu Ltd | 半導体装置 |
US6224711B1 (en) * | 1998-08-25 | 2001-05-01 | International Business Machines Corporation | Assembly process for flip chip package having a low stress chip and resulting structure |
JP2000150695A (ja) * | 1998-11-05 | 2000-05-30 | Internatl Business Mach Corp <Ibm> | 半導体装置 |
Also Published As
Publication number | Publication date |
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KR20030013737A (ko) | 2003-02-15 |
US7211889B2 (en) | 2007-05-01 |
US20030030140A1 (en) | 2003-02-13 |
JP2003068931A (ja) | 2003-03-07 |
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