KR100393363B1 - 반도체 장치 및 그 제조 방법 - Google Patents
반도체 장치 및 그 제조 방법 Download PDFInfo
- Publication number
- KR100393363B1 KR100393363B1 KR10-2000-0063931A KR20000063931A KR100393363B1 KR 100393363 B1 KR100393363 B1 KR 100393363B1 KR 20000063931 A KR20000063931 A KR 20000063931A KR 100393363 B1 KR100393363 B1 KR 100393363B1
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- KR
- South Korea
- Prior art keywords
- insulating layer
- semiconductor device
- stress relaxation
- wiring
- forming
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H01L23/293—Organic, e.g. plastic
- H01L23/295—Organic, e.g. plastic containing a filler
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/05005—Structure
- H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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Abstract
Description
노광 마스크 하부의 간극(㎛) | |||||
40 | 60 | 80 | 100 | ||
배선 폭(㎛) | 15 | × | × | × | × |
20 | ○ | × | × | × | |
25 | ○ | ○ | ○ | × | |
30 | ○ | ○ | ○ | ○ | |
40 | ○ | ○ | ○ | ○ | |
50 | ○ | ○ | ○ | ○ |
Claims (26)
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- 반도체 장치의 제조 방법에 있어서,웨이퍼 상에 형성된 전극 패드를 덮지 않는 영역에서, 또한 상기 웨이퍼의 제1 반도체 소자와 제2 반도체 소자에 걸치도록 상기 반도체 장치와 상기 반도체 장치가 실장된 기판 사이에 생기는 응력을 완화시키는 제1 절연층을 마스크를 이용하여 인쇄하여 형성하는 제1 공정과,상기 제1 절연층 상에 상기 전극 패드와 접속되는 배선을 형성하는 제2 공정과,상기 제1 절연층의 일부이며, 또한 상기 제1 반도체 소자와 상기 제2 반도체 소자 사이의 영역에 있는 부분을 제거하는 제3 공정과,상기 웨이퍼를 절단하는 제4 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제7항에 있어서, 상기 제3 공정과 상기 제4 공정 사이에, 상기 제1 절연층 상에 상기 배선과 전기적으로 접속되는 외부 접속 단자를 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 반도체 장치의 제조 방법에 있어서,웨이퍼 상에서 또한 반도체 소자의 중앙에 배열된 전극 패드를 덮지 않는 영역에서, 또한 상기 웨이퍼의 제1 반도체 소자와 제2 반도체 소자에 걸치도록 상기 반도체 장치와 상기 반도체 장치가 실장된 기판 사이에 생기는 응력을 완화시키는 제1 절연층을 마스크를 이용하여 인쇄하여 형성하는 제1 공정과,상기 제1 절연층 상에 상기 전극 패드와 접속되는 배선을 형성하는 제2 공정과,상기 제1 절연층의 일부이며, 또한 상기 제1 반도체 소자와 상기 제2 반도체 소자 사이의 영역에 있는 부분을 제거하는 제3 공정과,상기 제1 절연층 상에 상기 배선과 전기적으로 접속되는 외부 접속 단자를 형성하는 제4 공정과,상기 웨이퍼를 다이싱 라인을 따라 절단하는 제5 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제7항 또는 제9항에 있어서, 상기 제1 절연층의 일부를 제거하는 공정과 상기 웨이퍼를 절단하는 공정 사이에, 상기 제1 절연층 및 상기 배선을 덮는 제2 절연층을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제7항 또는 제9항에 있어서, 상기 제1 절연층의 일부를 제거하는 공정에 있어서, 상기 제1 절연층의 일부를 레이저 가공 혹은 기계 가공에 의해 제거하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제7항 또는 제9항에 있어서, 상기 제1 절연층의 일부를 제거하는 공정에서 제1 절단날을 이용하여 상기 제1 절연층의 일부를 제거하고, 상기 웨이퍼를 절단하는 공정에서는 상기 제1 절단날과는 다른 제2 절단날을 이용하여 상기 웨이퍼를 절단하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제7항 또는 제9항에 있어서, 상기 제1 절연층을 형성하는 공정에 있어서, 상기 웨이퍼의 인접하는 4개의 반도체 소자에 걸치도록 상기 제1 절연층을 인쇄하여 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제7항 또는 제9항에 있어서, 상기 제1 절연층을 형성하는 공정에 있어서, 상기 웨이퍼 상에 인접한 2열의 반도체 소자에 걸치도록 상기 제1 절연층을 인쇄하여 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제7항 또는 제9항에 있어서, 상기 제1 절연층을 형성하는 공정에 있어서, 입자를 함유하는 절연 재료를 인쇄하여 상기 제1 절연층을 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제15항에 있어서, 상기 제1 절연층을 형성하는 공정에 있어서, 상기 제1 절연층을 형성하는 절연 재료와 동일한 재료로 된 입자를 함유하는 절연 재료를 인쇄하여 상기 제1 절연층을 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제15항에 있어서, 상기 제1 절연층을 형성하는 공정에 있어서, 직경이 0 보다 크고 10 마이크로미터 이하인 입자를 갖는 절연 재료를 인쇄하여 상기 제1 절연층을 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제7항 또는 제9항에 있어서, 상기 제1 절연층을 형성하는 공정에 있어서, 상기 제1 절연층의 경사부와 상기 제1 절연층의 평탄부의 경계에, 팽창 부분을 갖는 제1 절연층을 인쇄하여 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제7항 또는 제9항에 있어서, 상기 제1 절연층을 형성하는 공정에 있어서, 막 두께가 35 내지 150 마이크로미터인 제1 절연층을 인쇄하여 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제7항 또는 제9항에 있어서, 상기 제1 절연층을 형성하는 공정에 있어서, 막 두께가 상기 반도체 소자의 막 두께의 1/20 내지 1/5인 제1 절연층을 인쇄하여 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제7항 또는 제9항에 있어서, 상기 제1 절연층을 형성하는 공정에 있어서, 상기 반도체 소자에 대하여 5% 내지 30%의 경사각을 갖는 제1 절연층을 인쇄하여 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제7항 또는 제9항에 있어서, 상기 제1 절연층을 형성하는 공정에 있어서, 상기 제1 절연층의 탄성률이 0.1 GPa 내지 10 GPa인 절연 재료를 사용하여 상기 제1 절연층을 인쇄하여 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제7항 또는 제9항에 있어서, 경화 온도가 섭씨 100도 내지 250도인 절연 재료를 인쇄하여, 경화시켜 상기 제1 절연층을 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제7항 또는 제9항에 있어서, 상기 제1 절연층을 형성하는 공정에 있어서, 유리 전이 온도가 섭씨 150도 내지 400도인 절연 재료를 사용하여 제1 절연층을 인쇄하여 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제7항 또는 제9항에 있어서, 상기 제1 절연층을 형성하는 공정에 있어서, 폴리이미드, 폴리아미드, 폴리아미드이미드, 에폭시, 페놀, 실리콘 중 어느 하나를 사용하여 제1 절연층을 인쇄하여 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제7항 또는 제9항에 있어서, 상기 제1 절연층의 일부를 제거하는 공정에 있어서, 상기 제1 절연층의 일부를 제거함으로써 형성되는 상기 제1 절연층의 경사각이, 인쇄시에 형성되는 제1 절연층의 경사각보다 크게 되도록 상기 제1 절연층의 일부를 제거하는 것을 특징으로 하는 반도체 장치의 제조 방법.
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