KR100390240B1 - 반도체소자의 제조방법 - Google Patents
반도체소자의 제조방법 Download PDFInfo
- Publication number
- KR100390240B1 KR100390240B1 KR10-2001-0035791A KR20010035791A KR100390240B1 KR 100390240 B1 KR100390240 B1 KR 100390240B1 KR 20010035791 A KR20010035791 A KR 20010035791A KR 100390240 B1 KR100390240 B1 KR 100390240B1
- Authority
- KR
- South Korea
- Prior art keywords
- insulating film
- device isolation
- region
- isolation insulating
- forming
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000002955 isolation Methods 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 13
- 150000004767 nitrides Chemical class 0.000 claims description 25
- 239000012535 impurity Substances 0.000 claims description 11
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 238000004140 cleaning Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000005406 washing Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Element Separation (AREA)
Abstract
Description
Claims (5)
- 반도체기판 상부에 패드산화막과 질화막의 적층구조를 형성하고, 소자분리마스크를 식각마스크로 상기 적층구조와 소정 두께의 반도체기판을 식각하여 질화막패턴, 패드산화막패턴 및 트렌치를 형성하는 공정과,상기 트렌치의 표면에 소정 두께의 열산화막을 형성하는 공정과,전체표면 상부에 매립절연막을 형성하는 공정과,상기 매립절연막을 평탄화시켜 상기 트렌치에 매립되는 소자분리절연막을 형성하는 공정과,상기 질화막패턴을 제거하는 공정과,상기 반도체기판에서 PMOS영역으로 예정되는 부분에 n형 불순물을 이온주입하여 n웰을 형성하는 공정과,상기 반도체기판에서 NMOS영역으로 예정되는 부분에 p형 불순물을 이온주입하여 p웰을 형성하는 공정과,상기 NMOS영역 내에 형성되어 있는 패드산화막패턴과 소자분리절연막의 소정 두께를 제거하여 상기 PMOS영역 내에 형성되어 있는 소자분리절연막과의 두께 차이를 제거하는 공정을 포함하는 반도체소자의 제조방법.
- 제 1 항에 있어서,상기 질화막은 1200 ∼ 3000Å 두께로 형성되는 것을 특징으로 하는 반도체소자의 제조방법.
- 제 1 항에 있어서,상기 매립절연막의 평탄화공정은 상기 질화막패턴을 식각장벽으로 사용하되, 상기 평탄화공정은 상기 질화막패턴은 750 ∼ 2000Å 두께가 잔류하도록 실시되는 것을 특징으로 하는 반도체소자의 제조방법.
- 제 1 항에 있어서,상기 n형 불순물은 포스포러스(phosphorus) 또는 아즈닉(arsenic)이고, p형 불순물은 보론(boron)인 것을 특징으로 하는 반도체소자의 제조방법.
- 제 1 항에 있어서,상기 NMOS영역 내의 소자분리절연막은 전면식각공정으로 제거되는 것을 특징으로 하는 반도체소자의 제조방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0035791A KR100390240B1 (ko) | 2001-06-22 | 2001-06-22 | 반도체소자의 제조방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0035791A KR100390240B1 (ko) | 2001-06-22 | 2001-06-22 | 반도체소자의 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20030000131A KR20030000131A (ko) | 2003-01-06 |
KR100390240B1 true KR100390240B1 (ko) | 2003-07-07 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR10-2001-0035791A KR100390240B1 (ko) | 2001-06-22 | 2001-06-22 | 반도체소자의 제조방법 |
Country Status (1)
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KR (1) | KR100390240B1 (ko) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19990061023A (ko) * | 1997-12-31 | 1999-07-26 | 김영환 | 반도체소자의 제조방법 |
US5960276A (en) * | 1998-09-28 | 1999-09-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Using an extra boron implant to improve the NMOS reverse narrow width effect in shallow trench isolation process |
US6150235A (en) * | 2000-01-24 | 2000-11-21 | Worldwide Semiconductor Manufacturing Corp. | Method of forming shallow trench isolation structures |
US6228726B1 (en) * | 2000-03-06 | 2001-05-08 | Taiwan Semiconductor Manufacturing Company | Method to suppress CMOS device latchup and improve interwell isolation |
-
2001
- 2001-06-22 KR KR10-2001-0035791A patent/KR100390240B1/ko active IP Right Grant
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19990061023A (ko) * | 1997-12-31 | 1999-07-26 | 김영환 | 반도체소자의 제조방법 |
US5960276A (en) * | 1998-09-28 | 1999-09-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Using an extra boron implant to improve the NMOS reverse narrow width effect in shallow trench isolation process |
US6150235A (en) * | 2000-01-24 | 2000-11-21 | Worldwide Semiconductor Manufacturing Corp. | Method of forming shallow trench isolation structures |
US6228726B1 (en) * | 2000-03-06 | 2001-05-08 | Taiwan Semiconductor Manufacturing Company | Method to suppress CMOS device latchup and improve interwell isolation |
Also Published As
Publication number | Publication date |
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KR20030000131A (ko) | 2003-01-06 |
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