KR100382538B1 - Method for manufacturing cmos device - Google Patents
Method for manufacturing cmos device Download PDFInfo
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- KR100382538B1 KR100382538B1 KR1019960068669A KR19960068669A KR100382538B1 KR 100382538 B1 KR100382538 B1 KR 100382538B1 KR 1019960068669 A KR1019960068669 A KR 1019960068669A KR 19960068669 A KR19960068669 A KR 19960068669A KR 100382538 B1 KR100382538 B1 KR 100382538B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 4
- 238000002955 isolation Methods 0.000 abstract description 3
- 239000002019 doping agent Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 43
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체소자에 관한 것으로 특히, 모스소자의 래치-업 특성 방지 및 소자분리에 적당한 씨모스소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a CMOS device suitable for preventing latch-up characteristics and separating a device.
이하에서, 첨부된 도면을 참조하여 종래 씨모스소자의 제조방법을 설명하기로 한다.Hereinafter, a method for manufacturing a conventional CMOS device will be described with reference to the accompanying drawings.
도 1a 내지 도 1c는 종래 씨모스소자의 제조공정 단면도이다.1A to 1C are cross-sectional views of a manufacturing process of a conventional CMOS device.
먼저, 도 1a에 나타낸 바와 같이 p형 반도체기판(1)에 통상의 이온주입 공정으로 p형 웰(2) 및 n형 웰(3)을 교대로 형성한후 상기 p형 웰(2) 및 n형 웰(3)의 계면에 필드산화막(4)을 형성한다.First, as shown in FIG. 1A, p-type wells 2 and n-type wells 3 are alternately formed in a p-type semiconductor substrate 1 by a conventional ion implantation process, and then the p-type wells 2 and n The field oxide film 4 is formed at the interface of the mold well 3.
도 1b에 나타낸 바와 같이 상기 필드산화막(4)을 포함한 기판전면에 게이트 산화막(5)과 폴리실리콘을 형성한후 선택적으로 패터닝(포토리소그래피공정 + 식각공정)하여 p형 및 n형 웰(2)(3)이 형성된 반도체기판(1)의 소정영역상에 게이트전극(6)을 형성한다.As shown in FIG. 1B, the gate oxide film 5 and the polysilicon are formed on the front surface of the substrate including the field oxide film 4, and then selectively patterned (photolithography process + etching process) to form the p-type and n-type wells 2. The gate electrode 6 is formed on a predetermined region of the semiconductor substrate 1 on which (3) is formed.
도 1c에 나타낸 바와 같이 p형 웰(2) 및 n형 웰(3)을 감광막(도시하지 않음)을 마스크로 이용하여 각 웰과 반대도전형의 불순물 이온을 교대로 주입하여 p형 웰(2)상의 게이트전극(3)양측 반도체기판(1)에는 n형 불순물 영역(7)을 형성하고, n형 웰(3)상의 게이트전극(3)양측 반도체기판(1)에는 p형 불순물 영역(8)을 형성하여 종래 씨모스소자를 제조하였다.As shown in FIG. 1C, p-type wells 2 and n-type wells 3 are used as photoresist films (not shown) as masks to alternately inject each well with impurity ions of an opposite conductivity type to form p-type wells 2. N-type impurity regions 7 are formed in the semiconductor substrate 1 on both sides of the gate electrode 3 on the gate electrode 3, and p-type impurity regions 8 are formed in the semiconductor substrate 1 on both sides of the gate electrode 3 on the n-type well 3. ) To form a conventional CMOS device.
종래의 씨모스소자의 제조방법에 있어서는 p형 모스의 소오스(p형)와 웰(n형)과 기판(p형)에서와 같이 pnp구조를 이룬 수직 기생 트랜지스터(vertical parasitic bipolar) 및 n형 모스의 소오스(n형)와 기판(p형)과 측면의 웰(n형)에서와 같이 npn구조를 이룬 수평 기생 트랜지스터(lateral parasitic bipolar)의 구조가 형성되어 주변회로로부터의 영향을 받거나(AC-coupling), 외부로부터의 캐리어생성에 영향을 받거나(α-입자, 빛), 혹은 인접 트랜지스터의 드레인쪽에 형성된 높은 전계에 의하여 캐리어가 생성될 경우에, 이들 캐리어가 npn 혹은 pnp 기생트랜지스터의 에미터-베이스 접합을 순방향으로 바이어스(bias)시킬 경우 일단 하나의 트랜지스터에 일정수준 이상의 전류가 흐르기 시작하면 이 전류는 상대편 트랜지스터의 베이스전류를 공급하여 상승작용을 일으키는 과정을 거치게되어 과다한 전류가 흐르는 온(on)상태에 돌입하게 되면 씨모스는 그 본래의 기능을 상실하게 되는 래치-업(latch-up)현상이 발생되는 문제점이 있었다. 그리고, 이와 같은 래치-업 현상을 방지하기 위한 방법으로 절연층상에 실리콘 단결정 박막을 형성하고 그 위에 소자를 형성하는 기술인 SOI(Silicon On Insulator)구조를 이용한 씨모스 소자의 제조방법이 있으나 제조공정 시간이 길고 생산비용이 추가되어야 한다는 문제점이 있다.In the conventional method of manufacturing a CMOS device, a vertical parasitic bipolar and an n-type MOS having a pnp structure as in a p-type source (p-type), a well (n-type) and a substrate (p-type) are formed. As in the source (n-type) and the substrate (p-type) and the side well (n-type), the structure of the lateral parasitic bipolar with npn structure is formed and is affected by the peripheral circuit (AC- coupling), carriers from external sources ( α -particles, light), or when the carriers are generated by high electric fields formed on the drain side of adjacent transistors, these carriers are emitters of npn or pnp parasitic transistors. When biasing the base junction in the forward direction, once a certain level of current begins to flow in one transistor, this current supplies the base current of the opposite transistor to cause synergy. If a is the in-rush on (on) excessive current flowing through the state undergoes a CMOS latch which lose their original function - there is a problem in that the up (latch-up) occurs. In addition, there is a method of manufacturing a CMOS device using a silicon on insulator (SOI) structure, which is a technique of forming a silicon single crystal thin film on an insulating layer and forming a device thereon as a method for preventing the latch-up phenomenon. There is a problem that this is long and the production cost must be added.
본 발명은 상기한 바와 같은 종래 씨모스소자 제조방법의 문제점을 해결하기 위하여 안출한 것으로 매립산화막과 트랜치를 이용하여 모스소자의 래치-업 특성 방지 및 소자분리특성 향상에 적당한 씨모스소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the conventional CMOS device manufacturing method as described above, a method of manufacturing a CMOS device suitable for preventing the latch-up characteristics of the MOSFET device and improving the device isolation characteristics by using a buried oxide film and a trench. The purpose is to provide.
도 1a 내지 도 1c는 종래 씨모스소자의 제조공정 단면도1A to 1C are cross-sectional views of a manufacturing process of a conventional CMOS device.
도 2a 내지 도 2I은 본 발명 씨모스소자의 제조공정 단면도2A to 2I are cross-sectional views of a manufacturing process of the CMOS device of the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
10 : 반도체기판 11 : 패드산화막10: semiconductor substrate 11: pad oxide film
12: 제 1 절연막 13 : 산화막12: first insulating film 13: oxide film
14 : 에피택셜층 15 : 트랜치14 epitaxial layer 15 trench
16 : 제 2 절연막 17 : 제 1 도전형 웰16 second insulating film 17 first conductivity type well
18 : 제 2 도전형 웰 19 : 게이트 산화막18: second conductivity type well 19: gate oxide film
20 : 게이트전극 21 : 제 1 도전형 불순물 영역20 gate electrode 21 first conductivity type impurity region
22 : 제 2 도전형 불순물 영역22: second conductivity type impurity region
본 발명에 따른 씨모스소자의 제조방법은 제 1 도전형 반도체기판상에 패드산화막을 형성하는 단계, 상기 패드산화막의 소정영역상에 제 1 절연막을 형성하는 단계, 상기 기판의 노출된 패드산화막을 성장시켜 산화막을 형성하는 단계, 상기 제 1 절연막과 제 1 절연막 아래의 패드산화막을 제거하는 단계, 상기 반도체기판을 포함한 산화막 전면에 에피택셜층을 형성하는 단계, 상기 에피택셜층을 선택적으로 제거하여 상기 산화막을 부분적으로 노출시키는 트랜치를 형성하는 단계, 상기 트랜치에 제 2 절연막을 형성하는 단계, 상기 제 2 절연막의 양측 에피택셜층에 선택적인 이온주입공정으로 제 1, 제 2 도전형 웰을 형성하는 단계, 상기 에피택셜층 소정영역상에 게이트전극을 형성하는 단계, 상기 게이트전극 양 측면 제 1, 제 2 도전형 웰에 상기 제 1, 제 2 도전형 웰과 반대도전형의 불순물영역을 형성하는 단계를 포함한다.According to the present invention, a method of manufacturing a CMOS device includes forming a pad oxide film on a first conductive semiconductor substrate, forming a first insulating film on a predetermined region of the pad oxide film, and exposing the exposed pad oxide film of the substrate. Growing to form an oxide film, removing the pad oxide film under the first insulating film and the first insulating film, forming an epitaxial layer on the entire surface of the oxide film including the semiconductor substrate, and selectively removing the epitaxial layer. Forming a trench that partially exposes the oxide film, forming a second insulating film in the trench, and forming first and second conductivity wells by an ion implantation process on both epitaxial layers of the second insulating film. Forming a gate electrode on a predetermined region of the epitaxial layer; and forming a gate electrode on the first and second conductive wells on both sides of the gate electrode. And forming an impurity region of opposite conductivity type to the second conductivity type well.
이와 같은 본 발명 씨모스소자의 제조방법을 첨부된 도면을 참조하여 설명하기로 한다.Such a method of manufacturing the CMOS device will be described with reference to the accompanying drawings.
도 2a 내지 도 2l은 본 발명 씨모스소자의 제조공정 단면도이다.2A to 2L are cross-sectional views of a manufacturing process of the CMOS device of the present invention.
먼저, 도 2a에 나타낸 바와 같이, 제 1 도전형의 반도체기판(10)상에 패드산화막(11)을 형성한다.First, as shown in FIG. 2A, a pad oxide film 11 is formed on the first conductive semiconductor substrate 10.
도 2b에 나타낸 바와 같이, 상기 패드산화막(11)의 소정영역에 일정간격으로 제 1 절연막(12)을 형성한다. 이때, 상기 제 1 절연막(12)은 패드산화막(11)과 식각선택비가 다른 물질을 사용하여 형성하며 바람직하게는 질화막으로 형성한다.As shown in FIG. 2B, the first insulating film 12 is formed in a predetermined region of the pad oxide film 11 at a predetermined interval. In this case, the first insulating film 12 is formed using a material having a different etching selectivity from the pad oxide film 11, and preferably formed of a nitride film.
도 2c에 나타낸 바와 같이, 상기 절연막(12)에 마스킹되지 않은 패드산화막(11)을 일정높이로 성장시켜 산화막(13)을 형성한다.As shown in FIG. 2C, an oxide film 13 is formed by growing an unmasked pad oxide film 11 to a predetermined height.
도 2d에 나타낸 바와 같이, 상기 절연막(12) 및 절연막(12)하부의 패드산화막(11)을 제거한다. 그다음, 불산(HF)을 이용하여 전면을 세척한다.As shown in FIG. 2D, the insulating film 12 and the pad oxide film 11 under the insulating film 12 are removed. The front is then washed with hydrofluoric acid (HF).
도 2e에 나타낸 바와 같이, 상기 산화막(13)을 포함한 반도체기판(10) 전면에 비정질실리콘을 형성한후 어닐링(annealing)하여 에피택셜층(14)을 형성하여 상기 산화막(13)을 매몰시킨다.As shown in FIG. 2E, amorphous silicon is formed on the entire surface of the semiconductor substrate 10 including the oxide film 13, and then annealed to form an epitaxial layer 14 to bury the oxide film 13.
도 2f에 나타낸 바와 같이, 상기 에피택셜층(14)을 선택적으로 패터닝하여(포토리소그래피공정 + 식각공정)하여 상기 산화막(13)이 부분적으로 노출되는 트랜치(15)를 형성한다.As shown in FIG. 2F, the epitaxial layer 14 is selectively patterned (a photolithography process + an etching process) to form a trench 15 in which the oxide layer 13 is partially exposed.
도 2g에 나타낸 바와 같이, 상기 트랜치(15)를 포함한 에피택셜층(14)전면에 CVD 산화막(16)을 형성한다.As shown in FIG. 2G, a CVD oxide film 16 is formed on the entire surface of the epitaxial layer 14 including the trench 15.
도 2h에 나타낸 바와 같이, 상기 CVD 산화막(16)을 에치백하여 트랜치(15)내에만 남긴다.As shown in FIG. 2H, the CVD oxide film 16 is etched back and remains only in the trench 15. As shown in FIG.
도 2i에 나타낸 바와 같이, 상기 CVD 산화막(16)을 포함한 에피택셜층(14)전면에 제 1 감광막(PR1)을 형성한후 트랜치(15)일측의 에피택셜층(14)만 노출되도록 선택적으로 패터닝한다. 그다음, 상기 노출된 에피택셜층(14)에 제 1 도전형 불순물 이온을 주입하여 제 1 도전형 웰(17)을 형성한다.As shown in FIG. 2I, after the first photosensitive film PR1 is formed on the entire surface of the epitaxial layer 14 including the CVD oxide layer 16, the epitaxial layer 14 on one side of the trench 15 is selectively exposed. Pattern. Thereafter, a first conductivity type impurity ion is implanted into the exposed epitaxial layer 14 to form a first conductivity type well 17.
도 2j에 나타낸 바와 같이, 상기 제 1 감광막(PR1)을 제거한후 전면에 제 2 감광막(PR2)을 형성한다음 제 1 도전형 웰(17) 형성영역에만 상기 제 2 감광막(PR2)이 남도록 패터닝한다. 그다음, 상기 노출된 에피택셜층(14)에 제 2 도전형 불순물 이온을 주입하여 제 2 도전형 웰(18)을 형성한다.As shown in Fig. 2j, the first photoresist (PR 1) to the front after removing form the second photoresist layer (PR 2), and then the first conductivity type well (17) forming region only the second photoresist layer (PR 2) Pattern this to remain. Next, a second conductivity type impurity ion is implanted into the exposed epitaxial layer 14 to form a second conductivity type well 18.
도 2k에 나타낸 바와 같이, 상기 제 2 감광막(PR2)물 제거한후 상기 격리용 CVD 산화막(16)을 포함한 기판전면에 게이트 산화막(19) 및 게이트용 폴리실리콘을차례로 형성한다음 상기 게이트용 폴리실리콘을 선택적으로 패터닝하여 게이트전극(20)을 형성한다.As shown in FIG. 2K, after the second photoresist film PR 2 is removed, the gate oxide film 19 and the gate polysilicon are sequentially formed on the front surface of the substrate including the isolation CVD oxide film 16. Silicon is selectively patterned to form the gate electrode 20.
도 2l에 나타낸 바와 같이, 상기 게이트전극(20)을 마스크로 이용한 이온주입공정으로 게이트전극(20)양측면의 제 1, 제 2 도전형 웰(17)(18)에 각 도전형 웰과 반대도전형의 불순물 영역인 제 1 도전형 불순물 영역(21)과 제 2 도전형 불순물 영역(22)을 형성한다.As shown in FIG. 2L, the first and second conductive wells 17 and 18 on both sides of the gate electrode 20 are opposite to the respective conductive wells by an ion implantation process using the gate electrode 20 as a mask. The first conductivity type impurity region 21 and the second conductivity type impurity region 22 which are typical impurity regions are formed.
본 발명에 따른 씨모스소자의 제조방법에 있어서는 다음과 같은 효과가 있다.The manufacturing method of the CMOS device according to the present invention has the following effects.
첫째, 제 1, 제 2 도전형 웰이 매몰산화막위에 형성되어 기생 바이폴라 트랜지스터에 의한 래치-업을 막을 수 있다.First, first and second conductivity wells may be formed on the buried oxide film to prevent latch-up by parasitic bipolar transistors.
둘째, 제 1, 제 2 도전형 웰이 CVD 산화막에 의해 차단되므로 웰 정션 브레이크다운이 발생하지 않고 소자의 집적도를 향상시킬수 있다.Second, since the first and second conductivity type wells are blocked by the CVD oxide film, well junction breakdown does not occur, and thus the integration degree of the device can be improved.
Claims (5)
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| US11404270B2 (en) * | 2018-11-30 | 2022-08-02 | Texas Instruments Incorporated | Microelectronic device substrate formed by additive process |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR840005927A (en) * | 1982-08-13 | 1984-11-19 | 미쓰다 가쓰시게 | Semiconductor integrated circuit device and manufacturing method thereof |
| JPH02234461A (en) * | 1989-03-08 | 1990-09-17 | Hitachi Ltd | Semiconductor device |
| KR910008808A (en) * | 1989-10-25 | 1991-05-31 | 문정환 | Manufacturing method of bipolar-semos to prevent the latch-up phenomenon |
| KR920020722A (en) * | 1991-04-30 | 1992-11-21 | 문정환 | Latch-up prevention structure of two-win well CMOS |
| JPH07176692A (en) * | 1993-12-17 | 1995-07-14 | Fuji Electric Co Ltd | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR840005927A (en) * | 1982-08-13 | 1984-11-19 | 미쓰다 가쓰시게 | Semiconductor integrated circuit device and manufacturing method thereof |
| JPH02234461A (en) * | 1989-03-08 | 1990-09-17 | Hitachi Ltd | Semiconductor device |
| KR910008808A (en) * | 1989-10-25 | 1991-05-31 | 문정환 | Manufacturing method of bipolar-semos to prevent the latch-up phenomenon |
| KR920020722A (en) * | 1991-04-30 | 1992-11-21 | 문정환 | Latch-up prevention structure of two-win well CMOS |
| JPH07176692A (en) * | 1993-12-17 | 1995-07-14 | Fuji Electric Co Ltd | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11404270B2 (en) * | 2018-11-30 | 2022-08-02 | Texas Instruments Incorporated | Microelectronic device substrate formed by additive process |
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