KR100378197B1 - Method for suppressing degration of surface morphology property of metal layer and method for manufacturing semiconductor device having metal layer resulted from the same - Google Patents
Method for suppressing degration of surface morphology property of metal layer and method for manufacturing semiconductor device having metal layer resulted from the same Download PDFInfo
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- KR100378197B1 KR100378197B1 KR10-2001-0018961A KR20010018961A KR100378197B1 KR 100378197 B1 KR100378197 B1 KR 100378197B1 KR 20010018961 A KR20010018961 A KR 20010018961A KR 100378197 B1 KR100378197 B1 KR 100378197B1
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Abstract
금속층의 증착 후 산소 분위기에서의 열공정을 진행하기 이전에, 상기 열공정보다 낮은 온도에서 금속층을 산소 성분은 포함하되 아르곤 성분이 배제된 플라즈마 등에 노출시켜, 금속층의 상단에 금속-산소 성분의 혼합상을 형성한다. 금속-산소의 혼합상에 의해 후속 열공정에 의한 금속 산화물의 생성이 억제되어, 금속층의 표면 거칠기 및 모폴로지 특성을 개선할 수 있다.After the deposition of the metal layer and before the thermal process in the oxygen atmosphere, at a lower temperature than the thermal process, the metal layer is exposed to a plasma containing oxygen but excludes argon, thereby mixing the metal-oxygen component on the top of the metal layer. Form the phase. The metal-oxygen mixed phase can suppress the generation of metal oxides by subsequent thermal processes, thereby improving the surface roughness and morphology properties of the metal layer.
Description
본 발명은 열적 산화에 의한 표면 모폴로지의 변화가 억제된 금속층의 제조 방법 및 그러한 금속층을 가지는 반도체 장치의 제조 방법에 관한 것이다.The present invention relates to a method for producing a metal layer in which a change in surface morphology due to thermal oxidation is suppressed, and a method for producing a semiconductor device having such a metal layer.
반도체 장치에서는 절연층과 도전층이 수직 및 수평 방향으로 일정한 룰에 의해 배치되어 있으며, 이러한 배치에 의해, 트랜지스터, 캐패시터, 배선층 및 배선층을 연결하는 플러그 등의 소자가 형성되어 있다. 그런데, 일부의 반도체 소자에서 어느 하나가 먼저 형성되고 그 상부에 다른 소자가 형성되므로, 뒤에 형성되는 소자의 형성 공정에 의해 앞에 형성된 소자의 전기적 특성이 변화되고 열화되는 경우가 있다.In a semiconductor device, an insulating layer and a conductive layer are arranged by a predetermined rule in the vertical and horizontal directions, whereby elements such as a transistor, a capacitor, a wiring layer, and a plug connecting the wiring layer are formed. By the way, since some of the semiconductor elements are formed first and other elements are formed thereon, the electrical characteristics of the former elements may be changed and deteriorated by the formation process of the elements formed later.
후속 공정에 의한 소자의 특성 변화의 일예는 캐패시터에서 찾아 볼 수 있다. 통상 캐패시터를 제조하기 위해서는, 먼저 기판 상에 도전물질로 이루어진 하부 전극을 형성하고, 이어 그 상부에 유전막을 형성한다. 유전막 상에 상부 전극을 형성하기 이전에 유전막을 결정화시켜 캐패시터의 유전특성을 증가시키기 위해 약 700℃에서 어닐링을 실시한다. 다음, 도전물질로 이루어진 상부 전극을 형성한다. 그리고 캐패시터 형성 이후에 700℃의 결정화 어닐링에 의한 누설 전류를 감소시키기 위해 약 400℃ 및 산소 분위기에서 큐어링을 실시한다.An example of the characteristic change of the device by the subsequent process can be found in the capacitor. In general, in order to manufacture a capacitor, a lower electrode made of a conductive material is first formed on a substrate, and then a dielectric film is formed thereon. Prior to forming the upper electrode on the dielectric film, the dielectric film is crystallized to anneal at about 700 ° C. to increase the dielectric properties of the capacitor. Next, an upper electrode made of a conductive material is formed. After the formation of the capacitor, curing is performed at about 400 ° C. and in an oxygen atmosphere to reduce leakage current due to crystallization annealing at 700 ° C.
종래에는 하부 전극용 도전 물질로 반도체인 폴리 실리콘을 사용하고 상부 전극용 도전 물질로 금속을 사용한 MIS(Metal-Insulator-Semiconductor) 캐패시터가 주류를 이루었으나, 집적도의 증가에 따라 하부 전극 및 상부 전극을 금속으로 형성하는 MIM(Metal-Insulator-Metal)캐패시터의 사용이 증가하고 있다. 최근에는, 유전막과의 반응이 없고 일함수 값이 높은 Pt, Ru, Ir, Rh, Os와 같은 귀금속이 캐패시터의 상부 및/또는 하부 전극으로 사용되고 있다.Conventionally, MIS (Metal-Insulator-Semiconductor) capacitors, which use polysilicon as the lower electrode conductive material and metal as the upper electrode conductive material, have become mainstream, but as the degree of integration increases, the lower electrode and the upper electrode The use of metal-insulator-metal (MIM) capacitors formed of metal is increasing. Recently, precious metals such as Pt, Ru, Ir, Rh, Os, which have no reaction with the dielectric film and have a high work function, are used as the upper and / or lower electrodes of the capacitor.
이들 중, Pt는 산소와의 반응성이 거의 없어 산화계인 유전체막과의 계면에서 산화화합물을 형성하지 않으며 유전체 특성을 향상시키기 위한 결정화 어닐링 및 큐어링 처리가 행해지는 산소 분위기의 고온 열공정에서도 표면이 산화되지 않는 특성을 가지고 있다. 그러나, Ru, Ir, Pd, Rh 또는 Os등은 결정화 어닐링 및/또는 큐어링 공정 조건에서 그 표면이 쉽게 산화되므로, 부피가 팽창된 금속 산화물이 형성되고 그에 따라 표면 거칠기가 증가하며 표면 모폴로지가 변하고, 큐어링에 의한 금속층으로의 산소 확산이 방해되는 문제가 있다. 따라서, 유전막의 절연/누설전류 특성을 향상시키기 위한 산소 분위기에서의 열공정이 제한을 받게 되고, 특히 상부 전극과 유전막의 계면 특성을 향상시키기 위한 큐어링 공정을 400℃이상에서 실시하는 것이 곤란하게 되었다.Among them, Pt has little reactivity with oxygen and thus does not form an oxidizing compound at an interface with an oxide-based dielectric film, and the surface is not subjected to crystallization annealing and curing in order to improve dielectric properties. It does not oxidize. However, since Ru, Ir, Pd, Rh or Os are easily oxidized at the surface of the crystallization annealing and / or curing process conditions, a volume-expanded metal oxide is formed, thereby increasing the surface roughness and changing the surface morphology. , There is a problem that oxygen diffusion into the metal layer by curing is prevented. Therefore, the thermal process in the oxygen atmosphere for improving the insulation / leakage current characteristics of the dielectric film is limited, and in particular, it becomes difficult to perform the curing process for improving the interfacial properties of the upper electrode and the dielectric film at 400 ° C or higher. .
한편, 집적도의 증가에 따라 캐패시터의 전극의 두께도 얇아지게 되어, 종래에는 산화가 일어나지 않던 온도 조건에서도 금속 산화물이 형성된다. 예를 들면 1000Å두께의 루테늄막을 400℃의 산소분위기에서 열처리(큐어링) 한 후의 상태를 촬영한 사진이 도 1a에 나타나 있고, 루테늄막이 300Å이고 동일한 온도에서 열처리(큐어링)를 한 경우의 상태를 촬영한 사진이 도 1b에 나타나 있다. 도 1a 및 도 1b에 나타난 바와 같이, 막의 두께가 얇아지면 동일한 온도에서도 표면 거칠기가증가하고 표면 모폴로지가 변하게 되어 막의 저항값 및 캐패시터 누설 전류값이 증가하게 된다. 이는 도 2에 도시된 것과 같이, 열산화에 의해 루테늄막(1)의 표면에 RuO2로 이루어진 혹(2)이 형성되기 때문이다.On the other hand, as the degree of integration increases, the thickness of the electrode of the capacitor also becomes thin, and metal oxide is formed even at a temperature condition in which oxidation does not occur conventionally. For example, a photograph photographing a state after heat treatment (cure) of a ruthenium film having a thickness of 1000 μs in an oxygen atmosphere at 400 ° C. is shown in FIG. 1A, and a state when the heat treatment (cure) at a same temperature is performed at 300 ° C. A photo taken is shown in FIG. 1B. As shown in FIGS. 1A and 1B, when the thickness of the film becomes thinner, the surface roughness increases and the surface morphology changes even at the same temperature, thereby increasing the resistance value and the capacitor leakage current value of the film. This is because, as shown in Fig. 2, a lump 2 made of RuO 2 is formed on the surface of the ruthenium film 1 by thermal oxidation.
따라서, Ru, Ir, Pd, Rh 또는 Os 등의 금속을 캐패시터의 전극으로 사용하면서 원하는 누설 전류 값과 저항값을 얻기 위해서는, 이들 금속의 표면에 열산화막이 형성되는 것을 억제할 수 있는 기술이 요구된다.Therefore, in order to obtain a desired leakage current value and resistance value while using a metal such as Ru, Ir, Pd, Rh or Os as the electrode of the capacitor, a technique capable of suppressing the formation of a thermal oxide film on the surface of these metals is required. do.
본 발명이 이루고자 하는 기술적 과제는 열공정에 의한 금속 산화막의 형성을 억제할 수 있는 금속층의 제조 방법 및 그러한 금속층을 포함하는 반도체 장치의 제조 방법을 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method for producing a metal layer capable of suppressing the formation of a metal oxide film by a thermal process, and a method for manufacturing a semiconductor device including such a metal layer.
도 1a와 도 1b는 두께 변화에 따른 루테늄막의 표면 모폴로지를 보여주는 주사 전자 현미경 촬영 사진들이다.1A and 1B are scanning electron micrographs showing the surface morphology of the ruthenium film according to the thickness change.
도 2는 종래의 산소 열처리에 따라 형성된 루테늄막 상에 형성된 RuO2로 이루어진 혹을 보여주는 도면이다.FIG. 2 is a view showing a bump formed of RuO 2 formed on a ruthenium film formed by a conventional oxygen heat treatment.
도 3a 내지 도 3c는 본 발명의 2 단계 열처리에 따른 금속층 형성 방법을 보여주는 도면들이다.3A to 3C are views illustrating a metal layer forming method according to a two-step heat treatment of the present invention.
도 4a 내지 도 4e는 본 발명의 사상을 적용하되 플라즈마 어닐 시간의 변화에 따른 루테늄막의 표면 모폴로지 상태를 보여주는 주사 전자 현미경 촬영 사진들이다.4A to 4E are scanning electron micrographs showing the state of the surface morphology of the ruthenium film according to the change of the plasma annealing time while applying the idea of the present invention.
도 5는 도 4d의 루테늄막의 표면을 엑스선 회절 분석법으로 분석한 결과를 보여주는 그래프이다.FIG. 5 is a graph showing the results of analyzing the surface of the ruthenium film of FIG. 4D by X-ray diffraction analysis.
도 6은 RuO2를 엑스선 회절 분석법으로 분석한 결과를 보여주는 그래프이다.6 is a graph showing the results of analyzing RuO 2 by X-ray diffraction analysis.
본 발명이 이루고자 하는 기술적 과제를 달성하기 위해, 반도체 기판 상에 금속층을 형성하고, 금속층을 제 1 온도로, 예를 들면 약 150℃에서 저온 산화시켜 금속층의 표면을 금속층을 이루는 금속과 산소의 혼합상이 포함되게 변환시킨다. 다음, 산소 분위기에서 금속-산소 혼합상을 갖는 금속층을 제 1 온도보다 높은 제 2 온도로, 예를 들면 약 400℃에서 열처리한다. 특히 저온 산화 공정의 하나로, 산소 성분을 포함하되(질소 성분이 추가될 수도 있음) 아르곤 성분은 포함하지 않는 플라즈마에 금속층을 노출시키거나, 금속층을 오존 또는 H2O처리한다. 이러한 금속층은 Ru, Ir, Rh, Pd, Os 및 이들의 결합물로 이루어진 군에서 선택된 어느 하나로이루어질 수 있다. 한편, 산소 성분을 포함하되 아르곤 성분이 배제된 플라즈마는 He와 산소의 혼합 가스, N2와 산소의 혼합 가스, N2O, NO 또는 NO2가스를 사용하거나 이들 중의 한 가지 이상의 혼합 가스를 포함할 수 있다.In order to achieve the technical problem to be achieved by the present invention, a metal layer is formed on a semiconductor substrate, and the metal layer is oxidized at a low temperature at a first temperature, for example, at about 150 ° C. to mix the metal and oxygen forming the metal layer on the surface of the metal layer. Convert the image to be included. Next, the metal layer having the metal-oxygen mixed phase in an oxygen atmosphere is heat-treated at a second temperature higher than the first temperature, for example, at about 400 ° C. In particular, one of the low-temperature oxidation processes, the metal layer is exposed to a plasma containing an oxygen component (which may be added a nitrogen component) but not an argon component, or the metal layer is ozone or H 2 O treated. The metal layer may be made of any one selected from the group consisting of Ru, Ir, Rh, Pd, Os, and combinations thereof. On the other hand, the plasma including the oxygen component, but excludes the argon component, uses a mixed gas of He and oxygen, a mixed gas of N 2 and oxygen, N 2 O, NO or NO 2 gas or include one or more of them can do.
한편, 금속층이 캐패시터의 상부 전극인 경우에는 금속층 하부에 유전막을 형성하는단계를 더 구비한다. 금속층은 Ru, Ir, Rh, Pd, Os 및 이들의 결합물로 이루어진 군에서 선택된 어느 하나로 이루어진다. 금속층이 Ru인 경우 Ru는 산소와 질소가 포함되되 아르곤성분이 배제된 플라즈마에 약 300초 이상 노출되고 400℃이상에서 열처리될 수 있다. 한편, 유전막으로는 Ta2O5, SrTiO3(STO), (Ba, Sr)TiO3(BST), PbTiO3, Pb(Zr,Ti)O3(PZT), SrBi2Ta2O5(SBT), (Pb, La)(Zr, Ti)O3, Bi4Ti3O12및 BaTiO3(BTO)로 이루어진 군에서 어느 하나를 선택한다.On the other hand, when the metal layer is the upper electrode of the capacitor further comprises forming a dielectric film under the metal layer. The metal layer is made of any one selected from the group consisting of Ru, Ir, Rh, Pd, Os, and combinations thereof. When the metal layer is Ru, Ru may be exposed to a plasma containing oxygen and nitrogen but not including argon, for about 300 seconds or more, and heat-treated at 400 ° C. or more. On the other hand, as the dielectric film, Ta 2 O 5 , SrTiO 3 (STO), (Ba, Sr) TiO 3 (BST), PbTiO 3 , Pb (Zr, Ti) O 3 (PZT), SrBi 2 Ta 2 O 5 (SBT ), (Pb, La) (Zr, Ti) O 3 , Bi 4 Ti 3 O 12 And BaTiO 3 (BTO) is selected from the group consisting of.
이하에서는 본원 발명을 도면을 참조로 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the drawings.
본 발명에서는 금속층의 증착 후 행해지는 열처리 공정을, 상대적으로 저온상태에서 실시하는 전처리공정과 상대적으로 고온 상태에서 실시하는 주처리공정으로 구성된 2단계로 실시하여, 금속층 표면에 산화물이 생성되는 것을 억제한다.In the present invention, the heat treatment process performed after the deposition of the metal layer is carried out in two stages consisting of a pretreatment process performed at a relatively low temperature state and a main treatment process performed at a relatively high temperature state, thereby suppressing generation of oxide on the surface of the metal layer. do.
도 3a에서 반도체 기판(도시되지 않음) 상에 형성된 절연층(3) 상에 금속층(4)을 형성한다. 금속층(4)의 두께는 반도체 장치의 집적화에 따라 박막화되는 추세에 있으므로, 금속층(4)은 화학기상증착법을 사용하여 형성한다.In FIG. 3A, a metal layer 4 is formed on an insulating layer 3 formed on a semiconductor substrate (not shown). Since the thickness of the metal layer 4 tends to become thin with the integration of a semiconductor device, the metal layer 4 is formed using chemical vapor deposition.
도 3b에서, 금속층(4)을 저온 산화시킨다. 저온 산화란, 이후에 형성되는 큐어링 시의 산화에 비해 낮은 온도에서 실시되는 산화를 의미한다. 저온 산화의 방법으로, 산소 성분을 포함하되 아르곤 성분이 제외된 플라즈마에 금속층을 소정 시간 노출시켜 금속층(4)의 상단을 산소와 금속의 혼합상으로 이루어진 부분(5)으로 변환시킨다. 저온 산화의 방법으로 플라즈마 이외에 오존 또는 H2O 처리를 행할 수 있다. 산소 성분을 포함하되 아르곤 성분이 배제된 플라즈마는 He와 산소의 혼합 가스, N2와 산소의 혼합 가스, N2O, NO 또는 NO2가스를 사용하거나 이들 중의 한 가지 이상의 혼합 가스를 포함할 수 있다.In FIG. 3B, the metal layer 4 is oxidized at low temperature. By low temperature oxidation is meant oxidation carried out at a lower temperature compared to the oxidation at the time of subsequent curing. By the method of low temperature oxidation, a metal layer is exposed to a plasma containing oxygen but not argon for a predetermined time to convert the upper end of the metal layer 4 into a portion 5 composed of a mixed phase of oxygen and metal. In addition to plasma, ozone or H 2 O treatment can be performed by low temperature oxidation. Plasma that includes an oxygen component but excludes argon may use a mixed gas of He and oxygen, a mixed gas of N 2 and oxygen, N 2 O, NO, or NO 2 gas, or include a mixed gas of one or more of them. have.
도 3c에서는 금속층(4a)과 그 하부의 절연층(3)과의 계면 특성을 향상시키기 위해 금속층(4a+5)을 산소 분위기에서 큐어링을 위한 열처리를 실시한다. 큐어링 온도는 저온 산화를 위한 온도 보다 높다. 금속층의 상단(5)의 성분은 큐어링에 의해 산화되지 않으므로, 상단(5) 표면에는 금속 산화물이 형성되지 않는다.In FIG. 3C, heat treatment for curing the metal layer 4a + 5 in an oxygen atmosphere is performed to improve the interfacial property between the metal layer 4a and the insulating layer 3 below. The curing temperature is higher than the temperature for low temperature oxidation. Since the components of the top 5 of the metal layer are not oxidized by curing, no metal oxide is formed on the top 5 surface.
금속층으로는 Ru, Ir, Rh, Pd, Os 또는 이들의 결합물로 이루어진 금속을 사용할 수 있다. 한편, 전술한 Ru을 포함한 Ir, Rh, Pd, Os 또는 이들의 결합물로 이루어진 금속을 캐패시터의 상부 전극으로 사용할 경우에는, 금속층 하부의 절연막은 BST 외에 Ta2O5, SrTiO3(STO), PbTiO3, Pb(Zr,Ti)O3(PZT), SrBi2Ta2O5(SBT), (Pb, La)(Zr, Ti)O3, Bi4Ti3O12및 BaTiO3(BTO)로 이루어진 군에서 어느 하나가 사용될 수 있다.As the metal layer, a metal made of Ru, Ir, Rh, Pd, Os, or a combination thereof may be used. On the other hand, when using a metal made of Ir, Rh, Pd, Os or a combination thereof including Ru as the upper electrode of the capacitor, the insulating film under the metal layer is Ta 2 O 5 , SrTiO 3 (STO), PbTiO 3 , Pb (Zr, Ti) O 3 (PZT), SrBi 2 Ta 2 O 5 (SBT), (Pb, La) (Zr, Ti) O 3 , Bi 4 Ti 3 O 12 and BaTiO 3 (BTO) Any one from the group consisting of can be used.
저온 산화를 위한 온도와 큐어링 온도는 사용되는 금속의 종류와 금속층의 두께, 금속층 하부의 절연막의 종류와 두께 또는 그밖의 공정 조건에 따라 다양하게 결정될 수 있다.The temperature and curing temperature for low temperature oxidation may vary depending on the type of metal used and the thickness of the metal layer, the type and thickness of the insulating film under the metal layer, or other processing conditions.
본 발명의 사상을 300Å Ru에 적용한 결과가 도 4a 내지 도 4d 및 도 5에 나타나 있다.The results of applying the idea of the present invention to 300 kHz Ru are shown in FIGS. 4A-4D and FIG. 5.
먼저 300Å의 Ru막을 BaxSr(1-x)TiO3(BST) 상에 형성하고, Ru막을 150℃에서 50, 100, 200, 300 및 400초 동안 O2(5%)와 N2(95%)의 플라즈마에 노출시켜 저온 산화시키고 400℃의 산소 분위기에서 큐어링 열처리를 행한 결과가 도 4a 내지 도 4e에 각각 나타나 있다. 도 4a 내지 도 4e에 나타난 바와 같이, 플라즈마 처리 시간이 길어질수록 표면 거칠기가 개선됨을 알 수 있다. 특히 300초 이상(도 4d 및 도 4e)일 경우에는 Ru의 표면 모폴로지가 변하지 않음을 알 수 있다. 이는 Ru 상단에 플라즈마 처리에 의해 내산화성이 강한 Ru-O혼합상이 균일하게 형성되어지며, 이러한 Ru-O혼합상이 이후에 실시되는 큐어링시에 RuO2가 생성되는 것을 억제하는 것으로 생각된다.First, a 300 Å Ru film is formed on Ba x Sr (1-x) TiO 3 (BST), and the Ru film is O 2 (5%) and N 2 (95) at 50 ° C. for 50, 100, 200, 300 and 400 seconds. %) And the low temperature oxidation and curing treatment in an oxygen atmosphere of 400 ° C are shown in Figs. 4A to 4E, respectively. As shown in Figures 4a to 4e, it can be seen that as the plasma treatment time increases, the surface roughness is improved. In particular, when 300 seconds or more (FIGS. 4D and 4E) it can be seen that the surface morphology of Ru does not change. It is thought that the Ru-O mixed phase having high oxidation resistance is uniformly formed by the plasma treatment on the top of the Ru, and this Ru-O mixed phase is thought to suppress the generation of RuO 2 during the subsequent curing.
한편, Ru의 표면에 RuO2가 형성되지 않음은 도 5를 보면 알 수 있다. 즉, 도 5의 그래프는 RuO2의 엑스레이 회절법에 의해 각 방향의 성장률을 분석한 그래프인 도 6과 다른 모양을 보인다. 그리고, 플라즈마처리 이전의 Ru과 플라즈마 처리 이후의 Ru의 각 방향의 성장 형태가 유사함을 알 수 있다.On the other hand, it can be seen from Figure 5 that RuO 2 is not formed on the surface of Ru. That is, the graph of FIG. 5 shows a different shape from that of FIG. 6, which is a graph in which the growth rate in each direction is analyzed by X-ray diffraction of RuO 2 . In addition, it can be seen that the growth patterns in the respective directions of Ru before the plasma treatment and Ru after the plasma treatment are similar.
금속층의 증착 후 산소 분위기에서의 열공정을 진행하기 이전에, 상기 열공정보다 낮은 온도에서 금속층을 산화시켜, 금속층의 상단에 금속-산소 성분의 혼합상을 형성한다. 따라서, 후속 열공정에 의한 금속 산화물의 생성이 억제되고 금속층의 표면 거칠기 증가가 억제되고 표면 모폴로지 특성이 개선된다. 특히 금속층이 캐패시터의 상부 전극일 경우에는 상부 전극 하부에 형성되는 유전막과의 계면 특성이 향상되고 캐패시터의 누설 전류가 감소하는 효과가 있다.After the deposition of the metal layer and before the thermal process in the oxygen atmosphere, the metal layer is oxidized at a lower temperature than the thermal process to form a mixed phase of the metal-oxygen component on the top of the metal layer. Therefore, generation of metal oxides by the subsequent thermal process is suppressed, increase in surface roughness of the metal layer is suppressed, and surface morphology characteristics are improved. In particular, when the metal layer is the upper electrode of the capacitor, the interface property with the dielectric film formed under the upper electrode is improved, and the leakage current of the capacitor is reduced.
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| US10/101,353 US6683001B2 (en) | 2001-04-10 | 2002-03-19 | Method for manufacturing a semiconductor device whereby degradation of surface morphology of a metal layer from thermal oxidation is suppressed |
| US10/690,763 US6927166B2 (en) | 2001-04-10 | 2003-10-22 | Method for manufacturing semiconductor devices and integrated circuit capacitors whereby degradation of surface morphology of a metal layer from thermal oxidation is suppressed |
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