KR100376267B1 - Method of manufacturing a capacitor in a semiconductor device - Google Patents

Method of manufacturing a capacitor in a semiconductor device Download PDF

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Publication number
KR100376267B1
KR100376267B1 KR10-1999-0060559A KR19990060559A KR100376267B1 KR 100376267 B1 KR100376267 B1 KR 100376267B1 KR 19990060559 A KR19990060559 A KR 19990060559A KR 100376267 B1 KR100376267 B1 KR 100376267B1
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South Korea
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capacitor
semiconductor device
oxide film
film
forming
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KR10-1999-0060559A
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Korean (ko)
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KR20010063475A (en
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박기선
김동준
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주식회사 하이닉스반도체
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Priority to KR10-1999-0060559A priority Critical patent/KR100376267B1/en
Priority to JP2000388212A priority patent/JP2001237400A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD

Abstract

본 발명은 반도체 소자의 캐패시터 제조방법에 관한 것으로, MIM 구조의 캐패시터에서 하부전극 형상을 정의하는 캐패시터 산화막 제거공정시 하부의 층간 절연막이 손실되고 하부의 콘택 플러그가 손상되어 캐패시터가 불안정한 구조를 갖게되는 문제점을 해결하기 위하여, 캐패시터 산화막을 형성하기 전 캐패시터 산화막과 높은 식각 선택비를 갖는 식각 장벽층을 형성하므로써, 후속 캐패시터 산화막 제거시 하부의 층간 절연막의 손실을 최소화할 수 있도록 한 반도체 소자의 캐패시터 제조방법이 개시된다.The present invention relates to a method for manufacturing a capacitor of a semiconductor device, in which a lower interlayer insulating film is lost and a lower contact plug is damaged during a capacitor oxide film removing process defining a lower electrode shape in a capacitor having a MIM structure, and thus the capacitor has an unstable structure. In order to solve the problem, by forming an etch barrier layer having a high etching selectivity with the capacitor oxide film before forming the capacitor oxide film, manufacturing a capacitor of the semiconductor device to minimize the loss of the interlayer insulating film during the subsequent removal of the capacitor oxide film The method is disclosed.

Description

반도체 소자의 캐패시터 제조방법{Method of manufacturing a capacitor in a semiconductor device}Method of manufacturing a capacitor in a semiconductor device

본 발명은 반도체 소자의 캐패시터 제조 방법에 관한 것으로, 특히MIM(Metal-Insulator-Metal) 구조의 캐패시터를 안정된 구조로 형성하기 위한 반도체 소자의 캐패시터 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and more particularly, to a method for manufacturing a capacitor of a semiconductor device for forming a capacitor having a metal-insulator-metal (MIM) structure in a stable structure.

반도체 소자가 고집적화됨에 따라, 소자의 안정적인 구동을 위해 필요한 단위 셀당 캐패시터의 정전용량은 일정한 반면, 캐패시터의 면적은 감소하기 때문에 좁은 면적에서도 필요한 정전용량을 확보하기 위해서는 고유전 절연막의 도입이 필요하게 된다. 현재 대표적으로 연구되고 있는 고유전 절연막은 탄탈륨 옥사이드(Ta2O5)이며, 유전체막으로 나이트라이드-옥사이드(NO)를 사용하는 NO 캐패시터 구조에서처럼, 하부전극으로 폴리실리콘을 사용하고 상부전극으로 금속, 예를 들어 TiN을 사용하는 MIS(Metal-Insulator-Silicon) Ta2O5캐패시터 구조가 주로 사용된다. Ta2O5는 저압 유기화합물 증착법(Metal Organic Chemical Vapor Deposition; MOCVD)에 의해 증착하는데, 이 경우 Ta2O5막 내에 다량의 불순물이 포함되어 있어 증착 후 산소 분위기의 고온 열처리가 필수적이다. 그런데 이때 Ta2O5유전체막과 상부 및 하부 전극 물질간에 계면반응이 일어나게 되어 누설전류가 증가하게 되고, 하부전극 표면의 폴리실리콘이 산화되어 유전체막의 유효 산화막 두께(TOX)를 감소시키기 어려운 문제점이 있다.As semiconductor devices are highly integrated, the capacitance of a capacitor per unit cell required for stable driving of the device is constant while the area of the capacitor is reduced, so that a high-k dielectric insulating film is required to secure necessary capacitance even in a small area. . The high dielectric insulating film currently being studied is tantalum oxide (Ta 2 O 5 ), and as in the NO capacitor structure using nitride-oxide (NO) as the dielectric film, polysilicon is used as the lower electrode and metal is used as the upper electrode. For example, a metal-insulator-silicon (MIS) Ta 2 O 5 capacitor structure using TiN is mainly used. Ta 2 O 5 is deposited by metal organic chemical vapor deposition (MOCVD). In this case, a large amount of impurities are included in the Ta 2 O 5 film, so that high temperature heat treatment of an oxygen atmosphere after deposition is essential. However, at this time, an interfacial reaction occurs between the Ta 2 O 5 dielectric layer and the upper and lower electrode materials, thereby increasing leakage current, and it is difficult to reduce the effective oxide thickness (T OX ) of the dielectric layer by oxidizing polysilicon on the lower electrode surface. There is this.

이러한 문제점을 해결하기 위하여 하부전극으로 텅스텐(W), 플래티늄(Pt), 루테늄(Ru), 이리듐(Ir) 등의 금속을 사용하는 MIM(Metal-Insulator-Metal) Ta2O5캐패시터 기술이 연구되고 있다. 이러한 MIM(Metal-Insulator-Metal) Ta2O5캐패시터는 종래의 MIS Ta2O5캐패시터와 달리 하부 콘택홀 플러깅 공정이 캐패시터 형성에서 가장 중요한 단위 공정 중의 하나이다. 하부 콘택홀 플러깅 방법으로는 하부 콘택홀을 폴리실리콘으로 플러깅하고 콘택홀 내의 일부 폴리실리콘을 리세스(Recess)한 다음 Ti/TiN 장벽 금속층(Barrier Metal)을 형성하는 방법, Ti/TiN 장벽 금속층 형성 후 하부전극 물질로 직접 하부 콘택홀을 플러깅 하는 방법 등이 있다. 그러나 종래의 방법으로는 후속 캐패시터 산화막을 제거(Dip out)하는 과정에서 층간 절연막의 손실이 심하여 후속 Ta2O5어닐링 공정에서 장벽 금속층이 산화되어 캐패시터의 전기적 특성이 저하하게 된다.In order to solve this problem, a metal-insulator-metal (MIM) Ta 2 O 5 capacitor technology using metals such as tungsten (W), platinum (Pt), ruthenium (Ru), and iridium (Ir) as a lower electrode is studied. It is becoming. Unlike the conventional MIS Ta 2 O 5 capacitor, the MIM (Metal-Insulator-Metal) Ta 2 O 5 capacitor is one of the most important unit processes in the formation of the lower contact hole plugging process. The lower contact hole plugging method includes plugging the lower contact hole into polysilicon, recessing some polysilicon in the contact hole, and then forming a Ti / TiN barrier metal layer, forming a Ti / TiN barrier metal layer. Afterwards, there is a method of plugging the lower contact hole directly into the lower electrode material. However, in the conventional method, the loss of the interlayer insulating film is severe during the dip out of the subsequent capacitor oxide film, so that the barrier metal layer is oxidized in the subsequent Ta 2 O 5 annealing process, thereby lowering the electrical characteristics of the capacitor.

따라서, 본 발명은 MIM Ta2O5캐패시터 구조에서 캐피시터 산화막 제거시의 식각 장벽층으로 알루미늄 옥사이드(Al2O3)를 이용하므로써, 캐패시터의 하부층인 층간 절연막의 손실을 최소화하고 이에 따라 캐패시터의 구조를 안정적으로 할 수 있는 반도체 소자의 캐패시터 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention uses aluminum oxide (Al 2 O 3 ) as an etch barrier layer when removing the capacitor oxide film in the MIM Ta 2 O 5 capacitor structure, thereby minimizing the loss of the interlayer insulating film, which is the lower layer of the capacitor, and thus the structure of the capacitor. It is an object of the present invention to provide a method for manufacturing a capacitor of a semiconductor device capable of stably.

상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 캐패시터 제조방법은 캐패시터를 형성하기 위한 하부구조가 형성된 기판 상에 층간 절연막을 형성하고, 상기 층간 절연막의 선택된 부분을 제거하여 콘택 플러그를 형성하는 단계; 상기 콘택 플러그가 형성된 전체구조 상에 식각 장벽층을 형성하는 단계; 상기 식각 장벽층 상에 캐패시터 산화막을 형성하고 캐패시터 마스크를 이용한 식각 공정으로 상기 캐패시터 산화막의 선택된 부분을 제거하여 실린더 구조를 형성하는 단계; 상기 실린더 구조를 갖는 전체구조 상에 하부전극용 금속층을 형성하는 단계; 전체구조 상에 갭 필링막을 형성한 후, 상기 캐패시터 산화막 상단의 상기 하부전극용 금속층이 제거되도록 연마하고 상기 포토레지스트막을 제거하는 단계; 노출된 상기 캐패시터 산화막을 제거하여 실린더형 하부전극이 형성되는 단계; 및 상기 하부전극이 형성된 전체구조 상에 유전체막 및 상부전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, wherein an interlayer insulating film is formed on a substrate on which a substructure for forming a capacitor is formed, and a contact plug is formed by removing selected portions of the interlayer insulating film. step; Forming an etch barrier layer on the entire structure in which the contact plug is formed; Forming a capacitor oxide film on the etching barrier layer and removing a selected portion of the capacitor oxide film by an etching process using a capacitor mask to form a cylinder structure; Forming a metal layer for a lower electrode on the entire structure having the cylinder structure; Forming a gap filling film on the entire structure, polishing the lower electrode metal layer on the capacitor oxide film to be removed, and removing the photoresist film; Removing the exposed capacitor oxide film to form a cylindrical lower electrode; And forming a dielectric film and an upper electrode on the entire structure in which the lower electrode is formed.

도 1a 내지 1f는 본 발명에 따른 반도체 소자의 캐패시터 제조방법을 설명하기 위해 순차적으로 도시한 소자의 단면도.1A to 1F are cross-sectional views of devices sequentially shown to explain a method of manufacturing a capacitor of a semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>

101 : 기판 102 : 층간 절연막101 substrate 102 interlayer insulating film

103 : 콘택 플러그 104 : 식각 장벽층103 contact plug 104 etching barrier layer

105 : 캐패시터 산화막 106 : 하부전극용 금속층105: capacitor oxide film 106: metal layer for lower electrode

107 : 갭 필링막 108 : 하부전극107: gap filling film 108: lower electrode

109 : 유전체막 110 : 상부전극109: dielectric film 110: upper electrode

본 발명은 캐패시터의 콘택 플러그 형성 후 캐패시터 산화막을 형성하기 전에 캐패시터 산화막과 큰 식각 선택비를 갖는 식각 장벽층(A12O3)을 형성한다. 이에 따라, 후속 캐패시터 산화막 제거 공정시 캐패시터 하부의 층간 절연막이 손실되는 것을 방지하여 안정된 구조의 캐패시터를 제조할 수 있도록 한다.The present invention forms an etch barrier layer A1 2 O 3 having a large etch selectivity with the capacitor oxide film after forming the contact plug of the capacitor and before forming the capacitor oxide film. Accordingly, during the subsequent capacitor oxide film removal process, the interlayer insulating film under the capacitor is prevented from being lost, so that a capacitor having a stable structure can be manufactured.

이하, 첨부된 도면을 참조하여 본 발명의 실시 예를 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

도 1a에 도시된 바와 같이, 캐패시터를 형성하기 위한 하부구조가 형성된 기판(101) 상에 층간 절연막(102)을 형성하고, 층간 절연막(102)의 선택된 부분을 제거하여 캐패시터 콘택홀을 형성한 다음 전체구조 상에 금속층을 형성한다. 이후,캐패시터 콘택홀 내부에만 금속층이 매립되도록 연마공정을 실시하므로써 콘택 플러그(103)가 형성된다. 다음에, 콘택 플러그(103)가 형성된 전체구조 상에 식각 장벽층(104)을 형성한다.As shown in FIG. 1A, an interlayer insulating film 102 is formed on a substrate 101 on which a substructure for forming a capacitor is formed, and a selected portion of the interlayer insulating film 102 is removed to form a capacitor contact hole. A metal layer is formed on the entire structure. Thereafter, the contact plug 103 is formed by performing a polishing process so that the metal layer is embedded only in the capacitor contact hole. Next, the etch barrier layer 104 is formed on the entire structure in which the contact plug 103 is formed.

여기에서, 콘택 플러그(103)는 대표적인 장벽 금속층 재료인 티타늄(Ti)과 티타늄 나이트라이드(TiN)의 적층 구조로 형성한다. 또한, 식각 장벽층(104)은 단원자 증착(Atomic Layer Deposition; ALD) 방법에 의해 알루미늄 옥사이드(Al2O3)를 증착하여 형성한다. ALD 방법으로 Al2O3층을 형성하면, Al2O3층의 두께 조절이 용이하고 스텝 커버리지(Step Coverage) 특성을 우수하게 할 수 있다. 또한, Al2O3를 이용한 식각 장벽층(104)은 후속 공정 단계에서 형성될 캐패시터 산화막을 제거할 때 습식 식각 장벽층으로 작용하여 하부 층간 절연막(102)의 손실을 방지할 수 있는 두께만큼 형성하는데, 예를 들어 캐패시터 산화막을 6000 내지 12000Å으로 형성할 경우 식각 장벽층(104)은 60 내지 240Å의 두께로 형성한다. ALD 방법을 이용하여 Al2O3식각 장벽층(104)을 형성할 때에는 반응기의 온도를 250 내지 350℃로 유지하고, 트리메틸 알루미늄(Trimethyl aluminum; Al(CH3)3) 가스와 트리에틸 알루미늄(Triethyl aluminum; Al(C2H5)3) 중 어느 하나의 제 1 원료가스와 H20, O2, N2O, CxHyOH 중 어느 하나의 제 2 원료가스를 교대로 반응기에 주입한다. 또한, 각 원료가스의 잔류물이 남지 않도록 하기 위하여 원료가스를 교대로 주입하는 사이사이에 N2, Ar, HE 등의 불활성 기체를 주입한다. 원료가스와 불활성 기체의 주입 시간은 0.1 내지 10sec로 한다. 식각 장벽층(104)은 ALD 방법에 의해 증착하는 Al2O3또는 화학기상증착법에 의해 증착하는 Ta2O5중 어느 하나를 이용하여 형성한다.Here, the contact plug 103 is formed in a laminated structure of titanium (Ti) and titanium nitride (TiN), which are representative barrier metal layer materials. In addition, the etching barrier layer 104 is formed by depositing aluminum oxide (Al 2 O 3 ) by an atomic layer deposition (ALD) method. When the Al 2 O 3 layer is formed by the ALD method, the thickness of the Al 2 O 3 layer can be easily controlled and the step coverage characteristics can be excellent. In addition, the etching barrier layer 104 using Al 2 O 3 is formed to a thickness that can prevent the loss of the lower interlayer insulating layer 102 by acting as a wet etching barrier layer when removing the capacitor oxide film to be formed in a subsequent process step. For example, when the capacitor oxide film is formed to be 6000 to 12000 GPa, the etching barrier layer 104 is formed to a thickness of 60 to 240 GPa. When the Al 2 O 3 etch barrier layer 104 is formed using the ALD method, the reactor temperature is maintained at 250 to 350 ° C., trimethyl aluminum (Al (CH 3 ) 3 ) gas and triethyl aluminum ( Triethyl aluminum; Al (C 2 H 5 ) 3 ) and the first source gas of any one of H 2 0, O 2 , N 2 O, C x H y OH alternately to the reactor Inject. In order to prevent the residue of each source gas from remaining, an inert gas such as N 2 , Ar, HE or the like is injected between alternately injecting source gases. The injection time of the source gas and the inert gas is 0.1 to 10 sec. The etching barrier layer 104 is formed using either Al 2 O 3 deposited by the ALD method or Ta 2 O 5 deposited by the chemical vapor deposition method.

도 1b에 도시된 바와 같이, 전체구조 상에 캐패시터 산화막(105)을 형성하고 캐패시터 마스크를 이용한 식각 공정을 실시하여 실린더 구조를 형성한다. 캐패시터 산화막(105)은 PSG(8.0wt%)를 이용하여 형성한다.As shown in FIG. 1B, a capacitor oxide film 105 is formed on the entire structure, and an etching process using a capacitor mask is performed to form a cylinder structure. The capacitor oxide film 105 is formed using PSG (8.0 wt%).

도 1c에 도시된 바와 같이, 실린더 구조를 갖는 전체구조 상에 하부전극용 금속층(106)을 형성한다. 하부전극용 금속층(106)은 물리기상증착법(PVD)과 화학기상증착법(CVD)을 번갈아 실시하여 텅스텐(W)을 증착하여 형성한다. 물리기상증착법으로 텅스텐을 증착하는 경우에는 텅스텐층을 100 내지 200Å의 두께로 형성하며, 캐패시터 산화막(103) 측면에서 점착 특성을 향상시킬 수 있다. 또한, 화학기상증착법으로 텅스텐을 증착하는 경우에는 텅스텐층을 200 내지 400Å의 두께로 형성하며, 초기성장 메카니즘을 조절하여 전체 하부전극의 두께, 표면 거칠기 등을 용이하게 조절할 수 있다. 하부전극용 금속층(106)은 텅스텐(W) 외에도, 텅스텐 실리사이드(WSix), 텅스텐 나이트라이드(WN), 티타늄 실리사이드(TiSix), 티타늄 나이트라이드(TiN), 플래티늄(Pt), 루테늄(Ru), 이리듐(Ir) 중 어느 하나를 이용하여 형성할 수 있다.As shown in FIG. 1C, the metal layer 106 for lower electrodes is formed on the entire structure having a cylinder structure. The lower electrode metal layer 106 is formed by depositing tungsten (W) by alternately performing physical vapor deposition (PVD) and chemical vapor deposition (CVD). In the case of depositing tungsten by physical vapor deposition, the tungsten layer may be formed to a thickness of 100 to 200 kPa, and the adhesion characteristics may be improved in the capacitor oxide film 103. In addition, in the case of depositing tungsten by chemical vapor deposition, the tungsten layer is formed to a thickness of 200 to 400 GPa, and the initial growth mechanism can be adjusted to easily control the thickness and surface roughness of the entire lower electrode. The lower electrode metal layer 106 includes tungsten silicide (WSi x ), tungsten nitride (WN), titanium silicide (TiSi x ), titanium nitride (TiN), platinum (Pt), and ruthenium (Ru) in addition to tungsten (W). ) And iridium (Ir) can be formed.

도 1d는 전체구조 상에 갭 필링막(107)을 형성한 후, 캐패시터 산화막(105) 상단의 하부전극용 금속층(106)이 제거되도록 연마공정을 실시한 상태를 나타낸다.FIG. 1D illustrates a state in which the gap filling film 107 is formed over the entire structure, and then the polishing process is performed such that the lower electrode metal layer 106 on the capacitor oxide film 105 is removed.

여기에서, 갭 필링막(107)은 포토레지스트막 또는 언도프트 산화막을 사용하여 형성한다.Here, the gap filling film 107 is formed using a photoresist film or an undoped oxide film.

도 1e는 갭 필링막(107)을 제거한 후, 노출된 캐패시터 산화막(105)을 제거하여 실린더형 하부전극(108)이 형성된 상태를 나타낸다. 캐패시터 산화막(105)은 50:1 불산(HF) 용해제를 이용하여 100% 과도 딥 아웃(Over Deep out)하므로써 제거된다. 이때, 층간 절연막(102) 상의 Al2O3식각 장벽층(104)은 캐패시터 산화막(105)과의 식각 선택비가 높기 때문에, 캐패시터 산화막(105) 제거시의 식각 장벽층으로 작용하여 층간 절연막(102)이 손실되는 것을 방지할 수 있고 이에 따라, 안정된 캐패시터 구조를 형성할 수 있다. 실제로 캐패시터 산화막(105)을 PSG(8.0wt%)를 이용하여 형성하고 50:1 불산(HF) 용해제를 이용하여 식각할 때, 캐패시터 산화막(105)과 Al2O3식각 장벽층(104)의 식각율은 각각 20Å/sec와 0.5Å/sec가 되어 식각 선택비가 매우 높게 나타나는 것을 실험을 통해 확인하였다.FIG. 1E illustrates a state where the cylindrical lower electrode 108 is formed by removing the gap filling film 107 and then removing the exposed capacitor oxide film 105. The capacitor oxide film 105 is removed by 100% over deep out using a 50: 1 hydrofluoric acid (HF) solvent. At this time, since the Al 2 O 3 etch barrier layer 104 on the interlayer insulating film 102 has a high etching selectivity with the capacitor oxide film 105, the Al 2 O 3 etching barrier layer 104 acts as an etch barrier layer when the capacitor oxide film 105 is removed to form an interlayer insulating film 102. ) Can be prevented from being lost, thereby forming a stable capacitor structure. In fact, when the capacitor oxide film 105 is formed using PSG (8.0 wt%) and etched using a 50: 1 hydrofluoric acid (HF) solvent, the capacitor oxide film 105 and the Al 2 O 3 etching barrier layer 104 The etching rate was 20Å / sec and 0.5Å / sec, respectively, and it was confirmed through experiments that the etching selectivity was very high.

도 1f에 도시된 바와 같이, 하부전극(108)이 형성된 전체구조 상에 유전체막(109)을 형성하고 열처리한 후 상부전극(110)을 형성하므로써, MIM 구조의 캐패시터가 완성되게 된다. 여기에서, 유전체막(109)은 Ta2O5를 이용하여 100 내지 200Å의 두께로 형성한다. 유전체막(109) 형성 후의 열처리 공정은 400 내지 700℃에서 10 내지 60분간 진행하며, UV/O3또는 플라즈마 방법을 이용한다. 상부전극(110)은 티타늄 나이트라이드막(TiN)을 이용한 화학기상증착법 또는 ALD 방법에 의해 200 내지 500Å의 두께로 형성한다. 상부전극(110) 재료로서, 티타늄나이트라이드(TiN) 대신 플래티늄(Pt), 루테늄(Ru), 이리듐(Ir) 중 어느 하나를 이용하는 것도 가능하다.As shown in FIG. 1F, the MIM structure capacitor is completed by forming the dielectric film 109 on the entire structure where the lower electrode 108 is formed and then performing heat treatment to form the upper electrode 110. Here, the dielectric film 109 is formed to a thickness of 100 to 200 GPa using Ta 2 O 5 . After the dielectric film 109 is formed, the heat treatment process is performed at 400 to 700 ° C. for 10 to 60 minutes, and a UV / O 3 or plasma method is used. The upper electrode 110 is formed to a thickness of 200 to 500 kW by chemical vapor deposition or ALD using a titanium nitride film (TiN). As the material of the upper electrode 110, any one of platinum (Pt), ruthenium (Ru), and iridium (Ir) may be used instead of titanium nitride (TiN).

상술한 바와 같이, 본 발명은 캐패시터 산화막과 높은 식각 선택비를 갖는 식각 장벽층을 이용하므로써 캐패시터 산화막 제거공정시 캐패시터 하부의 층간 절연막이 손실되는 것을 최소화할 수 있어, 안정된 구조의 캐패시터를 제조할 수 있고, 이에 따라 캐패시터의 전기적 특성을 향상시킬 수 있다.As described above, the present invention can minimize the loss of the interlayer insulating film under the capacitor during the capacitor oxide film removing process by using the capacitor oxide film and the etching barrier layer having a high etching selectivity, so that a capacitor having a stable structure can be manufactured. As a result, the electrical characteristics of the capacitor can be improved.

Claims (13)

소정의 구조가 형성된 반도체 기판 상부에 층간 절연막을 형성하고, 상기 층간 절연막의 소정 영역에 콘택 플러그를 형성하는 단계;Forming an interlayer insulating film on the semiconductor substrate having a predetermined structure and forming a contact plug in a predetermined region of the interlayer insulating film; 전체 구조 상부에 식각 장벽층으로 알루미늄 옥사이드막 또는 탄탈륨 옥사이드막을 형성하는 단계;Forming an aluminum oxide film or a tantalum oxide film as an etch barrier layer on the entire structure; 상기 식각 장벽층 상부에 캐패시터 산화막을 형성하고 패터닝하는 단계;Forming and patterning a capacitor oxide layer on the etch barrier layer; 전체 구조 상부에 하부전극용 금속층을 형성하는 단계;Forming a lower electrode metal layer on the entire structure; 전체 구조 상부에 갭 필링막을 형성하고 상기 캐패시터 산화막 상단의 상기 하부전극용 금속층이 제거되도록 연마한 후 상기 갭 필링막을 제거하는 단계;Forming a gap filling film over the entire structure, polishing the lower electrode metal layer on the capacitor oxide film to be removed, and then removing the gap filling film; 상기 캐패시터 산화막을 제거하여 실린더형 하부전극이 형성되는 단계; 및Removing the capacitor oxide film to form a cylindrical lower electrode; And 전체 구조 상부에 유전체막 및 상부전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.And forming a dielectric film and an upper electrode over the entire structure. 제 1 항에 있어서,The method of claim 1, 상기 알루미늄 옥사이드는 ALD 방법에 의해 형성하고, 상기 탄탈륨 옥사이드는 화학기상증착법에 의해 형성하며, 이들은 각각 60 내지 240Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The aluminum oxide is formed by the ALD method, the tantalum oxide is formed by a chemical vapor deposition method, they are each formed in a thickness of 60 to 240 Å each of the capacitor manufacturing method of the semiconductor device. 제 2 항에 있어서,The method of claim 2, 상기 알루미늄 옥사이드막은 반응기의 온도를 250 내지 350℃로 유지하고, 제 1 원료가스 및 제 2 원료가스를 교대로 반응기에 주입하며, 상기 제 1 및 제 2 원료가스를 주입하는 사이사이에 불활성 기체를 주입하여 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The aluminum oxide film maintains the temperature of the reactor at 250 to 350 ° C., alternately injects the first source gas and the second source gas into the reactor, and introduces an inert gas between the first and second source gases. Capacitor manufacturing method of a semiconductor device, characterized in that formed by injection. 제 3 항에 있어서,The method of claim 3, wherein 상기 제 1 및 제 2 원료 가스, 상기 불활성 기체의 주입 시간은 0.1 내지 10sec로 하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The injection time of the said 1st, 2nd source gas, and the said inert gas is 0.1-10 sec, The capacitor manufacturing method of the semiconductor element characterized by the above-mentioned. 제 3 항에 있어서,The method of claim 3, wherein 상기 제 1 원료가스로는 Al(CH3)3또는 Al(C2H5)3)를 이용하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.Al (CH 3 ) 3 or Al (C 2 H 5 ) 3 ) is used as the first source gas capacitor manufacturing method of a semiconductor device. 제 3 항에 있어서,The method of claim 3, wherein 상기 제 2 원료가스로는 H20, O2, N2O, CxHyOH 중 어느 하나를 이용하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The second raw material gas, the capacitor manufacturing method of the semiconductor device which is characterized in that one of H 2 0, O 2, N 2 O, C x H y OH. 제 1 항에 있어서,The method of claim 1, 상기 캐패시터 산화막은 PSG를 이용하여 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The capacitor oxide film is a capacitor manufacturing method of a semiconductor device, characterized in that formed using PSG. 제 1 항에 있어서,The method of claim 1, 상기 하부전극용 금속층은 물리기상증착법에 의해 텅스텐을 100 내지 200Å의 두께로 증착하는 방법과 화학기상증착법에 의해 텅스텐을 200 내지 400Å의 두께로 증착하는 방법을 번갈아 실시하여 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The lower electrode metal layer is formed by alternately depositing tungsten to a thickness of 100 to 200 kW by physical vapor deposition and alternately depositing tungsten to a thickness of 200 to 400 kW by chemical vapor deposition. Capacitor manufacturing method of device. 제 1 항에 있어서,The method of claim 1, 상기 하부전극용 금속층은 텅스텐, 텅스텐 실리사이드, 텅스텐 나이트라이드, 티타늄 실리사이드, 티타늄 나이트라이드, 플래티늄, 루테늄, 이리듐 중 어느 하나를 이용하여 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The metal layer for the lower electrode is a capacitor manufacturing method of a semiconductor device, characterized in that formed using any one of tungsten, tungsten silicide, tungsten nitride, titanium silicide, titanium nitride, platinum, ruthenium, iridium. 제 1 항에 있어서,The method of claim 1, 상기 캐패시터 산화막은 50:1 불산 용해제를 이용하여 제거하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.And the capacitor oxide film is removed using a 50: 1 hydrofluoric acid solvent. 제 1 항에 있어서,The method of claim 1, 상기 유전체막은 100 내지 200Å의 두께로 탄탈륨 옥사이드를 증착하여 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The dielectric film is a capacitor manufacturing method of a semiconductor device, characterized in that formed by depositing tantalum oxide to a thickness of 100 to 200Å. 제 1 항에 있어서,The method of claim 1, 상기 상부전극은 화학기상증착법 또는 ALD 방법에 의해 티타늄 나이트라이드막을 200 내지 500Å의 두께로 증착하여 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The upper electrode is a capacitor manufacturing method of a semiconductor device, characterized in that formed by depositing a titanium nitride film to a thickness of 200 to 500Å by chemical vapor deposition or ALD method. 제 1 항에 있어서,The method of claim 1, 상기 상부전극은 티타늄 나이트라이드, 플래티늄, 루테늄, 이리듐 중 어느 하나를 이용하여 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 제조방법.The upper electrode is a capacitor manufacturing method of a semiconductor device, characterized in that formed using any one of titanium nitride, platinum, ruthenium, iridium.
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