KR100368303B1 - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
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- KR100368303B1 KR100368303B1 KR10-1999-0065174A KR19990065174A KR100368303B1 KR 100368303 B1 KR100368303 B1 KR 100368303B1 KR 19990065174 A KR19990065174 A KR 19990065174A KR 100368303 B1 KR100368303 B1 KR 100368303B1
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- Prior art keywords
- trench
- semiconductor substrate
- layer
- film
- forming
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- 229920005591 polysilicon Polymers 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 13
- 239000011229 interlayer Substances 0.000 description 8
- 238000000151 deposition Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Abstract
본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 플래쉬 메모리 소자 및 EEPROM 을 기판의 트랜치(Trench)에 매립되도록 형성하여 후속 금속 배선 공정에서 발생되는 토폴로지(Topology) 문제를 해결할 수 있는 반도체 소자의 제조방법을 제시한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, a method of manufacturing a semiconductor device capable of solving a topology problem generated in a subsequent metal wiring process by forming a flash memory device and an EEPROM embedded in a trench of a substrate. To present.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 플래쉬 메모리 소자 및 EEPROM을 기판의 트랜치(Trench)에 매립되도록 형성하여 후속 금속 배선 공정에서 발생되는 토폴로지(Topology) 문제를 해결할 수 있는 플래쉬 메모리 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, a flash memory device and an EEPROM are formed to be embedded in a trench of a substrate, thereby manufacturing a flash memory device capable of solving a topology problem generated in a subsequent metal wiring process. It is about a method.
종래 반도체 소자의 플래쉬 메모리 소자 및 EEPROM 제조 방법은 다음과 같다.A flash memory device and an EEPROM manufacturing method of a conventional semiconductor device are as follows.
반도체 기판 상에 터널 산화막 및 제 1 폴리실리콘막을 순차적으로 형성한 후 마스크를 이용한 식각공정으로 제 1 폴리실리콘막 및 터널 산화막을 패터닝하고, 전체 상부면에 유전체막, 제 2 폴리실리콘막, 실리사이드층 및 반사방지막을 순차적으로 적층한 후 이들을 게이트 마스크를 이용한 식각공정으로 제 1 폴리실리콘막이 플로팅 게이트가 되고, 제 2 폴리실리콘막이 콘트롤 게이트가 되는 스택구조의 게이트를 형성한다. 이후, 이온주입공정으로 반도체 기판에 LDD(Lightly Doped Drain) 영역을 형성한다.After the tunnel oxide film and the first polysilicon film were sequentially formed on the semiconductor substrate, the first polysilicon film and the tunnel oxide film were patterned by an etching process using a mask, and the dielectric film, the second polysilicon film, and the silicide layer were formed on the entire upper surface. And sequentially stacking the antireflection films, and forming the gates of the stack structure in which the first polysilicon film becomes a floating gate and the second polysilicon film becomes a control gate by an etching process using a gate mask. Thereafter, an LDD (Lightly Doped Drain) region is formed on the semiconductor substrate by an ion implantation process.
스택 구조의 게이트 측부에 스페이서를 형성한 후 게이트 측부의 반도체 기판에 소오스/드레인 이온주입공정을 실시하여 소오스 및 드레인을 형성하고, 전체 상부면에 층간절연막 및 금속 배선을 다층구조로 형성한다.After the spacers are formed on the gate side of the stack structure, source and drain ion implantation processes are performed on the semiconductor substrate on the gate side to form a source and a drain, and an interlayer insulating film and a metal wiring are formed on the entire upper surface in a multilayer structure.
상술한 종래 스택 구조의 게이트전극을 갖는 플래쉬 메모리 소자 및 EEPROM 은 이중 폴리실리콘막 구조로서 토폴로지로 인하여 후속 금속 배선공정시 정확한 타겟 콘트롤을 어렵게 하는 문제점이 있다.The flash memory device and the EEPROM having the gate electrode of the conventional stack structure described above have a double polysilicon film structure, which makes it difficult to accurately control targets in subsequent metal wiring processes due to the topology.
따라서, 본 발명은 플래쉬 메모리 소자 및 EEPROM의 스택 구조 게이트 전극으로 인한 토폴로지 문제를 해소하여 후속 금속 배선공정을 편리하고 정확하게 형성할 수 있도록 하는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device, which can solve the topology problem caused by the flash memory device and the stack structure gate electrode of the EEPROM so as to conveniently and accurately form the subsequent metal wiring process.
상기한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 메모리 소자 제조방법은 트렌치가 형성된 반도체 기판 전체 상부면에 터널 산화막 및 제 1 폴리실리콘막을 형성하는 단계; 상기 트렌치 내에 플로팅 게이트가 형성되고, 상기 플로팅 게이트 양측부에 LDD 영역이 정의되도록 상기 제 1 폴리실리콘막을 패터닝하는 단계; LDD 이온주입공정으로 상기 플로팅 게이트 측부의 반도체 기판에 LDD영역을 형성하는 단계; 전체 상부면에 유전체막을 형성한 후 제 2 폴리실리콘막을 증착하는 단계; 상기 반도체 기판의 표면이 노출될 때까지 상기 제 2 폴리실리콘막, 유전체막 및 터널 산화막을 전면 식각하여 트랜치 내부에 터널 산화막, 플로팅 게이트, 유전체막 및 콘트롤 게이트로 이루어진 게이트를 형성되도록 하는 단계; 소오스/드레인 이온주입공정으로 소오스 및 드레인 접합부을 형성하는 단계; 및 전체상부면에 다층 구조의 금속 배선을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.Memory device manufacturing method of a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a tunnel oxide film and the first polysilicon film on the entire upper surface of the semiconductor substrate is formed trench; Forming a floating gate in the trench and patterning the first polysilicon layer so that LDD regions are defined at both sides of the floating gate; Forming an LDD region on a semiconductor substrate of the floating gate side by an LDD ion implantation process; Depositing a second polysilicon film after forming a dielectric film on the entire upper surface; Etching the second polysilicon layer, the dielectric layer, and the tunnel oxide layer until the surface of the semiconductor substrate is exposed to form a gate including a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate in the trench; Forming a source and drain junction by a source / drain ion implantation process; And forming a metal wiring having a multi-layer structure on the entire upper surface.
도 1a 내지 도 1f는 본 발명에 따른 반도체 소자의 제조방법을 설명하기 위한 소자의 단면도.1A to 1F are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device according to the present invention.
〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>
10 : 반도체 기판 11 : 터널 산화막10 semiconductor substrate 11 tunnel oxide film
12 : 제 1 폴리실리콘막 12a : 플로팅 게이트12: first polysilicon film 12a: floating gate
13 : 감광막 패턴 14 : LDD영역13 photosensitive film pattern 14 LDD region
15 : 유전체막 16 : 제 2 폴리실리콘막15 dielectric film 16 second polysilicon film
16a : 콘트롤 게이트 17 : 소오스/드레인16a: control gate 17: source / drain
18 : 제 1 층간절연막 19 : 제 1 금속 배선18: first interlayer insulating film 19: first metal wiring
20 : 제 2 층간절연막 21 : 제 2 금속배선20: second interlayer insulating film 21: second metal wiring
22 : 제 3 층간절연막 23 : 제 3 금속배선22: third interlayer insulating film 23: third metal wiring
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1f는 본 발명에 따른 반도체 소자의 제조방법을 설명하기 위한 소자의 단면도이다.1A to 1F are cross-sectional views of devices for describing a method of manufacturing a semiconductor device according to the present invention.
도 1a를 참조하면, 셀이 형성될 영역의 반도체 기판(10)을 일정 깊이 식각하여 트랜치를 형성한다. 트렌치가 형성된 반도체 기판(10) 전체 상부면에 터널 산화막(11) 및 제 1 폴리실리콘막(12)을 형성한 후 트렌치 영역의 제 1 폴리실리콘막(12) 상부면에 플로팅 게이트 마스크를 이용하여 감광막 패턴(13)을 형성한다.Referring to FIG. 1A, a trench is formed by etching a semiconductor substrate 10 in a region where a cell is to be formed. After the tunnel oxide film 11 and the first polysilicon film 12 are formed on the entire upper surface of the semiconductor substrate 10 where the trench is formed, a floating gate mask is used on the upper surface of the first polysilicon film 12 in the trench region. The photosensitive film pattern 13 is formed.
도 1b를 참조하면, 감광막 패턴(13)을 식각 마스크로 이용한 식각공정으로 제 1 폴리실리콘막(12)의 노출된 부분을 제거하고, 이로인하여 트렌치 내에 플로팅 게이트(12a)가 형성되고, 플로팅 게이트(12a) 양측부에 LDD 영역이 형성될 부분이 정의(define)된다. LDD 이온 주입공정으로 플로팅 게이트(12a) 측부의 반도체 기판(10)에 LDD영역(14)을 형성한다.Referring to FIG. 1B, an exposed portion of the first polysilicon layer 12 is removed by an etching process using the photoresist pattern 13 as an etching mask, thereby forming a floating gate 12a in the trench, and forming a floating gate. (12a) The portions where the LDD regions are to be formed at both sides are defined. The LDD region 14 is formed in the semiconductor substrate 10 on the side of the floating gate 12a by an LDD ion implantation process.
도 1c를 참조하면, 전체 상부면에 유전체막(15)을 형성한 후 제 2 폴리실리콘막(16)을 트렌치가 완전히 매립되도록 증착한다.Referring to FIG. 1C, after the dielectric film 15 is formed on the entire upper surface, the second polysilicon film 16 is deposited to completely fill the trench.
도 1d를 참조하면, 반도체 기판(10)의 표면이 노출될 때까지 제 2 폴리실리콘막(16), 유전체막(15) 및 터널 산화막(11)을 전면 식각하여 트랜치 내부에 터널 산화막(11), 플로팅 게이트(12a), 유전체막(15) 및 콘트롤 게이트(16a)로 이루어진 게이트를 형성한다. 소오스/드레인 이온주입공정으로 소오스 및 드레인 접합부(17)을 형성한다.Referring to FIG. 1D, the second polysilicon layer 16, the dielectric layer 15, and the tunnel oxide layer 11 are etched to the entire surface until the surface of the semiconductor substrate 10 is exposed, and the tunnel oxide layer 11 is formed inside the trench. And a gate formed of the floating gate 12a, the dielectric film 15, and the control gate 16a. The source and drain junctions 17 are formed by a source / drain ion implantation process.
상기에서, 전면 식각은 화학적 기계적 연마방법으로 실시한다.In the above, the front surface etching is performed by a chemical mechanical polishing method.
도 1e는 전체상부면에 제 1 층간절연막(18)을 형성한 상태의 단면도이다.FIG. 1E is a cross-sectional view of the first interlayer insulating film 18 formed on the entire upper surface.
도 1f를 참조하면, 제 1 층간절연막(18)을 패터닝한 후 제 1 금속 배선(19)을 형성하고, 제 2 층간절연막(20), 제 2 금속 배선(21), 제 3 층간절연막(22) 및 제 3 금속 배선(23)을 순차적을 형성한다.Referring to FIG. 1F, after the first interlayer insulating film 18 is patterned, the first metal wiring 19 is formed, and the second interlayer insulating film 20, the second metal wiring 21, and the third interlayer insulating film 22 are formed. ) And the third metal wiring 23 are sequentially formed.
상술한 바와 같이, 본 발명은 종래 반도체 기판 상부면에 형성되는 게이트 전극으로 인한 토폴로지 영향을 받지않도록 반도체 기판의 트랜치 내부에 게이트 전극을 형성하므로 후속 금속 배선 공정시 평탄화 된 토폴로지에 의해 공정 콘트롤이 쉽고 금속 배선의 패일(fail)이 감소되어 소자의 수율이 향상되는 효과가 있다.As described above, the present invention forms a gate electrode inside the trench of the semiconductor substrate so as not to be affected by the topology due to the gate electrode formed on the upper surface of the conventional semiconductor substrate, and thus, the process control is easy by the flattened topology during the subsequent metal wiring process. Fail of the metal wiring is reduced, thereby improving the yield of the device.
Claims (2)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1999-0065174A KR100368303B1 (en) | 1999-12-29 | 1999-12-29 | Method of manufacturing a semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1999-0065174A KR100368303B1 (en) | 1999-12-29 | 1999-12-29 | Method of manufacturing a semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR20010065301A KR20010065301A (en) | 2001-07-11 |
| KR100368303B1 true KR100368303B1 (en) | 2003-01-24 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR10-1999-0065174A KR100368303B1 (en) | 1999-12-29 | 1999-12-29 | Method of manufacturing a semiconductor device |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1041414A (en) * | 1996-07-17 | 1998-02-13 | Ricoh Co Ltd | Nonvolatile semiconductor memory device and manufacture thereof |
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1999
- 1999-12-29 KR KR10-1999-0065174A patent/KR100368303B1/en not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1041414A (en) * | 1996-07-17 | 1998-02-13 | Ricoh Co Ltd | Nonvolatile semiconductor memory device and manufacture thereof |
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| KR20010065301A (en) | 2001-07-11 |
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