KR100365418B1 - Method for manufacturing capacitor of semiconductor device - Google Patents

Method for manufacturing capacitor of semiconductor device Download PDF

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Publication number
KR100365418B1
KR100365418B1 KR1019950019369A KR19950019369A KR100365418B1 KR 100365418 B1 KR100365418 B1 KR 100365418B1 KR 1019950019369 A KR1019950019369 A KR 1019950019369A KR 19950019369 A KR19950019369 A KR 19950019369A KR 100365418 B1 KR100365418 B1 KR 100365418B1
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South Korea
Prior art keywords
forming
charge storage
capacitor
nitride
nitride film
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KR1019950019369A
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Korean (ko)
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KR970004009A (en
Inventor
이형동
장명식
박진요
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주식회사 하이닉스반도체
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Priority to KR1019950019369A priority Critical patent/KR100365418B1/en
Publication of KR970004009A publication Critical patent/KR970004009A/en
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Publication of KR100365418B1 publication Critical patent/KR100365418B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors

Abstract

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to be capable of protecting the bottom portion of an electrode though oxygen is penetrated through a nitride layer by forming a nitride layer spacer and a nitride-oxide layer. CONSTITUTION: After forming an interlayer dielectric on a semiconductor substrate(1), a contact hole is formed by selectively etching the interlayer dielectric for forming a capacitor. An electric charge storage node(3) made of polysilicon is formed in the contact hole. After depositing a nitride layer on the entire surface of the resultant structure, a nitride layer spacer is partially formed at the bottom portion of the electric charge storage node by carrying out a blanket etching process. A dielectric layer(5) made of a nitride layer and an oxide layer is formed on the electric charge storage node. Then, a plate electrode(6) is formed on the resultant structure by depositing polysilicon.

Description

반도체 소자의 캐패시터 제조 방법Capacitor Manufacturing Method of Semiconductor Device

본 발명은 일반적으로 반도체 소자 제조 방법에 관한 것으로서 특히 유전층(Dielectric)으로 질화막-산화막(Nitride-Oxide)층을 이용하는 캐패시터(Capacitor)를 제조하는데 있어서, 질화막 스페이서를 이용하여 보다 수율이 높은 캐패시터를 제조하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method of manufacturing a semiconductor device, and in particular, in manufacturing a capacitor using a nitride-oxide layer as a dielectric layer, a capacitor having a higher yield is manufactured by using a nitride spacer. It is about how to.

반도체 소자가 고집적화됨에 따라 캐패시터의 유전층으로 질화막-산화막-질화막(ONO)층을 사용하던 구조보다 질화막-산화막(NO)층을 이용하는 구조를 사용하고자 하는 시도가 늘고 있다. 그러나 증착된 질화막의 두께가 얇은 경우에 산소가 질화막을 통해 침투되어, 질화막의 스텝커버리지(step coverage)가 나쁜 부분인 전하저장 전극(Storage Node)의 밑부분을 산화시켜 캐패시터를 불량화시킨다는 문제점을 가지고 있었다.As semiconductor devices have been highly integrated, attempts have been made to use a structure using a nitride-oxide (NO) layer rather than a structure using a nitride-oxide-nitride (ONO) layer as a dielectric layer of a capacitor. However, when the thickness of the deposited nitride film is thin, oxygen penetrates through the nitride film, thereby oxidizing the lower portion of the storage node, which is a poor step coverage of the nitride film, to deteriorate the capacitor. I had.

따라서, 전술한 바와 같은 문제점을 해결하기 위해 안출된 본 발명은 전하저장 전극을 형성한 후 전하저장 전극의 밑부분에 부분적으로 질화막 스페이서를 형성하고 질화막-산화막층을 형성하므로써, 산소가 질화막을 통해 침투하더라도 전극의 밑부분을 보호하여 보다 양호한 캐패시터를 제조하는 방법을 제공하는 것을 목적으로 한다.Accordingly, the present invention devised to solve the above-described problems is formed by forming a nitride spacer and a nitride film-oxide layer at the bottom of the charge storage electrode after forming the charge storage electrode, so that oxygen passes through the nitride film. It is an object of the present invention to provide a method of manufacturing a better capacitor by protecting the bottom of the electrode even if it penetrates.

본 발명의 캐패시터 제조 방법은, 반도체 기판에 모스트렌지스터가 형성된 구조 상에 층간 절연막을 형성하는 단계와, 캐패시터를 형성하기 위한 콘택홀을 형성하고 폴리실리콘으로 전하저장 전극을 형성하는 단계와, 스페이서를 형성하기 위한 질화막을 증착한 후, 상기 질화막을 블랭킷 식각하여 전하저장 전극의 밑부분에 부분적으로 질화막 스페이서를 형성하는 단계와, 질화막-산화막층으로 이루어진 유전층을 형성하는 단계 및, 플레이트 전극을 형성하기 위한 폴리실리콘을 증착하는 단계를 포함하여 이루어진 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a capacitor, including forming an interlayer insulating film on a structure in which a transistor is formed in a semiconductor substrate, forming a contact hole for forming a capacitor, and forming a charge storage electrode with polysilicon, and After depositing a nitride film for formation, blanket etching the nitride film to form a nitride spacer partially at the bottom of the charge storage electrode, forming a dielectric layer consisting of a nitride film-oxide layer, and forming a plate electrode Characterized in that it comprises a step for depositing polysilicon.

이제 본 발명의 캐패시터 제조 방법의 실시예에 대하여 첨부도면을 참조하여 상세하게 살펴보게 된다, 먼저 제 1A도에 도시 된 바와 같이 반도체 기판(1)에 모스(MOS) 트렌지스터가 형성된 구조 상에 층간 절연막(2)을 형성한다. 다음으로 제 1B도에 도시된 바와 같이 캐패시터를 형성하기 위한 콘택홀을 형성하고 폴리실리콘으로 전하저장 전극(Storage node)(3)을 형성한다. 다음으로 제 1C도에 도시된 바와 같이 측벽 스페이서를 형성하기 위한 질화막을 증착한 후, 상기 질화막을 블랭킷(blanket) 식각하여 전하저장 전극의 밑부분에 부분적으로 질화막 스페이서(4)를 형성한다. 다음으로 제 1 D도에 도시된 바와 같이 유전층으로 질화막-산화막(Nitride-Oxide)층(5)을 형성한다. 다음으로 제 1E도에 도시된 바와 같이 플레이트 전극(Plate Node)(6)을 형성하기 위한 폴리실리콘을 증착한다.An embodiment of a capacitor manufacturing method of the present invention will now be described in detail with reference to the accompanying drawings. First, as shown in FIG. 1A, an interlayer insulating film is formed on a structure in which a MOS transistor is formed on a semiconductor substrate 1. (2) is formed. Next, as shown in FIG. 1B, a contact hole for forming a capacitor is formed, and a storage node 3 is formed of polysilicon. Next, as shown in FIG. 1C, after depositing a nitride film for forming sidewall spacers, the nitride film is blanket-etched to form a nitride film spacer 4 partially under the charge storage electrode. Next, as shown in FIG. 1D, a nitride-oxide layer 5 is formed of a dielectric layer. Next, as shown in FIG. 1E, polysilicon is deposited to form a plate electrode 6.

반도체 소자 제조시, 전술한 바와 같은 본 발명에 따라 유전층으로 산화막-질화막-산화막층을 이용하는 구조 대신 질화막-산화막 구조의 유전층을 형성하므로써 유전층의 두께를 줄일 수 있어 고용량의 캐패시터를 형성할 수 있으면서, 얇은 질화막을 통해 침투된 산소에 의한 산화작용을 방지 할 수 있어 보다 양호한 캐패시터를 제조할 수 있다.When manufacturing a semiconductor device, the thickness of the dielectric layer can be reduced by forming a dielectric layer having a nitride-oxide structure instead of the structure using the oxide-nitride-oxide layer as the dielectric layer in accordance with the present invention as described above, while forming a capacitor having a high capacity, It is possible to prevent the oxidation by the oxygen penetrated through the thin nitride film can be produced a better capacitor.

제 1A도 내지 제 1E도는 본 발명의 캐패시터 제조 방법에 따른 공정도.1A to 1E are process drawings according to the method of manufacturing a capacitor of the present invention.

※ 도면의 주요 부분에 대한 부호의 설명 ※※ Explanation of code about main part of drawing ※

1 : 반도체 기판 2 : 층간절연막1 semiconductor substrate 2 interlayer insulating film

3 : 전하저장 전극 4 : 질화막 스페이서3: charge storage electrode 4: nitride film spacer

5 : NO막 6 : 플래이트 전극5: NO film 6: plate electrode

Claims (1)

모스 트렌지스터가 형성된 반도체 기판에 있어서,In a semiconductor substrate having a MOS transistor, 상기 반도체 기판상에 층간 절연막을 형성하고, 상기 층간 절연막을 선택적으로 식각하여 캐패시터를 형성하기 위한 콘택홀을 형성하는 단계와;Forming an interlayer insulating film on the semiconductor substrate and selectively etching the interlayer insulating film to form a contact hole for forming a capacitor; 상기 콘택홀을 포함한 기판상에 폴리실리콘으로 전하저장 전극을 형성하는 단계와;Forming a charge storage electrode of polysilicon on the substrate including the contact hole; 상기 전하저장 전극을 포함한 기판상에 질화막을 증착하고, 블랭킷 식각하여 상기 전하저장 전극의 밑부분에 부분적으로 질화막 스패이서를 형성하는 단계와;Depositing a nitride film on a substrate including the charge storage electrode, and blanket etching to form a nitride film spacer at a bottom of the charge storage electrode; 상기 질화막 스페이서를 포함한 전하저장 전극상에 질화막-산화막으로 이루어진 유전층을 형성하는 단계와;Forming a dielectric layer formed of a nitride film-oxide film on the charge storage electrode including the nitride film spacer; 상기 유전층상에 폴리실리콘을 증착하여 플레이트 전극을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 캐패시터 제조방법.Depositing polysilicon on the dielectric layer to form a plate electrode.
KR1019950019369A 1995-06-30 1995-06-30 Method for manufacturing capacitor of semiconductor device KR100365418B1 (en)

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KR1019950019369A KR100365418B1 (en) 1995-06-30 1995-06-30 Method for manufacturing capacitor of semiconductor device

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KR100365418B1 true KR100365418B1 (en) 2003-02-25

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04360571A (en) * 1991-06-07 1992-12-14 Nec Corp Semiconductor storage device and its manufacture

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04360571A (en) * 1991-06-07 1992-12-14 Nec Corp Semiconductor storage device and its manufacture

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