KR100359155B1 - Method for manufacturing electric charge storage node of semiconductor device - Google Patents

Method for manufacturing electric charge storage node of semiconductor device Download PDF

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Publication number
KR100359155B1
KR100359155B1 KR1019950008147A KR19950008147A KR100359155B1 KR 100359155 B1 KR100359155 B1 KR 100359155B1 KR 1019950008147 A KR1019950008147 A KR 1019950008147A KR 19950008147 A KR19950008147 A KR 19950008147A KR 100359155 B1 KR100359155 B1 KR 100359155B1
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South Korea
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charge storage
conductive layer
storage electrode
semiconductor device
storage node
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KR1019950008147A
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Korean (ko)
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KR960039368A (en
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황준
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: A method for manufacturing an electric charge storage node of a semiconductor device is provided to be capable of increasing the surface of the storage node and improving the reliability of operation by entirely etching a gate electrode. CONSTITUTION: After forming a gate electrode at the upper portion of a semiconductor substrate(1), the gate electrode is entirely etched, so that a step difference between the gate electrode and a sidewall spacer is generated. An interlayer dielectric(7) having an electric charge storage node contact hole(9), is formed at the upper portion of the resultant structure. The electric charge storage node contact hole is filled by depositing a conductive layer(10) on the entire surface of the resultant structure. A nitride pattern(11) is formed on the conductive layer for exposing the predetermined portion of the conductive layer. A thermal oxide layer is formed on the exposed conductive layer. After removing the thermal oxide layer and the nitride pattern, an electric charge storage node is formed by etching the conductive layer using a mask.

Description

반도체소자의 전하저장전극의 제조방법Method for manufacturing charge storage electrode of semiconductor device

본발명은 반도체소자의 전하저장전극 제조방법에 관한 것으로서, 특히 스페이서를 구비하는 게이트전극의 상측을 식각하며 스페이서와 단차가 지게하여 전하저장전극의 표면적을 증기시키거나, 전하저장전극의 상측 일부를 열산화시켜 산화막에 의해 전하저장전극의 상측이 굴곡이 지게하여 정전용량을 증가시켜 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 반도체소자의 전하저장전극의 제조방법에 관한것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a charge storage electrode of a semiconductor device. In particular, the upper side of a gate electrode including a spacer is etched so as to be stepped with the spacer to vaporize the surface area of the charge storage electrode, or The present invention relates to a method for manufacturing a charge storage electrode of a semiconductor device which can be thermally oxidized to cause the upper side of the charge storage electrode to be bent by an oxide film to increase capacitance, thereby improving process yield and reliability of device operation.

최근 반도체 소자의 고집적화 추세에 따라 셀 크기가 감소되어 충분한 정전용량을 갖는 캐패시터를 형성하기가 어려워지고 있다.Recently, due to the trend toward higher integration of semiconductor devices, it is difficult to form capacitors with sufficient capacitance because the cell size is reduced.

특히, 하나의 모스 트랜지스터와 캐패시터로 구성되는 디램 소자에서는 캐패시터의 정전용량을 증가시키기 위하여 유전상수가 높은 물질을 유전막으로 사용하거나, 유전막의 두께를 얇게하거나 또는 전하저장전극의 표면적을 증가시키는 등의 방법이 있다.In particular, in a DRAM device composed of one MOS transistor and a capacitor, a material having a high dielectric constant is used as the dielectric film, a thickness of the dielectric film is increased, or the surface area of the charge storage electrode is increased to increase the capacitance of the capacitor. There is a way.

그러나 이러한 방법들은 모두 각각의 문제점을 가지고 있다.However, all these methods have their own problems.

즉, 높은 유전상수를 갖는 유전물질로는 예를들어 Ta2O5, TiO2또는 SrTiO3등이 연구되고 있으나, 이러한 물질들은 접합 파괴전압등과 같은 신뢰도 및 박막특성등이 확실하게 확인되어 있지 않아 실제소자에 적용하기가 어렵다.That is, for example, Ta 2 O 5 , TiO 2 or SrTiO 3 have been studied as dielectric materials with high dielectric constant, but these materials have not been confirmed with reliability and thin film characteristics such as junction breakdown voltage. It is difficult to apply to the actual device.

또한 유전막 두께를 감소시키는 방법은 소자 동작시 유전막이 파괴되어 캐패시터의 신뢰도에 심각한 영향을 준다.In addition, the method of reducing the dielectric film thickness has a serious effect on the reliability of the capacitor because the dielectric film is destroyed during operation of the device.

종래 기술에 따른 반도체소자의 전하저장전극 제조방법을 살표보면 다음과같다.Looking at the charge storage electrode manufacturing method of the semiconductor device according to the prior art as follows.

먼저, 반도체기판상에 소자분리를 위한 필드산화막과, 게이트산화막 및 다결정실리콘층 패턴으로된 일련의 게이트전극들을 형성하고, 상기 게이트전극의 측벽과 양측의 반도체기판에 산화막 스페이서와 소오스/드레인전극을 형성한다.First, a series of gate electrodes having a field oxide film, a gate oxide film, and a polysilicon layer pattern for device isolation are formed on a semiconductor substrate, and an oxide spacer and a source / drain electrode are formed on sidewalls of the gate electrode and semiconductor substrates on both sides. Form.

그다음 상기 소오스/드레인전극 중 전하저장전극 콘택으로 예정되어 있는 부분을 노출시키는 전하저장전극 콘택홀을 구비하는 층간절연막을 형성한 후, 상기 전하저장전극 콘택홀을 통하여 소오스/드레인전극과 접촉되는 전하저장전극을 다결정 실리콘층 패턴으로 형성한다.Next, an interlayer insulating film having a charge storage electrode contact hole exposing a portion of the source / drain electrode, which is intended as a charge storage electrode contact, is formed, and then the charge is contacted with the source / drain electrode through the charge storage electrode contact hole. The storage electrode is formed in a polycrystalline silicon layer pattern.

그후, 상기 전하저장전극의 표면에 유전막을 도포하고, 상기 구조의 전표면에 플레이트 전극을 형성하여 캐패시터를 완성한다.After that, a dielectric film is coated on the surface of the charge storage electrode, and a plate electrode is formed on the entire surface of the structure to complete the capacitor.

상기와 같은 종래 기술에 따른 반도체소자의 제조방법은 전하저장전극간의 간격을 디자인 룰 이하의 간격으로 감소시키기가 어려워 소자의 고집적화에 장애가 되고, 표면적 증가를 위한 공정이 복잡하여 공정수율이 떨어지는 문제점이 있다.In the method of manufacturing a semiconductor device according to the prior art as described above, it is difficult to reduce the spacing between charge storage electrodes to an interval less than a design rule, which hinders the high integration of the device, and the complexity of the process for increasing the surface area reduces the process yield. have.

본발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본발명의 목적은 게이트전극을 전면 식각하여 스페이서와 단차가 지도록하여 그 상부에 적층되는 전하저장전극의 표면적을 증가시키거나 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 반도체소자의 전하저장전극의 제조방법을 제공함에 있다.The present invention is to solve the above problems, the object of the present invention is to etch the gate electrode in front of the gap between the spacer to increase the surface area of the charge storage electrode stacked on top of the process yield and device operation It is to provide a method of manufacturing a charge storage electrode of a semiconductor device that can improve the reliability.

본발명의 다른 목적은 전하저장전극의 상측 일부를 열산화시켜 굴곡지게하여 공정이 간단하고, 소자의 고집적화에 유리한 반도체소자의 전하저장전극의 제조방법을 제공함에 있다.Another object of the present invention is to provide a method of manufacturing a charge storage electrode of a semiconductor device, which is simple in thermally oxidizing a portion of the upper side of the charge storage electrode to bend, and is advantageous for high integration of the device.

상기와 같은 목적을 달성하기 위한 본발명에 따른 반도체소자의 전하저장전극 제조방법의 특징은, 반도체소자의 전하저장전극의 제조방법에 있어서, 하부구조물 상부에 전하저장전극 콘택홀이 구비된 층간절연막을 형성하는 공정과, 상기 구조의 전표면에 도전층을 형성하여 상기 전하저장전극 콘택홀을 메우는 공정과, 상기 도전층의 일부를 노출시키는 질화막 패턴을 상기 도전층상에 형성하는 공정과, 상기 노출된 도전층에 열산화막을 성장시키는 공정과, 상기 열산화막과 질화막 패턴을 제거하는 공정과, 저하저장건극용 마스크를 사용한 사진식각 공정으로 상기 도전층을 식각하여 전하저장전극을 형성하는 공정을 구비함에 있다.A method of manufacturing a charge storage electrode of a semiconductor device according to the present invention for achieving the above object is, in the method of manufacturing a charge storage electrode of a semiconductor device, an interlayer insulating film provided with a charge storage electrode contact hole on the lower structure Forming a conductive layer on the entire surface of the structure to fill the charge storage electrode contact hole, forming a nitride film pattern exposing a portion of the conductive layer on the conductive layer, and exposing the conductive layer. Growing a thermal oxide film on the conductive layer, removing the thermal oxide film and the nitride film pattern, and forming a charge storage electrode by etching the conductive layer by a photolithography process using a mask for degradation storage electrode. It's in the ship.

이하, 본발명에 따른 반도체소자의 전하저장전극의 제조방법에 관하여 첨부도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a charge storage electrode of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

제 1A 도 내지 제 1D 도는 본발명의 일실시예에 따른 반도체소자의 전하저장전극 제조 공정도이다.1A to 1D are flowcharts of manufacturing a charge storage electrode of a semiconductor device according to an exemplary embodiment of the present invention.

먼저, 반도체기판(1)의 일측에 필드산화막(2)과 게이트산화막(3)을 형성한 후, 상기 게이트산화막(3)과 필드산화막(2)상에 한방향으로 연장된 일련의 게이트전극(4)들을 형성하고, 상기 게이트전극(4)의 측벽 및 양측의 반도체기판(1)에 산화막 스페이서(5)와 엘.디.디(lightly doped drain; LDD) 구조의 소오스/드레인전극(6)을 형성한다. 이때 상기 게이트전극(4)은 다결정실리콘층등의 도전 패턴으로 형성되며, 형성하고자하는 두께 보다 예정된 두께, 예를들어 4000∼5000Å 정도 더 두껍게 형성한다.(제 1A 도 참조).First, the field oxide film 2 and the gate oxide film 3 are formed on one side of the semiconductor substrate 1, and then a series of gate electrodes 4 extending in one direction on the gate oxide film 3 and the field oxide film 2 are formed. ) And source / drain electrodes 6 having an oxide spacer 5 and a lightly doped drain (LDD) structure on sidewalls of the gate electrode 4 and semiconductor substrates 1 on both sides thereof. Form. In this case, the gate electrode 4 is formed of a conductive pattern such as a polysilicon layer, and is formed to have a predetermined thickness thicker than a thickness to be formed, for example, about 4000 to 5000 kPa (see FIG. 1A).

그다음 상기 게이트전극(4)에서 두껍게 형성된 만큼을 전면 이방성 식각하여상기 스페이서(5) 보다 낮게하여 단차가 지게한 후, 상기 구조의 전표면에 산화막이나 산화막-BPSG의 적층막으로 층간절연막(7)을 도포한다.After that, the gate electrode 4 is anisotropically etched as much as the thickness of the gate electrode 4 so as to be lower than the spacer 5 so as to have a step difference. Then, the interlayer insulating film 7 is formed of an oxide film or an oxide film-BPSG on the entire surface of the structure. Apply.

그후, 상기 소오스/트레인전극(5)에서 전하저장전극 콘택으로 예정되어 있는 부분을 노출시키기 위한 제 1 감광막패턴(8)을 층간절연막(7)상에 형성한다. (제 1B 도 참조).A first photosensitive film pattern 8 is then formed on the interlayer insulating film 7 to expose a portion of the source / train electrode 5 which is intended as a charge storage electrode contact. (See also FIG. 1B).

그다음 상기 제 1 감광막패턴(8)에 의해 노출되어 있는 층간절연막(7)을 제거하여 전하저장전극 콘택홀(9)을 형성한 후, 제 1 감광막패턴(8)을 제거하고, 상기 구조의 전표면에 비정질 또는 다결정실리콘층등과 같은 도전층(10)을 형성하여 상기 전하저장전극 콘택홀(9)을 메운다.Then, the interlayer insulating film 7 exposed by the first photoresist pattern 8 is removed to form a charge storage electrode contact hole 9, and then the first photoresist pattern 8 is removed, and the structure of the structure A conductive layer 10 such as an amorphous or polysilicon layer is formed on the surface to fill the charge storage electrode contact hole 9.

그후, 상기 도전층(10)에서 전하지장전극으로 에정되어 있는 부분상에 제 2 감광막패턴(11)을 형성한다. (제 1C 도 참조).Thereafter, a second photosensitive film pattern 11 is formed on the portion of the conductive layer 10 which is etched by the electric field electrode. (See also FIG. 1C).

그다음 상기 제 2 감광막패턴(11)에 의해 노출되어 있는 도전층(10)을 제거하여 전하저장전극 콘택홀(9)을 동하여 소오스/드레인전극(6)과 접촉되는 도전층(10)패턴으로된 전하저장전극(12)을 형성한 후, 제 2 감광막패턴(11)을 제거한다.Next, the conductive layer 10 exposed by the second photoresist layer pattern 11 is removed to move the charge storage electrode contact hole 9 to the conductive layer 10 pattern which is in contact with the source / drain electrode 6. After the formed charge storage electrode 12 is formed, the second photoresist layer pattern 11 is removed.

그후, 상기 전하저장전극(12)의 표면에 유전막(13)을 형성하고, 상기 구조의 전표면에 비정질 또는 다결정실리콘등의 도전물질로 플레이트 전극(14)을 형성한다. 이때 상기 유전막(13)은 산화막이나 질화막등의 단일 절연막이나 산화막-질화막-산회막의 적층 구조로 형성하며, 상기 도전층(10)과 플레이트 전극(14)이 비정질 실리콘층이면 열처리하여 다결정화시킨다. (제 1D 도 참조).Thereafter, a dielectric film 13 is formed on the surface of the charge storage electrode 12, and a plate electrode 14 is formed on the entire surface of the structure by a conductive material such as amorphous or polycrystalline silicon. In this case, the dielectric layer 13 may be formed of a single insulating layer such as an oxide layer or a nitride layer, or a stacked structure of an oxide layer-nitride layer-acid lime layer. If the conductive layer 10 and the plate electrode 14 are amorphous silicon layers, the dielectric layer 13 may be thermally crystallized. . (See also FIG. 1D).

제 2A 도 내지 제 2D 도는 본발명의 다른 실시예에 따른 반도체소자의 전하저장전극 제조공정도이다.2A through 2D are diagrams illustrating a process of manufacturing a charge storage electrode of a semiconductor device according to another exemplary embodiment of the present invention.

먼저, 반도체기판(1)상에 필드산화막(2)과 게이트산화막(3)을 형성하고, 게이트전극(4)과 스페이서(5) 및 소오스/드레인전극(6)을 형성하여 모스 전계효과 트랜지스터를 형성하고, 상기 소오스/드레인전극(5)에서 전하저장전극 콘택으로 예정되어 있는 부분을 노출시키기 위한 전하저장전극 콘택홀(9)을 구비하는 층간절연막(7)을 도포한다.First, a field oxide film 2 and a gate oxide film 3 are formed on the semiconductor substrate 1, and a gate electrode 4, a spacer 5, and a source / drain electrode 6 are formed to form a MOS field effect transistor. And an interlayer insulating film 7 having a charge storage electrode contact hole 9 for exposing a portion of the source / drain electrode 5 to be a charge storage electrode contact.

그다음 상기 구조의 전표면에 비정질이나 다결정실리콘층등과 같은 도전층(10)을 형성하여 상기 전하저장전극 콘택홀(9)을 메우고, 상기 도전층(10) 상에 화학기상증착(chemical vapor deposition; 이하 CVD라 칭함) 방법으로 질화막(15)을 도포한다. 이때 상기 도전층(10)은 형성하고자하는 전하저장전극의 두께 보다 예정된 정도, 예를들어 1000∼2000Å 정도 더 두껍게 형성한다.Then, a conductive layer 10 such as an amorphous or polysilicon layer is formed on the entire surface of the structure to fill the charge storage electrode contact hole 9 and chemical vapor deposition on the conductive layer 10. The nitride film 15 is coated by the following method (CVD). In this case, the conductive layer 10 is formed to be thicker than a thickness of the charge storage electrode to be formed, for example, about 1000 to 2000 Å thicker.

그후, 상기 질화막(15)의 일부를 노출시키는 제 1 감광막패턴(8)을 형성한다. 상기 제 1 감광막패턴(8)은 디자인룰이 허용하는 한도내에서 최소의 크기로하여 되도록 여러곳의 질화막(15)이 노출되도록 한다. (제 2A 도 참조).Thereafter, a first photosensitive film pattern 8 for exposing a part of the nitride film 15 is formed. The first photoresist layer pattern 8 is exposed to a plurality of nitride layers 15 so as to have a minimum size within the limits allowed by the design rule. (See also FIG. 2A).

그다음 상기 제 1 감광막패턴(8)에 의해 노출되어 있는 질화막(15)을 제거하여 도전층(10)을 노출시키는 질화막(15) 패턴을 형성하고, 상기 제 1 감광막패턴(8)을 제거한다.Next, the nitride film 15 exposed by the first photosensitive film pattern 8 is removed to form the nitride film 15 pattern exposing the conductive layer 10, and the first photosensitive film pattern 8 is removed.

그후, 상기 질화막(15)을 열산화 마스크로 사용하여 노출되어 있는 도전층(10)의 추가로 형성된 두께 만큼을 열산화시켜 예정된 두께, 예를들어 2500∼6000Å 정도 두께의 열산화막(16)을 형성한다. 이때 상기 도전층(10)의 전 두께가 산화되지 않도록한다. (제 2B 도 참조).Thereafter, using the nitride film 15 as a thermal oxidation mask, the thermal oxidation film 16 having a predetermined thickness, for example, a thickness of about 2500 to 6000 kPa is thermally oxidized by the additional thickness of the conductive layer 10 exposed. Form. At this time, the entire thickness of the conductive layer 10 is not oxidized. (See also FIG. 2B).

그다음 상기 질화막(15)과 열산화막(16)을 제거한 후, 상기 남아 있는 도전층(10)에서 전하저장전극으로 예정되어 있는 부분상에 제 2 감광막패턴(11)을 형성한다. (제 2C 도 참조).After the nitride film 15 and the thermal oxide film 16 are removed, a second photosensitive film pattern 11 is formed on a portion of the remaining conductive layer 10 that is intended as a charge storage electrode. (See also FIG. 2C).

그후, 상기 제 2 감광막패턴(11)을 마스크로 노출되어있는 도전층(10)을 제거하여 전하저장전극 콘택홀(9)을 통하여 소오스/드레인전극(6)과 접촉되는 도전층(10)패턴으로된 전하저장전극(12)을 형성한 후, 제 2 감광막패턴(11)을 제거하고, 상기 전하저장전극(12)의 표면에 유전막(13)을 형성하고, 상기 구조의 전표면에 다결정실리콘등의 도전물질로 플레이트 전극(14)을 형성한다. (제 2D 도 참조).Thereafter, the conductive layer 10 exposing the second photoresist layer pattern 11 as a mask is removed to contact the source / drain electrode 6 through the charge storage electrode contact hole 9. After the charge storage electrode 12 is formed, the second photoresist layer pattern 11 is removed, a dielectric film 13 is formed on the surface of the charge storage electrode 12, and polycrystalline silicon is formed on the entire surface of the structure. The plate electrode 14 is formed of a conductive material such as the same. (See also 2D).

이상에서 설명한 바와 같이, 본발명에 따른 반도체소자의 전하저장전극 제조방법은 게이트전극을 전면 식각하여 산화막 스페이서와 단차가 지도록한 후, 후속공정을 진행하여 전하저장전극이 굴곡이 지도록하거나, 전하저장전극의 상측 일부를 열산화시켜 표면이 굴곡지게하여 전하저장전극의 정진용량을 증가시켰으므로, 소자동작의 신뢰성이 향상되고, 공정이 간단하여 공정 수율이 향상되는 이점이 있다.As described above, in the method of manufacturing a charge storage electrode of a semiconductor device according to the present invention, the gate electrode is etched entirely to form a step with an oxide spacer, and then the subsequent process is performed so that the charge storage electrode is curved or charge storage. Since the upper portion of the electrode is thermally oxidized to make the surface bent to increase the forward capacitance of the charge storage electrode, the reliability of the device operation is improved, the process is simple, and the process yield is improved.

제 1A 도 내지 제 1D 도는 본발명의 일실시예에 따른 반도체소자의 제조공정도.1A to 1D are manufacturing process diagrams of a semiconductor device according to one embodiment of the present invention.

제 2A 도 내지 제 2D 도는 본발명의 다른 실시예에 따른 반도체소자의 제조공정도.2A to 2D are manufacturing process diagrams of a semiconductor device according to another embodiment of the present invention.

〈 도면의 주요부분에 대한 부호의 설명 〉<Description of the reference numerals for the main parts of the drawings>

1 : 반도체기판 2 : 필드산화막1: semiconductor substrate 2: field oxide film

3 : 게이트산화막 4 : 게이트전극3: gate oxide film 4: gate electrode

5 : 산화막 스페이서 6 : 소오스/드레인전극5 oxide film spacer 6 source / drain electrode

7 : 층간절연막 8 : 제 1 감광막패턴7: interlayer insulating film 8: first photosensitive film pattern

9 : 전하저장전극 콘택홀 10 : 도전층9: charge storage electrode contact hole 10: conductive layer

11 : 제 2 감광막패턴 12 : 전하저장전극11 second photosensitive film pattern 12 charge storage electrode

13 : 유전막 14 : 플레이트 전극13 dielectric film 14 plate electrode

15 : 질화막 16 : 열산화막15: nitride film 16: thermal oxide film

Claims (3)

반도체소자의 전하저장전극의 제조방법에 있어서,In the method of manufacturing a charge storage electrode of a semiconductor device, 하부구조물 상부에 전하저장전극 콘택홀이 구비된 층간절연막을 형성하는 공정과,Forming an interlayer insulating film having a charge storage electrode contact hole on the lower structure; 상기 구조의 전표면에 도전층을 형성하여 상기 전하저장전극 콘택홀을 메우는 공정과,Forming a conductive layer on the entire surface of the structure to fill the charge storage electrode contact hole; 상기 도전층의 일부를 노출시키는 질화막 패턴을 상기 도전층상에 형성하는 공정과,Forming a nitride film pattern on the conductive layer to expose a portion of the conductive layer; 상기 노출된 도전층에 열산화막을 성장시키는 공정과,Growing a thermal oxide film on the exposed conductive layer; 상기 열산화막과 질화막 패턴을 제거하는 공정과,Removing the thermal oxide film and the nitride film pattern; 저하저장건극용 마스크를 사용한 사진식각 공정으로 상기 도전층을 식각하여 전하저장전극을 형성하는 공정을 포함하는 반도체소자의 전하저장전극의 제조방법.A method of manufacturing a charge storage electrode of a semiconductor device comprising the step of etching the conductive layer to form a charge storage electrode by a photolithography process using a mask for degradation storage electrode. 제 1 항에 있어서,The method of claim 1, 상기 도전층을 열산화되는 두께를 고려하여 1000∼2000Å 더 두껍게 형성하는 것을 특징으로 하는 반도체소자의 전하저장전극의 제조방법.A method for manufacturing a charge storage electrode of a semiconductor device, characterized in that the conductive layer is formed to be 1000 ~ 2000∼ thicker in consideration of the thermal oxidation thickness. 제 1 항에 있어서,The method of claim 1, 상기 열산화막의 두께를 2500∼6000Å로 형성하는 것을 특징으로 하는 반도체소자의 전하저장전극의 제조방법.A method of manufacturing a charge storage electrode of a semiconductor device, characterized in that the thickness of the thermal oxide film is formed to 2500 ~ 6000Å.
KR1019950008147A 1995-04-07 1995-04-07 Method for manufacturing electric charge storage node of semiconductor device KR100359155B1 (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0414866A (en) * 1990-05-08 1992-01-20 Nec Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0414866A (en) * 1990-05-08 1992-01-20 Nec Corp Semiconductor device

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