KR100358568B1 - A method for fabricating of a semiconductor device - Google Patents
A method for fabricating of a semiconductor device Download PDFInfo
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- KR100358568B1 KR100358568B1 KR1019990066390A KR19990066390A KR100358568B1 KR 100358568 B1 KR100358568 B1 KR 100358568B1 KR 1019990066390 A KR1019990066390 A KR 1019990066390A KR 19990066390 A KR19990066390 A KR 19990066390A KR 100358568 B1 KR100358568 B1 KR 100358568B1
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- polysilicon
- word line
- interlayer insulating
- bit line
- forming
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 불순물 접합영역이 형성된 반도체기판 상부에 폴리실리콘, 마스크산화막, 마스크질화막의 적층구조를 형성하고 상기 적층구조를 비트라인 마스크를 이용한 사진식각공정으로 패터닝한 다음, 그 측벽에 질화막 스페이서가 구비되는 비트라인을 형성하고 전체표면상부에 워드라인용 폴리실리콘을 형성한 다음, 전체표면상부에 층간절연막을 형성하고 상기 층간절연막을 평탄화식각하여 상기 워드라인용 폴리실리콘을 노출시킨 다음, 상기 층간절연막과 워드라인용 폴리실리콘을 순차적으로 식각하여 워드라인을 형성하는 공정으로 워드라인 및 비트라인의 특성 열화 없이 제조공정을 용이하게 실시하여 반도체소자의 고집적화를 가능하게 하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein a stacked structure of polysilicon, a mask oxide film, and a mask nitride film is formed on a semiconductor substrate on which an impurity junction region is formed, and the stacked structure is patterned by a photolithography process using a bit line mask. Next, a bit line having a nitride film spacer is formed on the sidewall, and a polysilicon for word line is formed on the entire surface. Then, an interlayer insulating film is formed on the entire surface, and the interlayer insulating film is planarized to be etched. After the silicon is exposed, the interlayer insulating film and the polysilicon for the word line are sequentially etched to form a word line. Thus, the manufacturing process can be easily performed without deteriorating the characteristics of the word line and the bit line, thereby enabling high integration of semiconductor devices. It is a technique to do.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 비트라인을 먼저 형성하고 후속공정으로 워드라인을 형성하여 소자의 높이를 낮춤으로써 비트라인 사이의 공간으로 셀 문턱전압 ( cell Vt ) 을 결정하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, a technique for determining a cell threshold voltage (cell Vt) into a space between bit lines by first forming a bit line and then forming a word line in a subsequent process to reduce the height of the device. It is about.
도시되지않았으나, 종래기술에 따른 반도체소자의 제조방법은 다음과 같다.Although not shown, a method of manufacturing a semiconductor device according to the prior art is as follows.
먼저, 반도체기판 상부에 활성영역을 정의하는 소자분리막을 형성한다.First, an isolation layer defining an active region is formed on the semiconductor substrate.
그리고, 상기 활성영역에 워드라인을 형성하고 그 상부를 평탄화시키는 층간절연막을 형성한다.A word line is formed in the active region and an interlayer insulating film is formed to planarize the upper portion.
그리고, 상기 층간절연막을 통하여 상기 반도체기판의 콘택 예정 영역을 노출시키는 비트라인 콘택홀을 형성한다.A bit line contact hole for exposing a contact predetermined region of the semiconductor substrate is formed through the interlayer insulating layer.
그리고, 상기 콘택홀을 매립하는 비트라인 콘택플러그를 형성한다.A bit line contact plug is formed to fill the contact hole.
그 다음, 상기 비트라인 콘택플러그에 접속되는 비트라인을 형성한다.A bit line is then formed that is connected to the bit line contact plug.
이때, 비트라인 형성공정시 별도의 비트라인 콘택플러그를 형성하지 않고 상기 비트라인 콘택홀을 매립하지 않고 바로 형성할 수도 있다.In this case, the bit line forming process may be performed without forming a separate bit line contact plug and without filling the bit line contact hole.
상기한 종래기술에서, 워드라인인 폴리1 사이의 공간이 비트라인인 폴리2 의 콘택 면적이 된다.In the above-described prior art, the space between poly1 which is a word line becomes the contact area of poly2 which is a bit line.
그리고, 폴리1 사이의 공간이 적으면 산화막이 제대로 매립되지않아 빈 공간이 생기게 되는 보이드 ( void ) 라는 것이 발생한다.If the space between the poly 1s is small, voids occur because the oxide film is not buried properly and an empty space is generated.
이것은 후속공정인 랜딩 플러그 폴리 ( landing plug poly, LPP ) 증착공정시 서로 브릿지가 발생하는 결과를 가져왔다.This resulted in the formation of bridges with each other during the subsequent landing plug poly (LPP) deposition process.
그리고, 폴리1 사이의 공간이 커지면 그 만큼 폴리1 의 폭이 작아지므로 셀 Vt 가 너무 작아지거나 폴리1 이 끊어지는 결과를 가져온다.As the space between the poly 1s increases, the width of the poly 1s decreases, which results in the cell Vt becoming too small or the poly 1s breaking.
즉, 폴리1 사이의 공간이 작아지면 폴리2 콘택 저항이 커지거나 낫 오픈 ( not open ) 되는 현상이 발생하고, 공간이 커지면 셀 문턱전압이 높아지거나 라인( line ) 자체가 끊어지는 현상이 발생한다.That is, when the space between poly 1 becomes smaller, the poly 2 contact resistance becomes larger or not open, and when the space becomes larger, the cell threshold voltage increases or the line itself breaks. .
상기한 바와같이 종래기술에 따른 반도체소자의 제조방법은, 워드라인 형성공정시 워드라인 간의 공간이 넓거나 좁게 형성되어 상기 워드라인의 특성이 열화되거나 상기 비트라인의 콘택공정이 어렵게 되는 현상으로 인하여 반도체소자의 특성 및 신뢰성을 저하시키는 문제점이 있다.As described above, the semiconductor device manufacturing method according to the related art is formed by a wide or narrow space between word lines during the word line forming process, resulting in deterioration of characteristics of the word line or difficulty in contacting the bit line. There is a problem of lowering the characteristics and reliability of the semiconductor device.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 반도체기판 상부에 비트라인을 형성하고 그 상부에 워드라인용 도전층을 형성한 다음, 그 상부를 평탄화시키는 층간절연막을 형성하고 패터닝공정으로 워드라인을 형성함으로써 별도의 비트라인 콘택공정이 불필요하여 반도체소자의 제조를 용이하게 하고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.The present invention, in order to solve the above problems of the prior art, to form a bit line on the semiconductor substrate, and to form a conductive layer for the word line on the upper portion, then to form an interlayer insulating film to planarize the upper portion and the word in the patterning process It is an object of the present invention to provide a method for manufacturing a semiconductor device, by forming a line, so that a separate bit line contact process is not required, thereby facilitating the manufacture of the semiconductor device, and thereby enabling high integration of the semiconductor device.
도 1a 내지 도 1g 는 본 발명의 실시예에 따른 반도체소자의 제조방법을 도시한 단면도.1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11 : 반도체기판 13 : 소자분리막11: semiconductor substrate 13: device isolation film
15 : 제1감광막패턴 17 : 불순물 접합영역15: first photosensitive film pattern 17: impurity junction region
19 : 비트라인용 폴리실리콘 21 : 마스크산화막19: polysilicon for bit line 21: mask oxide film
23 : 제2감광막패턴 25 : 마스크질화막23: second photosensitive film pattern 25: mask nitride film
26 : 질화막 스페이서 27 : 워드라인용 폴리실리콘26: nitride film spacer 27: polysilicon for word line
29 : 층간절연막29: interlayer insulating film
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 제조방법은,불순물 접합영역이 형성된 반도체기판 상부에 폴리실리콘, 마스크산화막, 마스크질화막의 적층구조를 형성하는 공정과,비트라인 마스크를 이용한 사진식각공정으로 상기 적층구조를 패터닝하고 그 측벽에 질화막 스페이서가 구비되는 비트라인을 형성하는 공정과,전체표면상부에 워드라인용 폴리실리콘을 형성하는 공정과,전체표면상부에 층간절연막을 형성하는 공정과,상기 층간절연막을 평탄화식각하여 상기 워드라인용 폴리실리콘을 노출시키는 공정과,In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes: forming a stacked structure of a polysilicon, a mask oxide film, and a mask nitride film on an upper portion of a semiconductor substrate on which an impurity junction region is formed; and photolithography using a bit line mask Patterning the stacked structure and forming a bit line having a nitride spacer on a sidewall thereof, forming a polysilicon for word lines over the entire surface, and forming an interlayer insulating film over the entire surface; And planarizing etching the interlayer insulating layer to expose the polysilicon for the word line,
상기 층간절연막과 워드라인용 폴리실리콘을 순차적으로 식각하여 워드라인을 형성하는 공정을 포함하는 것을 특징으로한다.And forming a word line by sequentially etching the interlayer insulating layer and the polysilicon for the word line.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1g 는 본 발명의 실시예에 따른 반도체소자의 제조방법을 도시한 단면도이다.1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
먼저, 반도체기판(11)에 활성영역을 정의하는 소자분리막(13)을 형성하고, 상기 반도체기판(11) 상부에 제1감광막패턴(15)을 형성한다.First, an isolation layer 13 defining an active region is formed on the semiconductor substrate 11, and a first photoresist layer pattern 15 is formed on the semiconductor substrate 11.
이때, 상기 제1감광막패턴(15)은 불순물 접합영역을 형성하기 위한 것이다. (도 1a)In this case, the first photoresist layer pattern 15 is for forming an impurity junction region. (FIG. 1A)
그 다음, 상기 제1감광막패턴(15)을 마스크로 하여 상기 반도체기판(11)에 불순물을 이온주입하여 상기 반도체기판(1) 상측 일부에 불순물 접합영역(17)을 형성한다. (도 1b)Subsequently, impurities are implanted into the semiconductor substrate 11 using the first photoresist pattern 15 as a mask to form an impurity junction region 17 on a portion of the upper side of the semiconductor substrate 1. (FIG. 1B)
그리고, 상기 제1감광막패턴(15)을 제거하고 상기 반도체기판(11) 상부에 비트라인용 폴리실리콘(19), 마스크산화막(21) 및 마스크질화막(25)을 순차적으로 적층하고 그 상부에 제2감광막패턴(23)을 형성한다.Then, the first photoresist layer pattern 15 is removed, and the polysilicon 19, the mask oxide layer 21, and the mask nitride layer 25 for bit lines are sequentially stacked on the semiconductor substrate 11, and the first photoresist layer pattern 15 is sequentially stacked on the semiconductor substrate 11. The two photosensitive film patterns 23 are formed.
이때, 상기 제2감광막패턴(23)은 비트라인 마스크(도시안됨)를 이용한 노광 및 현상공정으로 형성한다. (도 1c)In this case, the second photoresist layer pattern 23 is formed by an exposure and development process using a bit line mask (not shown). (FIG. 1C)
그 다음, 상기 제2감광막패턴(23)을 마스크로하여 상기 마스크질화막(25),마스크산화막(21) 및 비트라인용 폴리실리콘(19)을 순차적으로 식각한다.Next, the mask nitride film 25, the mask oxide film 21, and the bit line polysilicon 19 are sequentially etched using the second photoresist pattern 23 as a mask.
그리고, 상기 제2감광막패턴(23)을 제거한다.In addition, the second photoresist layer pattern 23 is removed.
그 다음, 상기 비트라인용 폴리실리콘(19), 마스크산화막(21) 및 마스크질화막(23)의 적층구조 측벽에 절연막 스페이서(26)를 형성하여 반도체기판(11) 상부에 비트라인을 형성한다.이때, 상기 절연막 스페이서(26)는 질화막을 일정두께 형성하고 이를 전면식각하여 형성한 것이다. (도 1d)Next, an insulating film spacer 26 is formed on the sidewalls of the multilayer structure of the bit line polysilicon 19, the mask oxide film 21, and the mask nitride film 23 to form a bit line on the semiconductor substrate 11. In this case, the insulating layer spacer 26 is formed by forming a nitride film with a predetermined thickness and etching the entire surface thereof. (FIG. 1D)
그리고, 상기 반도체기판의 워드라인 형성영역에만 셀 문턱전압을 조절할 수 있는 불순물을 임플란트 ( implant ) 한다.In addition, an impurity capable of adjusting a cell threshold voltage is implanted only in the word line forming region of the semiconductor substrate.
그리고, 전체표면상부에 워드라인용 폴리실리콘(27)을 일정두께 형성한다. (도 1e)Then, polysilicon 27 for word lines is formed on the entire surface at a constant thickness. (FIG. 1E)
그리고, 전체표면상부에 층간절연막(29)을 형성한다. 이때, 상기 층간절연막(29)은 BPSG 와 같이 플로우가 잘되는 절연물질로 형성한다.Then, an interlayer insulating film 29 is formed over the entire surface. At this time, the interlayer insulating film 29 is formed of an insulating material that flows well, such as BPSG.
그 다음, 상기 워드라인용 폴리실리콘(27)을 노출시키는 화학기계연마 ( chemical mechenical polishing, 이하에서 CMP 이라 함 ) 공정으로 상기 층간절연막(29)을 평탄화식각한다.Next, the interlayer insulating layer 29 is planarized by a chemical mechanical polishing (hereinafter referred to as CMP) process in which the polysilicon 27 for word lines is exposed.
그리고, 상기 평탄화된 구조 상부에 제3감광막패턴(31)을 형성한다. 이때, 상기 제3감광막패턴(31)은 워드라인 마스크(도시안됨)를 이용한 노광 및 현상공정으로 형성한다. (도 1f)A third photoresist pattern 31 is formed on the planarized structure. In this case, the third photoresist pattern 31 is formed by an exposure and development process using a word line mask (not shown). (FIG. 1F)
그 다음, 상기 제3감광막패턴(31)을 마스크로 하고 상기 마스크질화막(25)을 식각장벽으로 하여 상기 층간절연막(29)과 워드라인용 폴리실리콘(27)을 식각하여 상기 워드라인을 형성한다. (도 1g)Next, the word line is formed by etching the interlayer insulating layer 29 and the word line polysilicon 27 by using the third photoresist layer pattern 31 as a mask and the mask nitride layer 25 as an etch barrier. . (Fig. 1g)
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 제조방법은, 반도체기판 상부에 비트라인을 형성하고 그 주변에 질화막으로 절연특성을 향상시킨 다음, 전체표면상부에 워드라인용 폴리실리콘과 평탄화된 층간절연막을 형성하고 이들을 워드라인 마스크를 이용하여 패터닝함으로써 워드라인 사이의 공간 부족으로 인한 보이드의 발생을 방지하고 임계크기 ( critical dimension ) 의 균일성을 향상시키며, 상기 비트라인 사이의 공간으로 워드라인의 폭을 조절할 수 있어 반도체소자의 제조공정을 용이하게 실시할 수 있도록 하고 그에 따른 반도체소자의 고집적화를 가능하게 하는 효과를 제공한다.As described above, in the method of manufacturing a semiconductor device according to the present invention, a bit line is formed on an upper surface of a semiconductor substrate, and an insulating property is improved by a nitride film around the semiconductor substrate, and then polysilicon and a planarized interlayer are formed on the entire surface. By forming an insulating film and patterning them using a word line mask, it prevents the generation of voids due to lack of space between word lines, improves the uniformity of critical dimensions, and improves the space between the bit lines. The width can be adjusted to facilitate the manufacturing process of the semiconductor device, thereby providing an effect of enabling high integration of the semiconductor device.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH01201940A (en) * | 1988-02-08 | 1989-08-14 | Toshiba Corp | Formation of electrode wiring of semiconductor device |
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| JPH01201940A (en) * | 1988-02-08 | 1989-08-14 | Toshiba Corp | Formation of electrode wiring of semiconductor device |
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