KR100348313B1 - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR100348313B1 KR100348313B1 KR1020000005193A KR20000005193A KR100348313B1 KR 100348313 B1 KR100348313 B1 KR 100348313B1 KR 1020000005193 A KR1020000005193 A KR 1020000005193A KR 20000005193 A KR20000005193 A KR 20000005193A KR 100348313 B1 KR100348313 B1 KR 100348313B1
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- layer
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- semiconductor device
- forming
- polysilicon layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 29
- 229920005591 polysilicon Polymers 0.000 claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 claims abstract description 18
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 12
- 230000003746 surface roughness Effects 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000007789 gas Substances 0.000 claims description 20
- 150000002500 ions Chemical class 0.000 claims description 12
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 8
- 229910052786 argon Inorganic materials 0.000 claims description 7
- 239000000460 chlorine Substances 0.000 claims description 7
- 229910052801 chlorine Inorganic materials 0.000 claims description 3
- 125000001309 chloro group Chemical group Cl* 0.000 claims description 3
- 239000011261 inert gas Substances 0.000 claims description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 2
- 230000001419 dependent effect Effects 0.000 claims description 2
- 125000001153 fluoro group Chemical group F* 0.000 claims 1
- 239000007772 electrode material Substances 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 7
- 239000010408 film Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Plasma & Fusion (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 게이트전극 물질로 사용되는 폴리실리콘의 표면 균일도를 기존의 장비만으로도 충분한 수준까지 얻을 수 있는 반도체 소자의 제조방법을 제공하기 위한 것으로, 본 발명의 반도체 소자 제조방법은 반도체 기판상에 게이트 절연층을 형성하고, 상기 게이트 절연층상에 폴리실리콘층을 형성하는 공정과, 플라즈마를 이용한 식각 공정으로 상기 폴리실리콘층 표면의 거칠기를 개선시키는 공정과, 표면 거칠기가 개선된 상기 폴리실리콘층상에 실리사이드층을 형성하는 공정과, 상기 실리사이드층 및 상기 폴리실리콘층을 식각하여 게이트 전극을 형성하는 공정과, 고농도의 소오스/드레인 영역을 형성하는 공정을 포함하여 이루어지는 것을 특징으로 한다.The present invention is to provide a method for manufacturing a semiconductor device that can obtain a surface uniformity of polysilicon used as a gate electrode material to a sufficient level with existing equipment, the method of manufacturing a semiconductor device of the present invention is a gate insulation on a semiconductor substrate Forming a layer, forming a polysilicon layer on the gate insulating layer, improving the roughness of the surface of the polysilicon layer by an etching process using plasma, and a silicide layer on the polysilicon layer having improved surface roughness Forming a gate electrode by etching the silicide layer and the polysilicon layer, and forming a high concentration source / drain region.
Description
본 발명은 반도체 소자에 관한 것으로 특히, 게이트 전극 물질의 표면 균일도를 향상시켜 소자의 신뢰성을 향상시킬 수 있는 반도체 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a method of manufacturing a semiconductor device capable of improving the surface uniformity of a gate electrode material to improve the reliability of the device.
반도체 소자가 고 집적화 및 저 전력화됨에 따라 게이트 유전막의 두께 또한얇아지는 추세에 있다.As semiconductor devices become more integrated and lower in power, the thickness of the gate dielectric layer also tends to become thinner.
그러함에도 불구하고 기존에 범용적으로 사용해오던 폴리실리콘의 표면 불균일성은 게이트 유전막에 데미지(damage)를 가하게 될 뿐만 아니라 폴리실리콘 위에 형성되는 실리사이드의 표면 균일도에 영향을 미치게된다(C.T. Gabriel, "Gate oxide damage from polysilicon etching", J.Vac. Sci. Tech. B, vol.9, no.2, p370, 1991).Nevertheless, the surface non-uniformity of polysilicon, which has been used in general, not only damages the gate dielectric layer but also affects the surface uniformity of the silicide formed on the polysilicon (CT Gabriel, "Gate oxide" damage from polysilicon etching ", J. Vac. Sci. Tech. B, vol. 9, no. 2, p370, 1991).
특히, 하부 폴리실리콘 대신에 SiGe등으로 대치되는 시점에서 SiGe의 증착으로 인해 발생하는 극심한 표면 거칠기(roughness)를 극복하기 위한 많은 연구가 이루어지고 있다(미국특허 US593560, Method to fabricate the thin film transistor, 1997).In particular, many studies have been conducted to overcome the extreme surface roughness caused by the deposition of SiGe at the time when it is replaced by SiGe instead of lower polysilicon (US Patent US593560, Method to fabricate the thin film transistor, 1997).
그러나 이러한 방법은 CMP등을 이용하므로써, CMP의 단점인 불균일성 및 에치레이트(etchrate)를 개선할 수 없으며, 새로운 단계를 추가하는 것으로 새로운 장비 및 이에 따른 비용이 증가하게 된다.However, this method can not improve the nonuniformity and etchrate which is a disadvantage of CMP by using CMP, etc., and by adding a new step, new equipment and its cost increase.
이하, 첨부된 도면을 참조하여 종래 기술에 따른 반도체 소자 제조방법을 설명하기로 한다.Hereinafter, a semiconductor device manufacturing method according to the related art will be described with reference to the accompanying drawings.
도 1a 내지 1d는 종래 기술에 따른 반도체 소자 제조방법을 설명하기 위한 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
종래에는 UHV/CVD(Ultrahigh vacuum chemical vapor deposition) 시스템은 별도의 열처리 단계를 거치지 않고 550℃이하의 낮은 온도에서 Si나 SiGe를 성장시키기 위해 사용된다.Conventionally, UHV / CVD (Ultrahigh vacuum chemical vapor deposition) systems are used to grow Si or SiGe at low temperatures of 550 ° C. or less without undergoing a separate heat treatment step.
즉, 도 1a에 도시한 바와 같이, 반도체 기판(11)상에 채널물질(12)을 형성한 후, CMP(Chemical Mechanical Polishing)공정을 이용하여 표면 거칠기를 감소시킨다.That is, as shown in FIG. 1A, after forming the channel material 12 on the semiconductor substrate 11, the surface roughness is reduced by using a chemical mechanical polishing (CMP) process.
이때, 상기 채널물질(12)은 UHV/CVD시스템을 이용하여 실리콘(Si) 또는 SiGe을 증착한다.At this time, the channel material 12 deposits silicon (Si) or SiGe using a UHV / CVD system.
즉, UHV/CVD 시스템에서 성장된 Si나 SiGe는 표면 모폴로지가 좋지 않으므로 CMP공정을 이용하여 Si나 SiGe의 표면 거칠기를 감소시켜 주어야 한다.That is, since Si or SiGe grown in UHV / CVD system has poor surface morphology, the surface roughness of Si or SiGe should be reduced by using CMP process.
이후, 도 1b에 도시한 바와 같이, 상기 채널 물질(12)을 포함한 기판상에 게이트 유전막(13)을 형성하고, 상기 게이트 유전막(13)상에 UHV/CVD시스템을 이용하여 폴리실리콘 또는 SiGe를 증착하는 것에 의해 게이트 전극(14)을 형성한다.Thereafter, as shown in FIG. 1B, a gate dielectric layer 13 is formed on a substrate including the channel material 12, and polysilicon or SiGe is formed on the gate dielectric layer 13 using a UHV / CVD system. The gate electrode 14 is formed by vapor deposition.
이어, 도 1c에 도시한 바와 같이, 게이트 전극(14)을 포함한 전면에 실리콘 산화막(15)을 증착한 후, 이방성 플라즈마 식각을 수행하여 게이트 전극(14) 양측면에는 측벽(15a)을 형성하고, 상기 게이트 전극(14) 하부의 채널물질(12) 및 그 양측의 기판(11)을 노출시킨다.Subsequently, as shown in FIG. 1C, after the silicon oxide film 15 is deposited on the entire surface including the gate electrode 14, anisotropic plasma etching is performed to form sidewalls 15a on both sides of the gate electrode 14. The channel material 12 under the gate electrode 14 and the substrate 11 on both sides thereof are exposed.
이어, 도 1d에 도시한 바와 같이, 노출된 부위에 고농도의 소오스/드레인 영역을 형성한 후, 상기 게이트 전극(14)을 포함한 전면에 패시베이션막(16)을 형성한다.Subsequently, as shown in FIG. 1D, a high concentration source / drain region is formed in the exposed portion, and then a passivation film 16 is formed on the entire surface including the gate electrode 14.
마지막으로 게이트 전극(14) 및 소오스/드레인 영역이 노출되도록 콘택홀을 형성한 후, 콘택홀을 통해 연결되도록 메탈(17)층을 형성하면 종래 기술에 따른 반도체 소자 제조공정이 완료된다.Finally, after forming the contact hole to expose the gate electrode 14 and the source / drain region, and then forming the metal 17 layer to be connected through the contact hole, the semiconductor device manufacturing process according to the prior art is completed.
그러나 상기와 같은 반도체 소자 제조방법은 다음과 같은 문제점이 있었다.However, the semiconductor device manufacturing method as described above has the following problems.
표면의 거칠기를 제거하기 위해 CMP공정을 이용하므로, CMP공정의 단점인 균일도 및 식각율을 개선할 수 없으며, CMP공정에 따른 장비추가 및 그에 따른 비용이 추가되는 문제점이 있었다.Since the CMP process is used to remove the roughness of the surface, uniformity and etching rate, which are disadvantages of the CMP process, cannot be improved, and there is a problem in that additional equipment and cost are added according to the CMP process.
본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 안출한 것으로, 기존의 장비를 사용하여 폴리실리콘의 표면 균일도를 충분한 수준까지 얻을 수 있는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems of the prior art, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can obtain the surface uniformity of polysilicon to a sufficient level using existing equipment.
도 1a 내지 1d는 종래 기술에 따른 반도체 소자 제조방법을 설명하기 위한 공정단면도1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the related art.
도 2a 내지 2d는 본 발명에 따른 반도체 소자 제조방법을 설명하기 위한 공정단면도2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 게이트절연층21 semiconductor substrate 22 gate insulating layer
23 : 폴리실리콘층 24 : 실리사이드층23 polysilicon layer 24 silicide layer
25 : 감광막 26 : 패시베이션층25 photosensitive film 26 passivation layer
27,27a : 소오스/드레인 영역27,27a: source / drain regions
상기의 목적을 달성하기 위한 본 발명 반도체 소자의 제조방법은 반도체 기판상에 게이트 절연층을 형성하고, 상기 게이트 절연층상에 폴리실리콘층을 형성하는 공정과, 플라즈마를 이용한 식각 공정으로 상기 폴리실리콘층 표면의 거칠기를 개선시키는 공정과, 표면 거칠기가 개선된 상기 폴리실리콘층상에 실리사이드층을 형성하는 공정과, 상기 실리사이드층 및 상기 폴리실리콘층을 식각하여 게이트 전극을 형성하는 공정과, 고농도의 소오스/드레인 영역을 형성하는 공정을 포함하여 이루어지는 것을 특징으로 한다.The method of manufacturing a semiconductor device of the present invention for achieving the above object is a process for forming a gate insulating layer on a semiconductor substrate, a polysilicon layer on the gate insulating layer, and the etching process using a plasma, the polysilicon layer Improving the surface roughness, forming a silicide layer on the polysilicon layer having improved surface roughness, etching the silicide layer and the polysilicon layer to form a gate electrode, and a high concentration of source / And a step of forming a drain region.
이하, 본 발명 반도체 소자 제조방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a method of manufacturing a semiconductor device of the present invention will be described with reference to the accompanying drawings.
먼저, 본 발명은 플라즈마(plasma)를 사용하여 트랜지스터의 게이트 물질로 널리 사용되는 폴리실리콘의 표면 거칠기를 개선하기 위한 것이다.First, the present invention is to improve the surface roughness of polysilicon which is widely used as a gate material of a transistor by using a plasma (plasma).
도 2a 내지 2d는 본 발명에 따른 반도체 소자 제조방법을 설명하기 위한 공정단면도이다.2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
도 2a에 도시한 바와 같이, 반도체 기판(21)상에 게이트 절연층(22)을형성한다.As shown in FIG. 2A, the gate insulating layer 22 is formed on the semiconductor substrate 21.
상기 게이트 절연층(22)상에 게이트 전극 형성을 위한 폴리실리콘층(23)을 형성한다.A polysilicon layer 23 for forming a gate electrode is formed on the gate insulating layer 22.
이때, 상기 폴리실리콘층(23)은 도면에 도시된 바와 같이, 그 표면이 매우 거칠다.At this time, the polysilicon layer 23, as shown in the figure, the surface is very rough.
따라서, 상기 표면의 거칠기를 개선해주어야 하는데, 본 발명은 플라즈마를 이용한다.Therefore, the surface roughness should be improved, and the present invention uses plasma.
즉, 도 2b에 도시한 바와 같이, 플라즈마를 이용한 식각 공정으로 상기 폴리실리콘층(23) 표면의 거칠기를 개선시킨다.That is, as illustrated in FIG. 2B, the roughness of the surface of the polysilicon layer 23 is improved by an etching process using plasma.
이때, 플라즈마는 아르곤(Ar)가스 또는 클로린(chlorine)기를 포함하는 가스 또는 아르곤(Ar)을 포함하는 가스, 또는 클로린(chlorine)을 포함하는 가스 또는 불활성 가스, 또는 상기 가스들에 플로린(Flourine)기가 포함된 가스를 이용한다.At this time, the plasma is a gas containing argon (Ar) gas or chlorine group or a gas containing argon (Ar), or a gas or inert gas containing chlorine (Florine) or Florin (Flourine) to the gases Use gas containing groups.
즉, Ar 또는 Cl2+Ar 또는 SF6+Ar 또는 O2+Ar 또는 N2+Ar 가스를 이용한다.That is, Ar or Cl 2 + Ar or SF 6 + Ar or O 2 + Ar or N 2 + Ar gas is used.
그리고 식각장비로서는 RIE(Reactive Ion Etcher), MERIE(Magnetically Enhanced Reactive Ion Etcher), HDP(High Density Plasma)등 플라즈마내 이온 밀도와 이온 에너지를 의존적으로 혹은 독립적으로 조절할 수 있는 식각 장비를 이용한다.As etching equipment, etching equipment capable of independently or independently controlling ion density and ion energy in plasma such as RIE (Reactive Ion Etcher), MERIE (Magnetically Enhanced Reactive Ion Etcher), and HDP (High Density Plasma) are used.
이어, 도 2c에 도시한 바와 같이, 상기 폴리실리콘층(23)상에 실리사이드층(24)을 형성하고, 상기 실리사이드층(24)상에 감광막(25)을 도포한다.Subsequently, as illustrated in FIG. 2C, a silicide layer 24 is formed on the polysilicon layer 23, and a photosensitive film 25 is coated on the silicide layer 24.
노광 및 현상 공정을 이용하여 상기 감광막을 패터닝하고, 패터닝된 감광막을 마스크로 이용한 식각 공정으로 상기 실리사이드층(24)과 폴리실리콘층(23)을 차례로 식각하여 도 2d에 도시한 바와 같이, 게이트 전극(26)을 형성한 후, 고농도의 소오스/드레인 영역(27,27a)을 형성하면 본 발명에 따른 반도체 소자 제조공정이 완료된다.The photoresist is patterned using an exposure and development process, and the silicide layer 24 and the polysilicon layer 23 are sequentially etched by an etching process using the patterned photoresist as a mask, as shown in FIG. 2D. After the formation of (26), the high concentration source / drain regions 27 and 27a are formed to complete the semiconductor device manufacturing process according to the present invention.
이때, 상기 식각 가스로서는 클로린(chlorine)기를 포함한 가스, 산소(O2)를 포함한 가스, 불활성 가스 또는 상기 가스등에 플로린(flourine)기를 포함하는 가스를 이용한다.In this case, as the etching gas, a gas containing a chlorine group, a gas containing oxygen (O 2 ), an inert gas, or a gas containing a florin group in the gas is used.
즉, Cl2+O2, Cl2+HBr, Cl2+HBr+O2, Cl2+SF6가스를 이용한다.In other words, Cl 2 + O 2 , Cl 2 + HBr, Cl 2 + HBr + O 2 , Cl 2 + SF 6 gases are used.
이때, 상기 게이트 전극(26)을 형성하기 위한 식각 장비로서는 RIE(Reactive Ion Etcher), MERIE(Magnetically Enhanced Reactive Ion Etcher), HDP(High Density Plasma)등 플라즈마내 이온 밀도와 이온 에너지를 의존적으로 혹은 독립적으로 조절할 수 있는 식각 장비를 이용한다.In this case, as an etching apparatus for forming the gate electrode 26, the ion density and ion energy in plasma may be dependent or independent, such as Reactive Ion Etcher (RIE), Magnetically Enhanced Reactive Ion Etcher (MERIE), or High Density Plasma (HDP). Use etching equipment that can be adjusted.
이상 상술한 바와 같이 본 발명의 반도체 소자 제조방법은 다음과 같은 효과가 있다.As described above, the semiconductor device manufacturing method of the present invention has the following effects.
첫째, 게이트전극 물질의 표면 거칠기로 인한 절연막의 데미지를 줄일 수 있다.First, damage to the insulating film due to the surface roughness of the gate electrode material can be reduced.
둘째, 폴리실리콘층상에 형성되는 실리사이드층의 거칠기가 개선되므로 게이트 특성을 향상시킬 수 있다.Second, since the roughness of the silicide layer formed on the polysilicon layer is improved, the gate characteristics may be improved.
셋째, 플라즈마를 이용하므로 CMP에 비해 식각율이 일정하며 폴리실리콘층의 두께를 조절할 수 있다.Third, since the plasma is used, the etching rate is constant compared to the CMP, and the thickness of the polysilicon layer can be adjusted.
넷째, 플라즈마를 사용하므로 CMP에 비해 폴리실리콘층의 두께 균일도를 향상시킬 수 있다.Fourth, since the plasma is used, the thickness uniformity of the polysilicon layer can be improved as compared with the CMP.
다섯째, 플라즈마를 이용하므로 CMP에 비해 재현성을 향상시킬 수 있다.Fifth, since the plasma is used, the reproducibility can be improved compared to the CMP.
여섯째, 플라즈마를 이용하므로 공정을 연속적으로 진행할 수 있다.Sixth, the plasma can be used to proceed the process continuously.
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