JPH04208528A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04208528A JPH04208528A JP40014790A JP40014790A JPH04208528A JP H04208528 A JPH04208528 A JP H04208528A JP 40014790 A JP40014790 A JP 40014790A JP 40014790 A JP40014790 A JP 40014790A JP H04208528 A JPH04208528 A JP H04208528A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- germanium
- etching
- crystal layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 14
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 11
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- -1 germanium ions Chemical class 0.000 claims description 3
- 239000013078 crystal Substances 0.000 abstract description 15
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 abstract description 9
- 238000000137 annealing Methods 0.000 abstract description 4
- 238000001312 dry etching Methods 0.000 abstract description 4
- 239000005416 organic matter Substances 0.000 abstract description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 3
- 235000011114 ammonium hydroxide Nutrition 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- SCPYDCQAZCOKTP-UHFFFAOYSA-N silanol Chemical compound [SiH3]O SCPYDCQAZCOKTP-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Weting (AREA)
Abstract
Description
［０００１１ [00011
【産業上の利用分野］本発明は半導体装置の製造方法に
関し、特に表面の平坦化及び溝の形成方法に関する。
［０００２］
【従来の技術】従来、半導体装置の製造工程において、
半導体基板への溝の形成方法としては、感光性有機膜。
シリコン酸化膜あるいはシリコン窒化膜をマスクとする
プラズマを用いたドライエツチング法、特にアスペクト
比の良い反応性イオンエツチング（ＲＩ Ｅ）法が主に
用いられている。
［０００３］また、凹凸表面の平坦化法としては、エツ
チングレートが等しい膜を形成後エツチングを行うエッ
チバック法や、ポリイミドあるいはシラノール等による
塗布膜形成による平坦化法が主に用いられている。
［０００４］BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for flattening a surface and forming a groove. [0002] Conventionally, in the manufacturing process of semiconductor devices,
A photosensitive organic film is used as a method for forming grooves in a semiconductor substrate. A dry etching method using plasma using a silicon oxide film or a silicon nitride film as a mask, particularly a reactive ion etching (RIE) method with a good aspect ratio, is mainly used. [0003] Also, as a method for flattening an uneven surface, an etch-back method in which a film with an equal etching rate is formed and then etched, and a flattening method by forming a coating film of polyimide, silanol, etc. are mainly used. [0004]
【発明が解決しようとする課題】上述した従来の半導体
装置の製造工程における半導体基板のエツチング方法で
は、反応ガスをグロー放電によりプラズマ状態とし、プ
ラズマ中のイオンが基板にイオン衝撃を与え、励起した
フッ素及び塩素イオンと化学反応を起こりやすくして除
去しているため、被エツチング部のマスクとしてフォト
レジストなどを使用した場合、これがイオン衝撃により
分解し、側壁に再付着する。この付着物により形成する
溝の形状が悪くなったり、その除去の難しさのため、付
着物が残留してしまい、容量等における電気的不安定性
の原因となる。加えて、装置内壁材料のスパッタによる
半導体基板の汚染も発生する。
［０００５］また、基板結晶面によりエツチングレート
に差が生じ、 （１００）、 （１１０）、 （１
１１）面の順に溝形成の精度が悪くなる。加えて、不純
物含有量が１０２０個／Ｃｍ３程度からエツチング速度
が増加し、反応性イオンエツチングにおいても、マスク
下にアンダーカットが生じやすく、形状精度が悪くなる
。
［０００６１更に、基板表面の平坦化の場合も同様に、
ウェハの大口径化に伴い、プラズマ密度やガス流の影響
のため、ウェハ面内やバッチ内の均一なエツチングはよ
り難しくなる。
［０００７］[Problems to be Solved by the Invention] In the conventional method of etching a semiconductor substrate in the manufacturing process of a semiconductor device as described above, a reaction gas is brought into a plasma state by glow discharge, and ions in the plasma impact the substrate and become excited. Since it is removed by easily causing a chemical reaction with fluorine and chlorine ions, if a photoresist or the like is used as a mask for the area to be etched, it will be decomposed by ion bombardment and re-attached to the side wall. This deposit may deteriorate the shape of the groove formed, or because it is difficult to remove, the deposit may remain, causing electrical instability in capacitance and the like. In addition, contamination of the semiconductor substrate occurs due to sputtering of the material on the inner wall of the device. [0005] Also, there are differences in the etching rate depending on the crystal plane of the substrate, (100), (110), (1
11) The accuracy of groove formation deteriorates in the order of surfaces. In addition, the etching rate increases when the impurity content is around 1020/Cm3, and even in reactive ion etching, undercuts are likely to occur under the mask, resulting in poor shape accuracy. [00061 Furthermore, in the case of flattening the substrate surface, similarly,
As wafer diameters increase, uniform etching within the wafer surface and batch becomes more difficult due to the effects of plasma density and gas flow. [0007]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、シリコン基板に選択的にゲルマニウムをイオ
ン注入したのち熱処理しシリコン・ゲルマニウム混晶層
を形成する工程と、シリコン基板とシリコン・ゲルマニ
ラム混晶層とのエツチングレート比を利用し前記シリコ
ン・ゲルマニウム混晶層をエツチングする工程とを含ん
で構成される。
［０００８］混晶層を形成するための元素としては、ゲ
ルマニウムの他に高融点金属等も考えられるが、エツチ
ングレート比が低く、しかも後工程の熱処理によるシリ
コン基板への汚染が生ずるため適当ではない。
［０００９］[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes the steps of selectively implanting germanium ions into a silicon substrate and then performing heat treatment to form a silicon-germanium mixed crystal layer; The method includes a step of etching the silicon-germanium mixed crystal layer using an etching rate ratio with respect to the germanium mixed crystal layer. [0008] In addition to germanium, high-melting point metals can be considered as elements for forming the mixed crystal layer, but these are not suitable because the etching rate ratio is low and the silicon substrate is contaminated by heat treatment in the post-process. do not have. [0009]
【実施例】次に本発明について図面を参照して説明する
。図１（ａ）〜（ｄ）は本発明の第１の実施例を説明す
るための工程順に示した半導体チップの断面図であり、
本発明を溝形成に適用した場合である。
［００１０］まず図１（ａ）に示すように、シリコン基
板１０上にフォトレジスト膜１を塗布する。続いてフォ
トリソグラフィ技術によってフォトレジスト膜１をパタ
ニングする。次に図１（ｂ）に示すように、加速電圧が
可変なイオン注入装置を用い、数ｋｅＶのから数十Ｍｅ
Ｖの範囲で可変しながら、ゲルマニウムを高濃度（２，
５ｘ １０” ｃｍ−３程度）にイオン注入しゲルマニ
ウム注入層３を形成する。
［００１１］次いで図１ （Ｃ）に示すように、フォト
レジスト膜１を除去した後、ランプアニールあるいは炉
アニールにより数百℃以上で熱処理することによって、
シリコン・ゲルマニウムの混晶層４を形成する。最後に
ＣＦ４ と０２の混合ガスによるドライエツチング法
、あるいは、１００℃程度のアンモニア水・過酸化水素
混合液によるウェットエツチング法により、選択的にシ
リコン・ゲルマニウム混晶層４をエツチングすることに
よって、高アスペクト比の形状精度の良い微細な溝５を
形成する。ＣＦ４ ＋０２ ガスを用いた場合のシリ
コン・ゲルマニウム混晶層４のエツチングレートはシリ
コン基板の約４倍またアンモニア水・過酸化水素混合液
では約２０倍であり、溝５の形成を精度良く行うことが
できる。
（００１２１図２（ａ）〜（ｄ）は本発明の第２の実施
例を説明するための半導体チップの断面図であり、本発
明を基板の平坦化に適用した場合である。
［００１３］まず図２（ａ）に示すように、凸部６のあ
るシリコン基板１０上にポリイミドやシラノール等によ
る塗布膜７を形成し表面を平坦化する。次に図２（ｂ）
に示すように塗布膜７を通して、ゲルマニウムを高濃度
にイオン注入し、凸部６をゲルマニウム注入層３Ａとす
る。
［００１４］次に、図２（Ｃ）に示すように、塗布膜７
を除去後、ランプアニールあるいは炉アニールにより数
百℃以上で、熱処理することによって、凸部をシリコン
・ゲルマニウム混晶層４Ａとする。次に図２（ｄ）に示
すように、ＣＦ ４ と０２の混合ガスによるドライエ
ツチング法、あるいは、１００℃程度のアンモニア水・
過酸化水素液によるウェットエツチング法により選択的
にシリコン・ゲルマニウム混晶層４Ａをエツチングする
ことにより、表面に凹凸のない均一性のよい平坦なシリ
コン基板を形成できる。
［００１５］DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in order of steps for explaining the first embodiment of the present invention,
This is a case where the present invention is applied to groove formation. [0010] First, as shown in FIG. 1(a), a photoresist film 1 is coated on a silicon substrate 10. Subsequently, the photoresist film 1 is patterned by photolithography. Next, as shown in Fig. 1(b), an ion implanter with variable acceleration voltage is used to implant the ions from several keV to several tens of Me.
While varying the range of V, germanium was added at a high concentration (2,
5x 10" cm-3) to form a germanium implantation layer 3. [0011] Next, as shown in FIG. By heat treatment at over 100℃,
A silicon-germanium mixed crystal layer 4 is formed. Finally, the silicon-germanium mixed crystal layer 4 is selectively etched using a dry etching method using a mixed gas of CF4 and 02, or a wet etching method using a mixed solution of ammonia water and hydrogen peroxide at about 100°C. To form a fine groove 5 with a good aspect ratio shape accuracy. The etching rate of the silicon-germanium mixed crystal layer 4 when using CF4 +02 gas is about 4 times that of the silicon substrate, and about 20 times when using an ammonia water/hydrogen peroxide mixture, so that the grooves 5 can be formed with high precision. I can do it. (00121 FIGS. 2(a) to 2(d) are cross-sectional views of a semiconductor chip for explaining a second embodiment of the present invention, in which the present invention is applied to planarization of a substrate. [0013] First, as shown in FIG. 2(a), a coating film 7 of polyimide, silanol, etc. is formed on the silicon substrate 10 having the convex portion 6 to flatten the surface.Next, as shown in FIG. 2(b)
As shown in FIG. 2, germanium is ion-implanted at a high concentration through the coating film 7 to form the convex portion 6 as a germanium-implanted layer 3A. [0014] Next, as shown in FIG. 2(C), the coating film 7
After removing, the convex portion is converted into a silicon-germanium mixed crystal layer 4A by heat treatment at several hundred degrees centigrade or higher by lamp annealing or furnace annealing. Next, as shown in Figure 2(d), a dry etching method using a mixed gas of CF 4 and 02, or an ammonia water etching method at about 100°C is performed.
By selectively etching the silicon-germanium mixed crystal layer 4A using a wet etching method using a hydrogen peroxide solution, a flat silicon substrate with good uniformity and no irregularities can be formed on the surface. [0015]
【発明の効果】以上説明したように本発明は、イオン注
入法により高濃度のゲルマニウムをシリコン基板に選択
的に導入し、シリコン・ゲルマニウム混晶層を形成した
のち、この混晶層をエツチングして表面の平坦化や溝の
形成を行うことができる。このため、反応性イオンエツ
チングによる溝側壁への有機物の再付着に起因する電気
的不安定性の恐れがなくなり、ＶＬＳＩ対応の微細な高
アスペクト比を有する形状精度の良い溝の形成や、シリ
コン基板の平坦化を行うことができる。加えて、溝形成
にイオン注入を用いるため、ウェハ面内およびバッチ内
の溝形成の均一性にすぐれ、半導体基板の面方位及び不
純物ドーズ量に無関係に形状精度の良い溝を形成するこ
とができるという効果もある。[Effects of the Invention] As explained above, the present invention selectively introduces germanium at a high concentration into a silicon substrate by ion implantation to form a silicon-germanium mixed crystal layer, and then etches this mixed crystal layer. The surface can be flattened and grooves can be formed using the same method. Therefore, there is no fear of electrical instability caused by re-deposition of organic matter on the groove sidewalls due to reactive ion etching, and it is possible to form fine grooves with a high aspect ratio and good shape accuracy for VLSI, and to form grooves on silicon substrates. Flattening can be performed. In addition, since ion implantation is used for groove formation, the groove formation is highly uniform both within the wafer and within the batch, and grooves with excellent shape accuracy can be formed regardless of the surface orientation of the semiconductor substrate or the dose of impurities. There is also this effect.
【図１】本発明の第１の実施例を説明するための半導体
チップの断面図である。FIG. 1 is a cross-sectional view of a semiconductor chip for explaining a first embodiment of the present invention.
【図２】本発明の第２の実施例を説明するための半導体
チップの断面図である。FIG. 2 is a cross-sectional view of a semiconductor chip for explaining a second embodiment of the present invention.
１ フォトレジスト膜 ２ Ｇｅ” ３．３Ａ ゲルマニウム注入層 ４．４Ａ シリコン・ゲルマニウム混晶層５溝 ６ 凸部 ７ 塗布膜 １０ シリコン基板 1 Photoresist film 2 Ge” 3.3A germanium injection layer 4.4A Silicon/germanium mixed crystal layer 5 grooves 6 Convex part 7 Coating film 10 Silicon substrate
Claims (1)
オン注入したのち熱処理しシリコン・ゲルマニウム混合
層を形成する工程と、シリコン基板とシリコン・ゲルマ
ニウム混合層とのエッチングレート比を利用し前記シリ
コン・ゲルマニウム混合層をエッチングする工程とを含
むことを特徴とする半導体装置の製造方法。1. A step of selectively implanting germanium ions into a silicon substrate and then performing heat treatment to form a silicon-germanium mixed layer, and utilizing an etching rate ratio between the silicon substrate and the silicon-germanium mixed layer. A method for manufacturing a semiconductor device, comprising the step of etching a mixed layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP40014790A JPH04208528A (en) | 1990-12-03 | 1990-12-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP40014790A JPH04208528A (en) | 1990-12-03 | 1990-12-03 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04208528A true JPH04208528A (en) | 1992-07-30 |
Family
ID=18510063
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP40014790A Pending JPH04208528A (en) | 1990-12-03 | 1990-12-03 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04208528A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06252075A (en) * | 1993-02-23 | 1994-09-09 | American Teleph & Telegr Co <Att> | Method for manufacturing mos device by performing diffusion of boron |
| EP0862207A1 (en) * | 1997-02-27 | 1998-09-02 | Siemens Aktiengesellschaft | Method of forming a DRAM trench capacitor |
| WO2001011668A1 (en) * | 1999-08-06 | 2001-02-15 | Hitachi, Ltd. | Method of manufacturing semiconductor device |
| WO2007036449A1 (en) * | 2005-09-30 | 2007-04-05 | Robert Bosch Gmbh | Method for accelerating etching of silicon |
| JP2008508704A (en) * | 2004-07-29 | 2008-03-21 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Method for etching a layer on a substrate |
| US7709333B2 (en) * | 2005-08-03 | 2010-05-04 | International Business Machines Corporation | Method for reducing overlap capacitance in field effect transistors |
-
1990
- 1990-12-03 JP JP40014790A patent/JPH04208528A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06252075A (en) * | 1993-02-23 | 1994-09-09 | American Teleph & Telegr Co <Att> | Method for manufacturing mos device by performing diffusion of boron |
| EP0862207A1 (en) * | 1997-02-27 | 1998-09-02 | Siemens Aktiengesellschaft | Method of forming a DRAM trench capacitor |
| WO2001011668A1 (en) * | 1999-08-06 | 2001-02-15 | Hitachi, Ltd. | Method of manufacturing semiconductor device |
| JP2008508704A (en) * | 2004-07-29 | 2008-03-21 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Method for etching a layer on a substrate |
| JP4686544B2 (en) * | 2004-07-29 | 2011-05-25 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Method for etching a layer on a substrate |
| US8182707B2 (en) | 2004-07-29 | 2012-05-22 | Robert Bosch Gmbh | Method for etching a layer on a substrate |
| US7709333B2 (en) * | 2005-08-03 | 2010-05-04 | International Business Machines Corporation | Method for reducing overlap capacitance in field effect transistors |
| US7824989B2 (en) * | 2005-08-03 | 2010-11-02 | International Business Machines Corporation | Method for reducing overlap capacitance in field effect transistors |
| WO2007036449A1 (en) * | 2005-09-30 | 2007-04-05 | Robert Bosch Gmbh | Method for accelerating etching of silicon |
| DE102005047081B4 (en) | 2005-09-30 | 2019-01-31 | Robert Bosch Gmbh | Process for the plasma-free etching of silicon with the etching gas ClF3 or XeF2 |
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