KR100335765B1 - Method for fabricating charge storage electrode of semiconductor device - Google Patents

Method for fabricating charge storage electrode of semiconductor device Download PDF

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KR100335765B1
KR100335765B1 KR1019950017279A KR19950017279A KR100335765B1 KR 100335765 B1 KR100335765 B1 KR 100335765B1 KR 1019950017279 A KR1019950017279 A KR 1019950017279A KR 19950017279 A KR19950017279 A KR 19950017279A KR 100335765 B1 KR100335765 B1 KR 100335765B1
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layer
polysilicon
sacrificial oxide
charge storage
film
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KR1019950017279A
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KR970003979A (en
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나금주
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: A method for fabricating a charge storage electrode of a semiconductor device is provided to maximize an effective surface area of a capacitor without deteriorating step coverage by depositing a thin mask polysilicon layer on a phosphosilicate glass (PSG) layer which is a basic type of a cylindrical capacitor and by exposing the mask polysilicon layer to HF vapor. CONSTITUTION: An insulation layer(3) and a nitride layer(4) are sequentially formed on a silicon substrate(1) having a junction area(2). The nitride layer and the insulation layer are sequentially etched to form a contact hole exposing the junction area through a photolithography process. Oxide layer spacers(5) are formed on both sidewalls of the contact hole. The first polysilicon layer(6) and a PSG sacrificial oxide layer are sequentially deposited to fill the contact hole. Predetermined regions of the PSG sacrificial oxide layer and the first polysilicon layer are sequentially etched through a photolithography process. A mask polysilicon layer is formed on the resultant structure and is exposed to HF vapor to partially etch the surface of the PSG sacrificial oxide layer so that the surface of the PSG sacrificial oxide layer is of an embossed type. After the mask polysilicon layer is removed, the second polysilicon layer is deposited on the resultant structure. The second polysilicon layer is blanket-etched to form the second polysilicon spacer(9A) on the etch surface having the embossed structure. The PSG sacrificial oxide layer is eliminated to form the charge storage electrode(10) whose inner surface is of the embossed structure.

Description

반도체 소자의 전하저장전극 형성방법Method for forming charge storage electrode of semiconductor device

본 발명은 반도체 소자의 전하저장전극 형성방법에 관한 것으로, 특히 불산중기(HF-VAPOR)가 폴리실리콘의 결정계면을 따라 하부의 산화막을 부분적으로 식각시키는 원리를 이용하여 실린더형 캐패시터의 기본 모형이 되는 PSG 막에 얇은 마스크 폴리실리콘을 증착한 후 불산증기에 단시간 노출시켜 표면이 부분적으로 식각되어 엠보싱 형태의 표면을 가진 원통형 PSG 막을 형성시키므로써, 유효표면적의 증가로 캐패시터의 정전용량을 증대시킬 수 있도록 한 반도체 소자의 전하저장전극 형성방법에 관한 것이다.The present invention relates to a method for forming a charge storage electrode of a semiconductor device. In particular, a basic model of a cylindrical capacitor is developed by using HF-VAPOR partially etching an oxide layer below the polysilicon crystal interface. After depositing a thin mask polysilicon on the PSG film to be exposed to hydrofluoric acid for a short time, the surface is partially etched to form a cylindrical PSG film having an embossed surface, thereby increasing the capacitance of the capacitor by increasing the effective surface area. It relates to a method for forming a charge storage electrode of a semiconductor device.

일반적으로 디램(DRAM) 등과 같은 반도체 소자의 고집적화에 따라 셀(Cell)의 면적은 급격하게 축소된다. 그러나 소자의 동작을 위해서는 단위셀당 일정량 이상의 정전용량(Capacitance)을 반드시 확보해야 하기 때문에 소자의 제조에 많은 어려움이 따른다. 이에따라 셀의 동작에 필요한 정전용량을 그대로 유지하면서 그 캐패시터(Capacitor)가 차지하는 칩(Chip)상의 면적을 단차의 증가없이 최소화하며 일정수준 이상의 정전용량을 확보하기 위해 고도의 공정기술 개발과 소자의 신뢰성확보가 큰 문제점으로 대두되고 있다.In general, the area of a cell is rapidly reduced due to the high integration of semiconductor devices such as DRAM. However, the operation of the device requires a certain amount or more of capacitance (capacitance) per unit cell, so there are many difficulties in manufacturing the device. Accordingly, while maintaining the capacitance necessary for the operation of the cell as it is, while minimizing the area on the chip occupied by the capacitor without increasing the step height, the development of advanced process technology and device reliability to secure a certain level of capacitance Securing is a big problem.

이러한 문제점을 해결하기 위하여는 캐패시터의 구조를 3차원의 입체구조로 형성하여 유효표면적을 증가시키거나, 유전특성이 향상된 유전체(Dielectric)를 개발해야만 되는데, 이상적인 유전특성을 가지는 유전체막의 개발은 아직 소자의 제조에 적용이 어려운 실정이며, 그래서 소자의 동작에 필요한 정전용량의 확보를 위하여 전하저장전극의 유효표면적을 극대화시키는 방향으로 많은 연구가 이루어져 왔다.In order to solve this problem, it is necessary to increase the effective surface area by forming the three-dimensional structure of the capacitor structure or to develop a dielectric with improved dielectric properties. In order to secure the capacitance required for the operation of the device, many studies have been conducted to maximize the effective surface area of the charge storage electrode.

따라서 본 발명은 불산중기(HF-VAPOR)가 폴리실리콘의 결정계면을 따라 하부의 산화막을 부분적으로 식각시키는 원리를 이용하여 실린더형 캐패시터의 기본 모형이 되는 PSG 막에 얇은 마스크 폴리실리콘을 증착한 후 불산증기에 단시간 노출시켜 표면이 부분적으로 식각되어 엠보싱 형태의 표면을 가진 원통형 PSG 막을 형성하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 전하저장전극 형성방법을 제공하는데 그 목적이 있다.Therefore, in the present invention, the thin film polysilicon is deposited on the PSG film, which is the basic model of the cylindrical capacitor, by using HF-VAPOR partially etching the lower oxide film along the polysilicon crystal interface. It is an object of the present invention to provide a method for forming a charge storage electrode of a semiconductor device which can solve the above-mentioned disadvantages by forming a cylindrical PSG film having an embossed surface by partially etching the surface by short exposure to hydrofluoric acid.

상술한 목적을 달성하기 위한 본 발명은 접합영역이 형성된 실리콘 기판상에 절연막을 을 형성하고 그상부에 질화막을형성하는 단계와, 전하저장전극용 콘택홀 마스크를 이용한 사진 및 식각공정을 통해 상기 접합영역이 노출되도록 상기 질화막 및 절연막을 순차적으로 식각하여 콘택홀을 형성하는 단계와, 상기 콘택홀 양 측벽에 폴리간의 쇼트를 방지하기 위하여 산화막 스페이서를 형성하는 단계와, 전체상부면에 제 1 폴리실리콘 및 PSG 희생산화막을 순차적으로 증착한 후 전하저장전극용 마스크를 이용한 사진 및 식각공정을 통해 상기 PSG 희생산화막 및 제 1 폴리실리콘을 순차적으로 식각하는 단계와, 상기 전체상부면에 마스크 폴리실리콘을 형성하는 단계와, 불산증기에 노출하여 상기 PSG 희생산화막의 표면을 엠보싱형태로 부분 식각하는 단계와, 상기 마스크 폴리실리콘을 제거한 후 전체 상부면에 제 2 폴리실리콘을 증착하는 단계와, 상기 제 2 폴리실리콘을 블랜켓식각하여 상기 엠보싱 구조를 갖는 식각면에 제 2 폴리실리콘 스페이서를 형성한 후 상기 PSG 희생산화막을 제거하여 내면이 엠보싱 구조로 형성된 전하저장전극을 형성하는 단계로 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is formed by forming an insulating film on a silicon substrate having a junction region and a nitride film formed thereon, and the bonding through the photo and etching process using a contact hole mask for a charge storage electrode Forming a contact hole by sequentially etching the nitride film and the insulating film so as to expose a region, and forming an oxide spacer to prevent a short between poly on both sidewalls of the contact hole, and first polysilicon on the entire upper surface And sequentially etching the PSG sacrificial oxide film and the first polysilicon through a photolithography and an etching process using a mask for charge storage electrodes after sequentially depositing the PSG sacrificial oxide film, and forming mask polysilicon on the entire upper surface. And partially etching the surface of the PSG sacrificial oxide film in an embossed form by exposing the hydrofluoric acid vapor. Removing the mask polysilicon and depositing second polysilicon on the entire upper surface, and blanketing the second polysilicon to form a second polysilicon spacer on the etching surface having the embossed structure. Thereafter, the PSG sacrificial oxide film is removed to form a charge storage electrode having an inner surface having an embossed structure.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

제 1A 내지 제 1G 도는 본 발명에 따른 반도체 소자의 전하저장전극 형성방법을 설명하기 위해 도시한 소자의 단면도로서,1A to 1G are cross-sectional views of a device for explaining a method of forming a charge storage electrode of a semiconductor device according to the present invention.

제 1A 도는 소정의 공정을 거쳐 접합영역(2)이 형성된 실리콘기판(1)상에 절연막(3)을 형성하고 그상부에 질화막(4)을 50 내지 1000Å정도의 두께로 형성한 상태를 나타낸다.FIG. 1A shows a state in which the insulating film 3 is formed on the silicon substrate 1 on which the junction region 2 is formed through a predetermined process, and the nitride film 4 is formed thereon with a thickness of about 50 to 1000 kPa.

제 1B 도는 전하저장전극용 콘택홀(Contact hole) 마스크(Mask)를 이용한 사진 및 식각공정을 통해 상기 접합영역(2)이 노출되도록 상기 질화막(4) 및 절연막(3)을 순차적으로 식각하여 콘택홀을 형성하고, 폴리간의 쇼트를 방지하기 위하여 콘택홀 양 측벽에 산화막 스페이서(5)를 형성한 상태를 나타낸다.In FIG. 1B, the nitride film 4 and the insulating film 3 are sequentially etched to expose the junction region 2 through a photolithography and an etching process using a contact hole mask for a charge storage electrode. The oxide film spacers 5 are formed on both sidewalls of the contact holes in order to form holes and prevent shorts between poly.

제 1C 도는 전체상부면에 제 1 폴리실리콘(6) 및 PSG 희생산화막(7)을 순차적으로 증착한 후 전하저장전극용 마스크를 이용한 사진 및 식각공정을 통해 상기 PSG 희생산화막(7) 및 제 1 폴리실리콘(6)을 순차적으로 식각한 상태를 나타낸다.The first polysilicon 6 and the PSG sacrificial oxide film 7 are sequentially deposited on the entire upper surface of FIG. 1C or the PSG sacrificial oxide film 7 and the first through a photolithography and an etching process using a mask for a charge storage electrode. The state which the polysilicon 6 was etched sequentially is shown.

제 1D 도는 전체상부면에 마스크 폴리실리콘(8)을 500 내지 2000Å정도의 두께로 형성한 상태를 나타낸다.FIG. 1D shows a state in which the mask polysilicon 8 is formed to a thickness of about 500 to 2000 mm 3 on the entire upper surface.

제 1E 도는 제 1D 도의 상태에서 불산증기에 노출하여 상기 PSG 희생산화막(7)의 표면을 엠보싱 형태로 부분 식각한 상태를 나타낸다.FIG. 1E illustrates a state in which the surface of the PSG sacrificial oxide film 7 is partially etched in an embossed form by exposing hydrofluoric acid vapor in the state of FIG. 1D.

제 1F 도는 상기 마스크 폴리실리콘(8)을 제거한 후 전체상부면에 제 2 폴리실리콘(9)을 증착한 상태를 나타낸다.1F illustrates a state in which the second polysilicon 9 is deposited on the entire upper surface after the mask polysilicon 8 is removed.

제 1G 도는 상기 제 2 폴리실리콘(9)을 블랜켓(Blanket)식각하여 상기 엠보싱 구조를 갖는 식각면에 제 2 폴리실리콘 스페이서(9A)를 형성한 후 상기 PSG 희생산화막(7)을 제거하여 내면이 엠보싱 구조로 형성된 전하저장전극(10)을 형성한 상태의 단면도인데, 이와같이 원통형의 전하 저장전극의 내면을 엠보싱 구조가 되도록 형성하므로써 전하저장전극의 유효 표면적이 증가된다.1G or the second polysilicon 9 is blanket-etched to form a second polysilicon spacer 9A on an etching surface having the embossed structure, and then the PSG sacrificial oxide film 7 is removed to form an inner surface. This is a cross-sectional view of the state in which the charge storage electrode 10 formed of the embossing structure is formed. Thus, the effective surface area of the charge storage electrode is increased by forming the inner surface of the cylindrical charge storage electrode to be the embossing structure.

상술한 바와같이 본 발명에 의하면 불산증기(HF-VAPOR)가 폴리실리콘의 결정계면을 따라 하부의 산화막을 부분적으로 식각시키는 원리를 이용하여 실린더형 캐패시터의 기본 모형이 되는 PSG 막에 얇은 마스크 폴리실리콘을 증착한 후 불산증기에 단시간 노출시켜 표면이 부분적으로 식각되어 엠보싱 형태의 표면을 가진 원통형 PSG 막을 형성시키므로써, 단차의 증가없이 유효표면적이 증가되어 캐패시터의 정전용량이 증대될 수 있는 탁월한 효과가 있다.As described above, according to the present invention, a thin mask polysilicon is formed on the PSG film, which is a basic model of the cylindrical capacitor, by using HF-VAPOR partially etching the lower oxide film along the polysilicon crystal interface. After deposition, the surface is partially etched by hydrofluoric acid vapor for a short time to form a cylindrical PSG film having an embossed surface, thereby increasing the effective surface area without increasing the step, thereby increasing the capacitance of the capacitor. have.

제 1A 내지 제 1G 도는 본 발명에 따른 반도체 소자의 전하저장전극 형성방법을 설명하기 위해 도시한 소자의 단면도.1A to 1G are cross-sectional views of a device for explaining a method of forming a charge storage electrode of a semiconductor device according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

1 : 실리콘기판 2 : 접합영역1: silicon substrate 2: junction area

3: 절연막 4: 질화막3: insulating film 4: nitride film

5: 산화막 스페이서 6: 제 1 폴리실리콘5: oxide film spacer 6: first polysilicon

7: PSG 희생산화막 8: 마스크 폴리실리콘7: PSG sacrificial oxide 8: mask polysilicon

9: 제 2 폴리실리콘 9A: 제 2 폴리실리콘 스페이서9: second polysilicon 9A: second polysilicon spacer

10: 전하저장전극10: charge storage electrode

Claims (4)

접합 영역이 형성된 실리콘 기판 상부에 절연막 및 질화막을 순차적으로 형성하는 단계와,Sequentially forming an insulating film and a nitride film on the silicon substrate on which the junction region is formed, 전하저장전극용 콘택홀 마스크를 이용한 사진 및 식각 공정으로 상기 질화막 및 절연막을 순차적으로 식각하여 상기 접합 영역을 노출시키는 콘택홀을 형성하는 단계와,Forming a contact hole exposing the junction region by sequentially etching the nitride layer and the insulating layer by a photo and etching process using a contact hole mask for a charge storage electrode; 상기 콘택홀 양측벽에 산화막 스페이서를 형성하는 단계와,Forming oxide spacers on both sidewalls of the contact hole; 상기 콘택홀이 매립되도록 전체 구조 상부에 제 1 폴리실리콘막 및 PSG 희생산화막을 순차적으로 증착한 후 전하저장전극용 마스크를 이용한 사진 및 식각 공정으로 상기 PSG 희생 산화막 및 제 1 폴리실리콘막의 소정 영역을 순차적으로 식각하는 단계와,The first polysilicon film and the PSG sacrificial oxide film are sequentially deposited on the entire structure to fill the contact hole, and then a predetermined region of the PSG sacrificial oxide film and the first polysilicon film is removed by a photolithography and an etching process using a mask for a charge storage electrode. Etching sequentially; 전체 구조 상부에 마스크 폴리실리콘막을 형성한 후 불산 증기에 노출시켜 상기 PSG 희생 산화막의 표면을 엠버싱 형태로 부분 식각하는 단계와,Forming a mask polysilicon film on the entire structure and then partially etching the surface of the PSG sacrificial oxide film by embossing by exposing to hydrofluoric acid vapor; 상기 마스크 폴리실리콘막을 제거한 후 전체 구조 상부에 제 2 폴리실리콘막을 증착하는 단계와,Removing the mask polysilicon layer and depositing a second polysilicon layer on the entire structure; 상기 제 2 폴리실리콘막을 블랭킷 식각하여 상기 엠보싱 구조를 갖는 식각면에 제 2 폴리실리콘 스페이서를 형성한 후 상기 PSG 희생 산화막을 제거하여 내면이 엠보싱 구조로 형성된 전하저장전극을 형성하는 단계로 이루어진 것을 특징으로 하는 반도체 소자의 전하저장전극 형성방법.Blanket etching the second polysilicon film to form a second polysilicon spacer on an etched surface having the embossed structure, and then removing the PSG sacrificial oxide film to form a charge storage electrode having an inner surface embossed structure; A charge storage electrode forming method of a semiconductor device. 제 1 항에 있어서, 상기 질화막은 50 내지 1000Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 전하저장전극 형성방법.The method of claim 1, wherein the nitride film is formed to a thickness of 50 to 1000 GPa. 제 1 항에 있어서, 상기 마스크 폴리실리콘막은 500 내지 2000Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 전하저장전극 형성방법.The method of claim 1, wherein the mask polysilicon film is formed to a thickness of 500 to 2000 GPa. 제 1 항에 있어서, 상기 PSG 희생 산화막의 엠보싱 형태는 불산 증기가 마스크 폴리실리콘막의 계면을 따라 상기 PSG 희생 산화막을 부분적으로 식각하여 형성되는 것을 특징으로 하는 반도체 소자의 전하저장전극 형성방법.The method of claim 1, wherein the embossed form of the PSG sacrificial oxide film is formed by partially etching the PSG sacrificial oxide film along the interface of a mask polysilicon film.
KR1019950017279A 1995-06-24 1995-06-24 Method for fabricating charge storage electrode of semiconductor device KR100335765B1 (en)

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Citations (1)

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JPH06196649A (en) * 1992-12-08 1994-07-15 Nec Corp Manufacture of semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06196649A (en) * 1992-12-08 1994-07-15 Nec Corp Manufacture of semiconductor device

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