KR100331887B1 - A gate pattern of thin film transistor and a method of fabricating the same - Google Patents
A gate pattern of thin film transistor and a method of fabricating the same Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title description 6
- 239000002184 metal Substances 0.000 claims abstract description 53
- 229910052751 metal Inorganic materials 0.000 claims abstract description 53
- 239000010408 film Substances 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 15
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 13
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 238000001039 wet etching Methods 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 8
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910017604 nitric acid Inorganic materials 0.000 claims abstract description 5
- 230000001678 irradiating effect Effects 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 239000002253 acid Substances 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 125000002346 iodo group Chemical group I* 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 11
- 230000008021 deposition Effects 0.000 abstract description 4
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 abstract description 3
- 238000000206 photolithography Methods 0.000 abstract description 2
- 238000001465 metallisation Methods 0.000 abstract 1
- 239000000203 mixture Substances 0.000 abstract 1
- KHIWWQKSHDUIBK-UHFFFAOYSA-N periodic acid Chemical compound OI(=O)(=O)=O KHIWWQKSHDUIBK-UHFFFAOYSA-N 0.000 abstract 1
- 210000004231 tunica media Anatomy 0.000 abstract 1
- 150000002739 metals Chemical class 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- QFWPJPIVLCBXFJ-UHFFFAOYSA-N glymidine Chemical compound N1=CC(OCCOC)=CN=C1NS(=O)(=O)C1=CC=CC=C1 QFWPJPIVLCBXFJ-UHFFFAOYSA-N 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 231100001261 hazardous Toxicity 0.000 description 1
- 229910052740 iodine Inorganic materials 0.000 description 1
- 239000011630 iodine Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000006722 reduction reaction Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- C23F1/00—Etching metallic material by chemical means
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- C23F1/20—Acidic compositions for etching aluminium or alloys thereof
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F1/00—Etching metallic material by chemical means
- C23F1/10—Etching compositions
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- C23F1/16—Acidic compositions
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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Abstract
본 발명에 따른 박막트랜지스터의 게이트패턴은 투명기판 위에 형성된 Al계 금속막과, 상기 Al계 금속막 위에 형성된 Ti막의 2중막으로 이루어지고, 이러한 게이트패턴의 형성은, ① 투명기판 준비, ② Al계 금속의 증착, ③ Ti 증착, ④ 사진식각(photolithography), ⑤ 습식각, ⑥ 포토레지스트(PR) 제거의 공정을 따른다.The gate pattern of the thin film transistor according to the present invention is composed of an Al-based metal film formed on a transparent substrate and a double film of a Ti film formed on the Al-based metal film. The gate pattern is formed by (1) preparing a transparent substrate and (2) Al-based. Metal deposition, ③ Ti deposition, ④ photolithography, ⑤ wet etching, ⑥ photoresist (PR) removal.
박막트랜지스터의 게이트를 Al계 금속막/Ti막의 2중막으로 하여 혼합 식각액에 의해 단일 식각하므로써 공정을 단순화할 수 있으며, 혼합 식각액으로 요오드산(HiO4)계를 기본으로 한 불산(HF), 질산(HNO3)을 사용하므로써 환경을 보호할 수 있다.To the gates of the thin film transistor is of the Al-based metal film / Ti film 2 tunica media, and can simplify the process By a single etching by a mixed etchant, periodic acid (HiO 4) system for a hydrofluoric acid (HF), nitric acid as the primary of a mixture etchant (HNO 3 ) can be used to protect the environment.
Description
본 발명은 박막트랜지스터의 게이트패턴에 관한 것으로, 특히 Al계 금속막/Ti막의 2중 금속막으로 이루어진 게이트패턴 및 그것의 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate pattern of a thin film transistor, and more particularly, to a gate pattern made of a double metal film of an Al-based metal film / Ti film and a method of forming the same.
박막트랜지스터 액정표시소자(TFT LCD)의 제조는 일반적으로, 1) 투명기판 위에 박막트랜지스터를 형성하는 TFT공정, 2) 적(R), 청(G), 녹(B)의 3가지 색을 형성하는 컬러필터공정, 3) TFT가 형성된 기판과 컬러필터가 형성된 기판을 합착한 후 액정을 주입하여 구동이 가능한 상태로 패널을 만드는 셀제조공정, 및 4) 전자제품과 접합할 수 있도록 패널을 최종적으로 가공하여 모듈을 제조하는 공정의 4가지 공정을 따른다.In general, thin film transistor liquid crystal display (TFT LCD) is manufactured by 1) TFT process for forming a thin film transistor on a transparent substrate, and 2) red (R), blue (G), and green (B). Color filter process, 3) a cell manufacturing process of forming a panel in a state in which a liquid crystal is injected and then driven by bonding a substrate on which a TFT is formed with a substrate on which a color filter is formed, and 4) a panel is finally assembled to be bonded to an electronic product. Follow the four processes of manufacturing the module by processing.
박막트랜지스터의 게이트패턴은 전기적 신호에 따라 TFT의 소스/드레인전극 사이의 전류를 제어하기 위한 것으로서, 게이트패턴으로는 Al과 같이 전기적 저항이 낮은 금속이 주로 사용되는데. 근래에는, Al계 금속막이 갖는 단점을 보완하고자 Mo계 금속을 같이 사용하여 Mo계 금속막/Al계 금속막의 2중금속막을 게이트패턴으로 사용한다. 이러한 게이트패턴의 형성은 2개의 마스크 또는 1개의 마스크를 이용하여 수행된다.The gate pattern of the thin film transistor is to control the current between the source / drain electrodes of the TFT according to the electrical signal. A metal having a low electrical resistance such as Al is mainly used as the gate pattern. In recent years, in order to compensate for the drawbacks of Al-based metal films, Mo-based metals are used together to use a double metal film of Mo-based metal film / Al-based metal film as a gate pattern. The formation of such a gate pattern is performed using two masks or one mask.
먼저, 2개의 마스크를 이용할 경우 공정순서는, 투명기판 위에 Al계 금속을 증착하는 단계와, 상기한 금속 위에 포토레지스트를 도포하고 그 위에 광조사한 후 습식각하는 단계와, 포토레지스트를 제거하는 단계와, Mo계 금속을 증착하는 단계와, 상기한 금속 위에 포토레지스트를 도포하고 그 위에 광조사한 후 습식각하는 단계와, 그리고 포토레지스트를 제거하는 단계로 이루어진다.First, in the case of using two masks, the process sequence includes depositing an Al-based metal on a transparent substrate, applying a photoresist on the above metal, irradiating light on the wet substrate, and then wet etching, and removing the photoresist. And depositing a Mo-based metal, applying a photoresist on the metal, irradiating the light onto the metal, and wet etching the photoresist, and removing the photoresist.
다음, 1개의 마스크를 이용할 경우 공정순서는, 투명기판 위에 Al계 금속을 증착하는 단계와, 상기한 금속 위에 Mo계 금속을 증착하는 단계와, 상기한 금속 위에 포토레지스트를 도포하고 그 위에 광조사한 후 습식각하는 단계와, 습식각된 금속을 건식각하는 단계와, 그리고 포토레지스트를 제거하는 단계로 이루어진다.Next, in the case of using one mask, the process sequence includes depositing an Al-based metal on a transparent substrate, depositing an Mo-based metal on the metal, applying a photoresist on the metal, and irradiating the light on the metal. And then wet etching, dry etching the wet etched metal, and removing the photoresist.
그러나, 상기한 방법들은 공정수가 너무 많아 생산성이 낮고 원가가 많이 든다는 단점이 있고, 습식각시 환경에 유해한 물질이 다량 배출되는데, 특히 Al계 금속의 습식각시 사용되는 인산은 환경 유해성이 매우 높아 산업상 매우 불리하다.However, the above methods have the disadvantage of low productivity and high cost due to the excessive number of processes, and a large amount of harmful substances are emitted to the environment during wet etching. In particular, phosphoric acid used for wet etching of Al-based metals is highly hazardous to the environment. Very disadvantageous.
도 1은 Mo/Al 2중막을 1종류의 식각액으로 처리한 경우 게이트패턴의 부분단면도를 나타낸다.1 shows a partial cross-sectional view of a gate pattern when the Mo / Al double layer is treated with one type of etchant.
투명기판(10) 위에는 Al금속막(11)이 적층되고, 그 위에 Mo금속막(13)이 적층되어 2중막을 형성한다. 도면의 A영역은 후술하는 언더컷(Undercut) 영역을 나타낸다. 도면으로부터 알 수 있듯이, Mo계 금속/Al계 금속의 2중막을 1종의 식각액에서 식각할 경우, Al계 금속이 Mo계 금속 보다 식각속도가 빨라 동일 시간 기준으로 더 많이 식각되어 Mo금속막(13)의 하부에 Al금속막(11)의 과식각 영역을 만드는데 이러한 현상을 언더컷 현상이라한다. 이러한 언더컷영역에서는 테이퍼(taper)가 좋지 않아 후공정의 절연막 증착공정시에 불량의 원인이 될 수 있으므로, 상기 2중막은 각각의 단일 막에 대한 별도의 식각이 불가피하게 된다.An Al metal film 11 is laminated on the transparent substrate 10, and a Mo metal film 13 is laminated thereon to form a double film. Area A in the figure represents an undercut area described later. As can be seen from the figure, when the double layer of the Mo-based metal / Al-based metal is etched in one type of etchant, the Al-based metal is etched faster than the Mo-based metal and is etched more on the same time basis. The over-etched region of the Al metal film 11 is made at the bottom of 13). This phenomenon is called an undercut phenomenon. In such an undercut region, because the taper is not good, it may cause a defect in the subsequent insulating film deposition process. Therefore, the double layer has to be etched separately for each single film.
본 발명은 상기한 종래 기술의 문제점을 감안하여 이루어진 것으로서, 본 발명의 목적은, 박막트랜지스터의 게이트를 Al계 금속/Ti계 금속의 2중막으로 하여 혼합 식각액에 의해 단일 식각하므로써 공정을 단순화하는 것이다.SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems of the prior art, and an object of the present invention is to simplify the process by single etching with a mixed etchant by using a gate of a thin film transistor as a double layer of Al-based metal / Ti-based metal. .
본 발명의 다른 목적은 상기 식각액으로 요오드산(HiO4)계를 기본으로 한 불산(HF), 질산(HNO3)의 혼합식각액을 사용하므로써 환경을 보호할 수 있도록 하는 것이다.Another object of the present invention is to protect the environment by using a mixed etchant of hydrofluoric acid (HF), nitric acid (HNO 3 ) based on iodic acid (HiO 4 ) system as the etchant.
상기한 목적을 달성하기 위하여, 본 발명에 따른 박막트랜지스터의 게이트패턴은 투명기판 위에 형성된 Al계 금속막과, 상기 Al계 금속막 위에 형성된 Ti막의 2중막으로 이루어지고, 이러한 게이트패턴의 형성은, ① 투명기판 준비, ② Al계금속의 증착, ③ Ti 증착, ④ 사진식각(photolithography), ⑤ 습식각, ⑥ 포토레지스트(PR) 박리의 공정을 따른다.In order to achieve the above object, the gate pattern of the thin film transistor according to the present invention is composed of an Al-based metal film formed on a transparent substrate, and a double film of a Ti film formed on the Al-based metal film, the formation of such a gate pattern, ① Preparation of transparent substrate, ② Deposition of Al-based metal, ③ Ti deposition, ④ photolithography, ⑤ wet etching, ⑥ photoresist (PR) stripping.
도 1은 종래 박막트랜지스터의 Mo/Al게이트의 언더컷 현상을 나타내는 부분단면도.1 is a partial cross-sectional view showing the undercut phenomenon of the Mo / Al gate of the conventional thin film transistor.
도 2는 본 발명에 따른 Ti/Al게이트패턴의 부분단면도.2 is a partial cross-sectional view of a Ti / Al gate pattern according to the present invention.
도 3은 도 2의 Ti/Al게이트패턴의 제조방법을 나타내는 플로우챠트.FIG. 3 is a flowchart showing a method of manufacturing the Ti / Al gate pattern of FIG. 2.
이하, 본 발명의 바람직한 실시예를 도면을 참조하여 상세하게 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
도 2는 본 발명에 따른 Al/Ti게이트패턴의 부분단면도로서, 투명기판(113) 위에는 Al계 금속막(111)과 상기 Al계 금속막(111) 위에 형성된 Ti막(113)의 2중막으로 된 게이트패턴이 형성된다. 이때, 각각의 금속막(111, 113)은 투명기판(110)에 대해 일정각(θ)으로 경사지므로써 우수한 테이퍼 특성을 나타낸다.FIG. 2 is a partial cross-sectional view of an Al / Ti gate pattern according to the present invention, in which a double layer of an Al-based metal film 111 and a Ti film 113 formed on the Al-based metal film 111 is formed on a transparent substrate 113. A gate pattern is formed. At this time, each of the metal films 111 and 113 is inclined at a predetermined angle θ with respect to the transparent substrate 110, thereby exhibiting excellent taper characteristics.
이러한 테이퍼 특성은 도 1과 같은 구조에서 게이트절연막의 도포시 언더컷 영역에서 절연막의 끊어짐과 같은 불량을 근본적으로 예방하므로써 공정의 신뢰성을 향상시키게 된다.This taper characteristic improves process reliability by fundamentally preventing defects such as breakage of the insulating film in the undercut region when the gate insulating film is applied in the structure as shown in FIG. 1.
도 3은 상기 도 2의 게이트패턴의 제조방법을 나타내는 플로우챠트로서, 본 발명의 게이트패턴 제조는, 유리 등의 투명기판을 제공하는 단계(S101)와, 상기 투명기판 위에 Al계 금속을 스퍼터링 방법에 의해 증착하여 Al계 금속막을 형성하는 단계(S103)와, 상기 Al계 금속막 위에 Ti를 스퍼터링방법에 의해 적층하여 Ti막을 형성하는 단계(S105)와, 상기 Al계 금속막 및 Ti막 위에 포토레지스트를 도포하여 광조사하는 단계(S107)와, 계속해서, 상기 Al계 금속막 및 Ti막을 식각액에서 습식각하는 단계(S109)와, 마지막으로 상기 포토레지스트를 현상처리(developing)하여 제거하는 단계(S111)로 이루어진다. 이때, 상기 습식각시 식각액으로는요오드산(HiO4)계를 기본으로 한 불산(HF), 질산(HNO3)의 혼합식각액을 사용한다.FIG. 3 is a flowchart illustrating a method of manufacturing the gate pattern of FIG. 2. The method of manufacturing a gate pattern of the present invention includes providing a transparent substrate such as glass (S101), and sputtering an Al-based metal on the transparent substrate. Forming an Al-based metal film by deposition (S103); depositing Ti on the Al-based metal film by a sputtering method to form a Ti film (S105); and forming a photo on the Al-based metal film and the Ti film. Applying a resist to irradiate light (S107), and subsequently, wet etching the Al-based metal film and Ti film in an etchant (S109), and finally removing the photoresist by developing (S111). In this case, a mixed etchant of hydrofluoric acid (HF) and nitric acid (HNO 3 ) based on iodic acid (HiO 4 ) may be used as the etchant during wet etching.
Al계 금속막과 Ti계 금속막이 상기 혼합식각액에 의해 동시 식각가능한 것은 두 금속 간의 전위차가 없어 단순한 산화/환원 반응에 의해 식각되기 때문이다. 이러한 식각의 반응메카니즘은 이하의 식을 따른다.The reason why the Al-based metal film and the Ti-based metal film can be simultaneously etched by the mixed etching solution is because there is no potential difference between the two metals and the etching is performed by a simple oxidation / reduction reaction. The reaction mechanism of this etching follows the following formula.
본 발명에 따르면, 투명기판 위에 형성된 Al계 금속막과, 상기 Al계 금속막 위에 형성된 Ti막의 2중막으로 사용하고 요오드산, 불산, 질산의 혼합식각액을 이용하여 단일 식각하므로써 테이퍼특성이 우수한 게이트패턴을 얻을 수 있다.According to the present invention, an Al-based metal film formed on a transparent substrate and a Ti film formed on the Al-based metal film are used as a double layer, and a gate pattern excellent in taper characteristics by single etching using a mixed etching solution of iodine acid, hydrofluoric acid, and nitric acid Can be obtained.
더욱, 상기 혼합식각액은 환경 유해물질이 아니므로 환경보호에도 유리하다.In addition, the mixed etchant is also an environmental protection material is not harmful to the environment.
Claims (6)
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| JPH07169967A (en) * | 1993-12-16 | 1995-07-04 | Matsushita Electric Ind Co Ltd | Liquid crystal display device and its manufacture |
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