KR100319400B1 - 반도체패키지및그제조방법 - Google Patents
반도체패키지및그제조방법 Download PDFInfo
- Publication number
- KR100319400B1 KR100319400B1 KR1019980061610A KR19980061610A KR100319400B1 KR 100319400 B1 KR100319400 B1 KR 100319400B1 KR 1019980061610 A KR1019980061610 A KR 1019980061610A KR 19980061610 A KR19980061610 A KR 19980061610A KR 100319400 B1 KR100319400 B1 KR 100319400B1
- Authority
- KR
- South Korea
- Prior art keywords
- lead frame
- semiconductor chip
- circuit pattern
- manufacturing
- conductive
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
Claims (3)
- 반도체칩(30)과;상기 반도체칩(30)의 하면에 접착수단(20)으로 다수의 회로패턴부(16)가 접착되어 있고, 상기 회로패턴부(16)는 상기 반도체칩(30) 하면의 내주연 및 외주연으로 연장되어 있으며, 상기 반도체칩(30)의 외주연으로 연장된 회로패턴부(16) 상면에는 다수의 본딩부(12)가 형성되고 있으며, 상기 회로패턴부(16) 하면 전체에는 풀어레이형(Full Array Type)으로 볼랜드부(14)가 형성된 대략 판상의 리드프레임(10)과;상기 반도체칩(30)과 상기 리드프레임(10)의 본딩부(12)를 상호 전기적으로 접속하는 도전성와이어(40)와;상기 반도체칩(30) 및 도전성와이어(40)와, 상기 반도체칩(30) 외주연의 리드프레임(10) 상면을 봉지하는 봉지재(40)와;상기 리드프레임(10)의 하면 전체에 부착되어 있되, 상기 리드프레임(10)의 각 볼랜드부(14)와 대응되는 위치에는 관통부(62)가 형성된 절연성의 커버코트(60)와;상기 커버코트(60)의 관통부(62)를 통해 노출된 볼랜드부(14)에 형성된 도전성볼(70)을 포함하여 이루어진 반도체패키지.
- 다수의 회로패턴부(16)가 형성되고, 상기 회로패턴부(16)의 상면에는 다수의본딩부(12)가 형성되고, 상기 회로패턴부(16) 하면 전체에는 풀어레이형(Full Array Type)으로 볼랜드부(14)가 형성된 대략 판상의 리드프레임(10)을 제공하는 단계와;상기 리드프레임(10)의 하면에 절연성 커버코트(60)를 부착하는 단계와;상기 리드프레임(10)의 상면에 접착수단(20)을 개재한 후 반도체칩(30)을 부착하는 단계와;상기 반도체칩(30)과 리드프레임(10)의 본딩부(12)를 도전성와이어(40)로 접속하는 단계와;상기 반도체칩(30)과 도전성와이어(40) 및 리드프레임(10)의 상면을 봉지재(50)로 봉지하는 단계와;상기 리드프레임(10)의 하면에 부착되어 있는 커버코트(60) 중 리드프레임(10)의 볼랜드부(14) 하면과 대응되는 부분에 관통부(62)를 형성하는 단계와;상기 관통부(62)를 통해 노출된 리드프레임(10)의 볼랜드부(14)에 도전성볼(70)이 부착되는 단계를 포함하여 이루어진 반도체패키지 제조방법.
- 제2항에 있어서, 상기 관통부(62) 형성 단계는 레이저빔, 화학적 에칭 또는 빛의 조사중 어느 하나에 의해 이루어짐을 특징으로 하는 반도체패키지 제조 방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019980061610A KR100319400B1 (ko) | 1998-12-30 | 1998-12-30 | 반도체패키지및그제조방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019980061610A KR100319400B1 (ko) | 1998-12-30 | 1998-12-30 | 반도체패키지및그제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20000045084A KR20000045084A (ko) | 2000-07-15 |
KR100319400B1 true KR100319400B1 (ko) | 2002-05-13 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019980061610A KR100319400B1 (ko) | 1998-12-30 | 1998-12-30 | 반도체패키지및그제조방법 |
Country Status (1)
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101006907B1 (ko) | 2008-02-20 | 2011-01-13 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 제조 방법 |
KR20170017319A (ko) | 2015-08-06 | 2017-02-15 | 주식회사 레오퍼니쳐 | 가구용 문판 조립체 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100583496B1 (ko) * | 2000-08-14 | 2006-05-24 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지용 회로기판 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0936275A (ja) * | 1995-07-21 | 1997-02-07 | Toshiba Corp | 表面実装型半導体装置の製造方法 |
JPH0997868A (ja) * | 1995-09-28 | 1997-04-08 | Dainippon Printing Co Ltd | リードフレーム部材及びその製造方法 |
-
1998
- 1998-12-30 KR KR1019980061610A patent/KR100319400B1/ko not_active IP Right Cessation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0936275A (ja) * | 1995-07-21 | 1997-02-07 | Toshiba Corp | 表面実装型半導体装置の製造方法 |
JPH0997868A (ja) * | 1995-09-28 | 1997-04-08 | Dainippon Printing Co Ltd | リードフレーム部材及びその製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101006907B1 (ko) | 2008-02-20 | 2011-01-13 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 제조 방법 |
KR20170017319A (ko) | 2015-08-06 | 2017-02-15 | 주식회사 레오퍼니쳐 | 가구용 문판 조립체 |
Also Published As
Publication number | Publication date |
---|---|
KR20000045084A (ko) | 2000-07-15 |
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