KR100315447B1 - Shallow trench manufacturing method for isolating semiconductor devices - Google Patents
Shallow trench manufacturing method for isolating semiconductor devices Download PDFInfo
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- KR100315447B1 KR100315447B1 KR1019990010294A KR19990010294A KR100315447B1 KR 100315447 B1 KR100315447 B1 KR 100315447B1 KR 1019990010294 A KR1019990010294 A KR 1019990010294A KR 19990010294 A KR19990010294 A KR 19990010294A KR 100315447 B1 KR100315447 B1 KR 100315447B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000004065 semiconductor Substances 0.000 title abstract description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 22
- 239000010703 silicon Substances 0.000 claims abstract description 22
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 13
- 150000004767 nitrides Chemical class 0.000 claims abstract description 11
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims abstract description 9
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 15
- 238000000059 patterning Methods 0.000 claims description 2
- 238000000354 decomposition reaction Methods 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 238000002955 isolation Methods 0.000 abstract description 18
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 7
- 239000000126 substance Substances 0.000 abstract description 6
- 238000005498 polishing Methods 0.000 abstract description 3
- 238000001039 wet etching Methods 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 230000010354 integration Effects 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 17
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000007935 neutral effect Effects 0.000 description 3
- 230000035945 sensitivity Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 125000002524 organometallic group Chemical group 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
- H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
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Abstract
반도체 소자 분리를 위한 얕은 트렌치에 산화막을 매입한 후 나타나는 심 현상을 방지하기 위하여, 실리콘웨이퍼 상부에 패드 산화막과 질화막을 형성하고, 질화막과 패드 산화막을 패터닝하여 모트 패턴을 형성하고, 이를 마스크로 실리콘웨이퍼를 모트 식각하여 트렌치를 형성한 후, 실리콘웨이퍼를 열산화하여 트렌치 내벽에 라이너 산화막을 형성한다. 그리고, N2O 플라즈마 전처리로 라이너 산화막 상부를 전하적으로 중성화시킨 다음, 500℃, 760Torr, 130g/m3내지 135g/m3오존 농도하에서 TEOS/O3상압 화학 기상 증착으로 NSG막을 증착하여 트렌치를 매입한다. 따라서, 트렌치에 NSG막을 매입한 후 발생하는 심 현상을 방지할 수 있어, 후속의 화학 기계적 연마, 습식 식각 및 불산 디글래이즈 동안의 손상을 최소화하여 집적화로 소자의 전기적 특성인 전류 누설을 안정적으로 줄일 수 있어 반도체 소자 제조 공정의 수율을 향상시키며, 반도체 소자의 신뢰성을 향상시킨다.In order to prevent the core phenomenon after embedding the oxide film in the shallow trench for semiconductor device isolation, a pad oxide film and a nitride film are formed on the silicon wafer, and the nitride film and the pad oxide film are patterned to form a moat pattern, and the silicon is used as a mask. After forming the trench by mort etching the wafer, the silicon wafer is thermally oxidized to form a liner oxide film on the inner wall of the trench. Then, the upper portion of the liner oxide was neutralized by N 2 O plasma pretreatment, and then the NSG film was deposited by TEOS / O 3 atmospheric pressure chemical vapor deposition at 500 ° C., 760 Torr, and 130 g / m 3 to 135 g / m 3 ozone concentration. Purchase Therefore, it is possible to prevent the seam phenomenon occurring after embedding the NSG film in the trench, thereby minimizing damage during subsequent chemical mechanical polishing, wet etching, and hydrofluoric acid degradation, thereby stably preventing current leakage, an electrical characteristic of the device through integration. It can be reduced to improve the yield of the semiconductor device manufacturing process, and improve the reliability of the semiconductor device.
Description
본 발명은 반도체 소자를 제조하는 공정에 관한 것으로, 더욱 상세하게는 반도체 소자의 제조 공정중 반도체 소자와 소자 간을 전기적으로 격리하기 위한 얕은 트렌치를 제조하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process for manufacturing a semiconductor device, and more particularly, to a method of manufacturing a shallow trench for electrically isolating a semiconductor device from a device during a semiconductor device manufacturing process.
일반적으로 반도체 소자를 분리하는 방법으로는 선택적 산화법으로 질화막을 이용하는 LOCOS(local oxidation of silicon) 소자 분리 방법이 이용되어 왔다.In general, a method of separating a semiconductor device has been used a local oxidation of silicon (LOCOS) device separation method using a nitride film as a selective oxidation method.
LOCOS 소자 분리 방법은 질화막을 마스크로 하여 실리콘웨이퍼 자체를 열산화시키기 때문에 공정이 간소해서 산화막의 소자 응력 문제가 적고, 생성되는 산화막질이 좋다는 이점이 있다.Since the LOCOS device isolation method uses a nitride film as a mask to thermally oxidize the silicon wafer itself, there is an advantage that the process is simple and the device stress problem of the oxide film is small, and the resulting oxide film is good.
그러나, LOCOS 소자 분리 방법을 이용하면 소자 분리 영역이 차지하는 면적이 크기 때문에 소자의 미세화에 한계가 있을 뿐만 아니라 버즈 비크(bird's beak)가 발생하게 된다.However, when the LOCOS device isolation method is used, the area of the device isolation region is large, thereby limiting device miniaturization and generating bird's beaks.
이러한 것을 극복하기 위해 LOCOS 소자 분리 방법을 대체하는 기술로서 트렌치 소자 분리(STI ; shallow trench isolation)가 있다. 트렌치 소자 분리에서는 실리콘웨이퍼에 트렌치를 만들어 절연물을 집어넣기 때문에 소자 분리 영역이 차지하는 면적이 작아서 소자의 미세화에 유리하다.In order to overcome this, a trench trench isolation (STI) technique is an alternative to the LOCOS isolation scheme. In trench device isolation, since trenches are made in silicon wafers to insulate the insulating material, the area occupied by the device isolation region is small, which is advantageous for miniaturization of devices.
그러면, 첨부된 도 1a 내지 도 1c를 참조하여 종래 반도체 소자 분리를 위한 얕은 트렌치를 제조하는 방법을 설명한다.Next, a method of manufacturing a shallow trench for separating a conventional semiconductor device will be described with reference to FIGS. 1A to 1C.
먼저 도 1a에 도시한 바와 같이, 실리콘웨이퍼(1)를 열산화하여 패드 산화막(2)을 성장시키고, 그 상부에 화학 기상 증착(CVD ; chemical vapor deposition)으로 질화막(3)을 증착한다.First, as shown in FIG. 1A, the silicon wafer 1 is thermally oxidized to grow the pad oxide film 2, and the nitride film 3 is deposited by chemical vapor deposition (CVD) thereon.
그 다음 도 1b에 도시한 바와 같이, 반도체 소자가 형성될 액티브 영역(active region)과 반도체 소자 분리 영역이 형성될 필드 영역(field region)을 구분하기 위하여 질화막(3)과 패드 산화막(2)을 패터닝하여 모트(moat) 패턴을 형성한 후, 모트 패턴을 마스크로 드러난 실리콘웨이퍼(1)를 모트 식각하여 반도체 소자 분리 영역에 얕은 트렌치로 형성한다. 그리고, 실리콘웨이퍼(1)를 열산화하여 트렌치 내벽에 라이너 산화막(4)을 성장시킨다. 이때, 라이너 산화막(4)은 실리콘웨이퍼(1)의 모트 식각에 의한 손상을 보상함과 동시에 후속 공정에서 증착되는 물질에 대한 글루(glue)층 역할을 한다.Next, as shown in FIG. 1B, the nitride film 3 and the pad oxide film 2 are formed to distinguish the active region in which the semiconductor device is to be formed and the field region in which the semiconductor device isolation region is to be formed. After patterning to form a moat pattern, the silicon wafer 1 exposed by the mask as a mask is mortally etched to form a shallow trench in the semiconductor device isolation region. Then, the silicon wafer 1 is thermally oxidized to grow the liner oxide film 4 on the inner wall of the trench. At this time, the liner oxide layer 4 serves as a glue layer to the material deposited in a subsequent process while compensating for damage caused by the mort etching of the silicon wafer 1.
그 다음 도 1c에 도시한 바와 같이, TEOS(tetraethylorthosilicate)/O3상압 화학 기상 증착(APCVD ; atmospheric pressure chemical vapor deposition) 방식으로 760Torr 공정 압력하에서 유기금속(organometallic) 액체 소스 화학 물질인 TEOS와 오존(O3)의 열 화학 기상 증착에 의해 산화막(5)을 증착하여 액티브 영역과 필드 영역 간의 소자 분리를 완성한다.Next, as shown in FIG. 1C, TEOS and ozone (organometallic liquid source chemicals) under 760 Torr process pressure are used by TEOS (tetraethylorthosilicate) / O 3 atmospheric pressure chemical vapor deposition (APCVD) method. The oxide film 5 is deposited by thermal chemical vapor deposition of O 3 ) to complete device isolation between the active region and the field region.
이와 같은 종래의 방법에서는 TEOS/O3상압 화학 기상 증착 막의 일반적인 단점으로 지적되는 웨이퍼 표면에서의 하부 유전체의 화학적 조성(chemical composition) 및 표면 전위 차이에 따른 표면 감도(surface sensitivity) 영향을 극복하지 못한다. 따라서, 웨이퍼 표면에서의 민감한 표면 감도 영향에 의해 얕은 트렌치 부위에서 산화막의 증착후 심(seam ; polymer filament) 현상(도 1c의 6)이 발생된다. 즉, 라이너 산화막은 일반적으로 표면에 불안정한 전위가 잔재한다. 이는 제조상에서 트렌치 형성을 위한 모트 식각시 패턴 밀도간의 전위 차이에 기인하는데, 이러한 특성위에 트렌치를 매입할 경우 상압 화학 기상 증착막의 특성상 표면에서의 흐름성에 영향을 주어 심을 유발시키게 된다. 심은 상압 화학 기상 증착 TEOS/O3공정에서 얕은 트렌치 부위에서 하부막 종류와 트렌치 만곡(curvature) 구조 접경면에 잔재하는 전위 차 및 트렌치 매입시 적층되는 각 막의 계면간 등각 특성(conformal nature)에 기인하여 나타나는 가는 선이다.This conventional method does not overcome the surface sensitivity effects due to the chemical composition and surface potential differences of the underlying dielectric at the wafer surface, which is pointed out as a general disadvantage of TEOS / O 3 atmospheric pressure chemical vapor deposition films. . Accordingly, a polymer filament phenomenon (6 in FIG. 1C) after deposition of the oxide film occurs in the shallow trench region due to the sensitive surface sensitivity effect on the wafer surface. That is, the liner oxide film generally has an unstable potential on its surface. This is due to the potential difference between the pattern densities during the etching of the mort for forming trenches in manufacturing. If the trench is buried in this characteristic, the characteristics of the atmospheric chemical vapor deposition film affect the flowability on the surface, causing seam. In the atmospheric atmospheric chemical vapor deposition TEOS / O 3 process, due to the potential difference remaining on the lower film type and the trench curvature boundary surface in the shallow trench region and the conformal nature of each film laminated during the trench filling It is a thin line that appears.
그리고, 이러한 심은 후속의 얕은 트렌치를 평탄화하기 위한 화학 기계적 연마(CMP, chemical mechanical polishing), 질화막을 제거하기 위한 습식 식각 및불산(HF) 디글래이즈(deglaze) 동안 손상을 받아 심 틈새가 벌어져 전류 누설의 요인이 되어 집적회로 소자의 전기적 신뢰성에 큰 영향을 주게 된다.These seams are then damaged during chemical mechanical polishing (CMP) to flatten subsequent shallow trenches, wet etching and hydrofluoric acid (HF) deglaze to remove the nitride film, resulting in seam gaps resulting in current. Leakage causes a great influence on the electrical reliability of the integrated circuit device.
본 발명은 이와 같은 문제점을 해결하기 위한 것으로, 그 목적은 반도체 소자 분리를 위한 얕은 트렌치에 산화막을 매입한 후 나타나는 심 현상을 방지하는 데 있다.The present invention has been made to solve such a problem, and an object thereof is to prevent a core phenomenon that occurs after embedding an oxide film in a shallow trench for semiconductor device isolation.
도 1a 내지 도 1c는 종래의 방법에 따라 반도체 소자 분리를 위한 얕은 트렌치를 제조하는 공정을 개략적으로 도시한 실리콘웨이퍼의 단면도이고,1A to 1C are cross-sectional views of silicon wafers schematically illustrating a process of manufacturing a shallow trench for semiconductor device isolation according to a conventional method;
도 2a 내지 도 2d는 본 발명에 따라 반도체 소자 분리를 위한 얕은 트렌치를 제조하는 공정을 개략적으로 도시한 실리콘웨이퍼의 단면도이다.2A-2D are cross-sectional views of silicon wafers schematically illustrating a process of manufacturing a shallow trench for semiconductor device isolation in accordance with the present invention.
상기와 같은 목적을 달성하기 위하여, 본 발명은 트렌치를 매입하기 위하여 TEOS/O3상압 화학 기상 증착으로 얇은 NSG막을 증착하기 이전에, N2O 플라즈마 전처리로 트렌치 내벽의 라이너 산화막 상부를 전하적으로 중성 상태가 되도록 하는 것을 특징으로 한다.In order to achieve the above object, the present invention charges the upper portion of the liner oxide layer on the inner wall of the trench by N 2 O plasma pretreatment before depositing a thin NSG film by TEOS / O 3 atmospheric pressure chemical vapor deposition to fill the trench. It is characterized by being in a neutral state.
상기에서 TEOS/O3상압 화학 기상 증착은 500℃, 760Torr, 130g/m3내지 135g/m3오존 농도하에서 실시하는 것이 바람직하다.TEOS / O 3 atmospheric pressure chemical vapor deposition is preferably carried out at 500 ℃, 760 Torr, 130g / m 3 to 135g / m 3 ozone concentration.
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 일 실시예를 설명한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 따라 반도체 소자 분리를 위한 얕은 트렌치를 제조하는 공정을 개략적으로 도시한 실리콘웨이퍼의 단면도이다.2A-2D are cross-sectional views of silicon wafers schematically illustrating a process of manufacturing a shallow trench for semiconductor device isolation in accordance with the present invention.
먼저 도 2a에 도시한 바와 같이, 실리콘웨이퍼(11)를 열산화하여 패드 산화막(12)을 성장시키고, 그 상부에 화학 기상 증착으로 질화막(13)을 증착한다.First, as shown in FIG. 2A, the silicon wafer 11 is thermally oxidized to grow the pad oxide film 12, and the nitride film 13 is deposited by chemical vapor deposition on the silicon wafer 11.
그 다음 도 2b에 도시한 바와 같이, 반도체 소자가 형성될 액티브 영역과 반도체 소자 분리 영역이 형성될 필드 영역을 구분하기 위하여 질화막(13)과 패드 산화막(12)을 패터닝하여 모트 패턴을 형성한 후, 모트 패턴을 마스크로 드러난 실리콘웨이퍼(11)를 모트 식각하여 반도체 소자 분리 영역에 얕은 트렌치를 형성한다. 그리고, 실리콘웨이퍼(11)를 열산화하여 트렌치 내벽에 라이너 산화막(14)을 형성한다. 이때, 라이너 산화막(14)은 실리콘웨이퍼(11)의 모트 식각에 의한 손상을 보상함과 동시에 후속 공정에서 증착되는 물질에 대한 글루층 역할을 한다. 그러나, 라이너 산화막(14)은 표면에 불안정한 전위가 잔재한다.Next, as shown in FIG. 2B, the nitride layer 13 and the pad oxide layer 12 are patterned to form a mort pattern to distinguish the active region where the semiconductor element is to be formed and the field region where the semiconductor element isolation region is to be formed. Then, the silicon wafer 11 exposed by the mask of the mort pattern is mort-etched to form a shallow trench in the semiconductor device isolation region. The silicon wafer 11 is thermally oxidized to form a liner oxide film 14 on the inner wall of the trench. In this case, the liner oxide layer 14 compensates for the damage caused by the mort etching of the silicon wafer 11 and serves as a glue layer for the material deposited in a subsequent process. However, the liner oxide film 14 has an unstable potential on its surface.
따라서, 도 2c에 도시한 바와 같이, 실리콘웨이퍼(11) 전면을 N2O 플라즈마 전처리 즉, 라이너 산화막(14) 상부를 N2O 플라즈마 전처리한다. 그러면, 라이너 산화막(14)의 표면의 전위가 둔화되어 표면은 거의 전하적으로 중성 상태로 전이되므로 표면 감도가 둔화된 표면을 유지시켜 준다.Therefore, as shown in FIG. 2C, the entire surface of the silicon wafer 11 is N 2 O plasma pretreated, that is, the upper portion of the liner oxide film 14 is N 2 O plasma pretreated. Then, the potential of the surface of the liner oxide film 14 is slowed down so that the surface is almost charged to a neutral state, thereby maintaining the surface at which the surface sensitivity is slowed down.
그 다음 도 2d에 도시한 바와 같이, N2O 플라즈마 전처리가 끝난 라이너 산화막(14) 표면위에 TEOS/O3상압 화학 기상 증착 바람직하게는, 500℃, 760Torr, 130g/m3내지 135g/m3정도의 오존 농도하에서 유기금속 액체 소스 화학 물질인 TEOS와 반응 분해시킨 NSG(nondoped silicate glass)막으로서의 산화막(15)을 증착하여 트렌치를 완전히 매입하여 액티브 영역과 필드 영역 간의 소자 분리를 완성한다. 이때, 매입된 NSG막으로서의 산화막(15)은 하부 라이너 산화막(14) 표면의 전하적 중성 상태에 의해 유동성에 영향을 받아 안정한 산화막 망상 조직(network structure)을 형성하여 심 현상이 없는 양질의 막을 얻을 수 있다.Then, as shown in FIG. 2D, TEOS / O 3 atmospheric pressure chemical vapor deposition on the surface of the N 2 O plasma pretreated liner oxide film 14 is preferably 500 ° C., 760 Torr, 130 g / m 3 to 135 g / m 3. At a degree of ozone concentration, an oxide film 15 is deposited as a non-doped silicate glass (NSG) film which is reactively decomposed with TEOS, an organometallic liquid source chemical, to completely fill the trenches, thereby completing device isolation between the active and field regions. At this time, the buried oxide film 15 as the NSG film is influenced by the fluidity by the charge neutral state on the surface of the lower liner oxide film 14 to form a stable oxide film network structure to obtain a high quality film without core phenomenon. Can be.
이와 같이 본 발명은 트렌치에 NSG막을 매입한 후 발생하는 심 현상을 방지할 수 있어, 후속의 화학 기계적 연마, 습식 식각 및 불산 디글래이즈 동안의 손상을 최소화하여 집적회로 소자의 전기적 특성인 전류 누설을 안정적으로 줄일 수 있어 반도체 소자 제조 공정의 수율을 향상시킬 수 있을 뿐만 아니라 반도체 소자의 신뢰성을 향상시킬 수 있다.As such, the present invention can prevent seam phenomenon occurring after embedding an NSG film in a trench, thereby minimizing damage during subsequent chemical mechanical polishing, wet etching, and hydrofluoric acid degrading, thereby preventing current leakage, which is an electrical characteristic of an integrated circuit device. Can be stably reduced, so that the yield of the semiconductor device manufacturing process can be improved and the reliability of the semiconductor device can be improved.
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