KR100310257B1 - Method of forming minute pattern in semiconductor device - Google Patents
Method of forming minute pattern in semiconductor device Download PDFInfo
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- KR100310257B1 KR100310257B1 KR1019990032423A KR19990032423A KR100310257B1 KR 100310257 B1 KR100310257 B1 KR 100310257B1 KR 1019990032423 A KR1019990032423 A KR 1019990032423A KR 19990032423 A KR19990032423 A KR 19990032423A KR 100310257 B1 KR100310257 B1 KR 100310257B1
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000005530 etching Methods 0.000 claims abstract description 43
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims description 20
- 230000008021 deposition Effects 0.000 claims description 11
- 238000009413 insulation Methods 0.000 claims description 8
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 21
- 239000010410 layer Substances 0.000 description 24
- 229910052751 metal Inorganic materials 0.000 description 14
- 239000002184 metal Substances 0.000 description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 238000013461 design Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- -1 silicide transition metal Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000013077 target material Substances 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 238000003079 width control Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
반도체소자의 미세 패턴의 제조방법에 대해 개시되어 있다. 본 발명은 반도체기판 상부에 희생 절연막을 증착한 후에 희생 절연막 상부에 미세 패턴의 식각 마스크를 위한 감광막 패턴을 형성하고, 감광막 패턴의 양측면을 소정 부분 식각하여 그 선폭을 줄이고, 감광막 패턴을 식각 마스크로 삼아 희생 절연막을 식각해서 희생 절연막 패턴을 형성한 후에 감광막 패턴을 제거하고, 결과물에 도전막 또는 식각 선택비가 다른 희생 절연막을 증착하고 이를 식각해서 희생 절연막 패턴 측면에 미세한 패턴을 형성한다. 따라서, 본 발명은 통상의 노광 공정으로 형성된 패턴보다 2배 이상의 해상도를 가지는 미세 패턴을 형성하여 고가인 노광장비를 사용하지 않고서도 원하는 미세 패턴을 확보할 수 있어 제조 공정이 용이해진다.A method for producing a fine pattern of a semiconductor device is disclosed. According to the present invention, after the sacrificial insulating film is deposited on the semiconductor substrate, a photoresist pattern for a fine pattern etch mask is formed on the sacrificial insulating film, and both sides of the photoresist pattern are partially etched to reduce the line width, and the photoresist pattern is used as an etch mask. For example, after the sacrificial insulating film is etched to form the sacrificial insulating film pattern, the photoresist pattern is removed, and a sacrificial insulating film having a different conductive film or etch selectivity is deposited on the resultant, and the fine film is formed on the side of the sacrificial insulating film pattern by etching. Therefore, the present invention can form a fine pattern having a resolution twice or more than a pattern formed by a normal exposure process to ensure a desired fine pattern without using expensive exposure equipment, thereby facilitating a manufacturing process.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 노광장비의 해상한계를 넘는 미세패턴을 형성할 수 있는 반도체소자의 미세 패턴의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a fine pattern of a semiconductor device capable of forming a fine pattern exceeding a resolution limit of an exposure apparatus.
현재, 반도체 장치의 고집적화 추세에 따라 미세 패턴의 선폭은 점차 짧아져 근래에는 0.15㎛이하의 설계 규칙이 요구되고 있다. 또한, 피가공 대상물도 단결정 실리콘, 폴리 실리콘, 실리콘산화막, 알루미늄 등의 통상의 재료에 한정되는 것이 아니라 질화물, 실리사이드 천이 금속등으로까지 다양화되고 있다.At present, with the trend of higher integration of semiconductor devices, the line width of the fine pattern is gradually shortened, and in recent years, a design rule of 0.15 µm or less is required. In addition, the object to be processed is not limited to conventional materials such as single crystal silicon, polysilicon, silicon oxide film, and aluminum, but is diversified to nitride, silicide transition metal, and the like.
일반적으로 반도체장치의 제조에 있어서, 통상의 반도체소자의 패턴은 감광성 중합체 패턴을 마스크로 하여 하층막을 식각하는 포토리소그래피(photolithography) 공정을 이용하고 있는 바, 이러한 종래의 미세패턴의 형성방법을 설명하면 다음과 같다.In general, in the manufacture of a semiconductor device, a pattern of a conventional semiconductor device uses a photolithography process in which an underlayer film is etched using a photosensitive polymer pattern as a mask. As follows.
먼저, 하지층(下地層)이 형성된 반도체기판의 상부에 식각대상 물질층인 피식각층을 형성한다. 피식각층 상부에 감광물질을 약 0.5㎛ 내지 3㎛ 두께로 도포한 후, 노광마스크를 이용한 노광공정을 실시하고, 이를 현상하여 식각마스크인 감광막패턴을 얻는다.First, an etching target layer, which is an etching target material layer, is formed on an upper portion of a semiconductor substrate on which an underlayer is formed. After the photosensitive material is coated on the etched layer to a thickness of about 0.5 μm to 3 μm, an exposure process using an exposure mask is performed and developed to obtain a photoresist pattern that is an etching mask.
그 다음, 건식식각 또는 습식식각공정을 적용하여 감광막패턴이 형성되지 않은 노출부분의 피식각층을 제거하고, 감광막패턴을 제거함으로써 원하는 최종패턴을 형성한다.Then, a dry etching or a wet etching process is applied to remove the etched layer of the exposed portion where the photoresist pattern is not formed, and the desired final pattern is formed by removing the photoresist pattern.
한편, 상기와 같이 종래의 리소그래피 공정에 있어서, 해상도(resolution)는 다음의 레이리 식(Rayleigh's Equation)에 의해 결정된다.On the other hand, in the conventional lithography process as described above, the resolution is determined by the following Rayleigh's Equation.
여기서, R은 해상도, λ는 노광파장, NA는 노광장비의 렌즈의 개구수(numerical aperture)를 나타내며, k는 공정관련 상수로서 공정능력에 따라 변하는 값이지만 양산단계에서는 대략 0.7 정도이다.Here, R is the resolution, λ is the exposure wavelength, NA is the numerical aperture of the lens of the exposure equipment, k is a process-related constant, a value that varies depending on process capability, but is about 0.7 in the mass production stage.
그런데, 노광파장에 있어서, 현재 양산단계에서 주로 사용되는 광원인 g-선(g-line)은 0.436㎛, i-선(i-line)은 0.365㎛이고, 최근 양산단계에 도입되고 있는 심자외선(Deep Ultra Violet; 이하 DUV라 약칭한다) 광원은 0.248㎛이다. 렌즈의 개구수를 대략 0.5라고 할 때, 상기 수학식 1에 각각의 변수값을 대입하면 g-선, i-선, DUV에 대해 각각 0.5㎛, 0.4㎛, 0.3㎛ 정도의 값을 각각 가진다.However, in exposure wavelength, g-line (g-line), which is a light source mainly used in the mass production stage, is 0.436 µm and i-line (i-line) is 0.365 µm, and deep ultraviolet rays recently introduced in the mass production stage (Deep Ultra Violet; hereinafter abbreviated as DUV) The light source is 0.248 mu m. When the numerical aperture of the lens is about 0.5, the values of 0.5 μm, 0.4 μm, and 0.3 μm for the g-line, i-line, and DUV, respectively, are substituted for each variable in Equation 1 above.
따라서, 해상도를 향상시키기 위해서는 노광장비에 사용되는 광원의 파장이 짧을수록 유리하다는 것을 알 수 있다. 이를 위해서는 g-선보다는 i-선, 그보다는 DUV나 소프트 X-선을 이용하는 장비가 바람직하다.Therefore, in order to improve the resolution, it can be seen that the shorter the wavelength of the light source used in the exposure equipment is advantageous. For this purpose, equipment using i-rays rather than g-rays, rather DUV or soft X-rays is preferred.
그러나, 짧은 파장의 노광원을 얻기가 어렵기 때문에, 짧은 파장의 광원을 사용하는 장비일수록 장비의 가격이 기하급수적으로 증가하여 반도체장치의 제조원가가 상승된다. 또한, DUV보다 짧은 파장의 광원을 사용하는 장비는 현재 개발 중에 있다.However, since it is difficult to obtain an exposure source having a short wavelength, the cost of the equipment increases exponentially as the equipment using the short wavelength light source increases the manufacturing cost of the semiconductor device. In addition, equipment using light sources with shorter wavelengths than DUV is currently under development.
그러므로, 반도체소자의 선폭을 조정하는 노광 공정은 광학 노광장비상 이미 한계에 도달하게 되었다. 또한, 설계 규칙이 낮아짐에 따라 공정 여유도 역시 낮아져 오배열 및 오정렬 등의 문제점이 드러나게 되었다. 이를 위해서 전자빔을 이용하여 노광 공정을 실시하고 있지만, 장시간의 공정으로 인한 생산 수율 감소 및 장비의 고가로 인하여 생산 원가 증가 등의 많은 단점을 수반하게 되었다.Therefore, the exposure process for adjusting the line width of the semiconductor element has already reached its limit in optical exposure equipment. In addition, as the design rules are lowered, the process margin is also lowered, which causes problems such as misalignment and misalignment. For this purpose, the exposure process is carried out using an electron beam, but it is accompanied by a number of disadvantages such as reduced production yield due to a long process and increased production cost due to the high cost of equipment.
따라서, 차세대의 고집적 반도체장치의 미세패턴의 제조 공정시 정확한 선폭 조절의 재현성, 식각 공정시 패터닝된 감광막과 같은 선폭의 유지, 탄소로 이루어진 감광막을 사용함에 따라 하지층인 산화막과의 선택비 저하 등의 문제점이 있었다.Therefore, the reproducibility of precise line width control in the manufacturing process of fine patterns of the next generation of highly integrated semiconductor devices, the maintenance of the line width such as the patterned photoresist film during the etching process, the decrease in selectivity with the oxide film as the underlying layer by using the photosensitive film made of carbon, etc. There was a problem.
본 발명의 목적은 통상의 감광막 패턴의 폭을 소정 크기로 줄여 그 하부의 희생 절연막을 식각한 후에 그 측면에 스페이서로 이루어진 도전막 패턴을 형성함으로써 통상의 노광공정으로 형성된 패턴보다 2배 이상의 해상도를 가지는 반도체소자의 미세 패턴의 제조방법을 제공하는데 있다.An object of the present invention is to reduce the width of the conventional photosensitive film pattern to a predetermined size to etch the sacrificial insulating film at the bottom thereof to form a conductive film pattern consisting of spacers on the side thereof to achieve a resolution at least twice as high as the pattern formed by the conventional exposure process. The present invention provides a method of manufacturing a fine pattern of a semiconductor device.
본 발명의 다른 목적은 감광막 패턴의 폭을 소정 크기로 줄여 그 하부의 희생 절연막을 식각한 후에 그 측면에 절연막 식각 패턴을 형성함으로써 노광장비의 한계 해상도를 벗어나 미세패턴을 형성할 수 있는 반도체소자의 미세 패턴의 제조방법을 제공하는데 있다.Another object of the present invention is to reduce the width of the photoresist pattern to a predetermined size and to form a fine pattern out of the limit resolution of the exposure equipment by etching the sacrificial insulating film beneath it and forming an insulating film etching pattern on the side thereof. It is to provide a method for producing a fine pattern.
도 1a 내지 도 1f는 본 발명의 일실시예에 따른 반도체소자의 미세 게이트전극 패턴 제조방법을 설명하기 위한 공정 순서도,1A to 1F are flowcharts illustrating a method of manufacturing a fine gate electrode pattern of a semiconductor device according to an embodiment of the present invention;
도 2a 내지 도 2b는 본 발명의 다른 실시예에 따른 반도체소자의 금속 배선 패턴 제조방법을 설명하기 위한 공정 순서도.2A to 2B are process flowcharts illustrating a metal wiring pattern manufacturing method of a semiconductor device according to another embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10: 반도체기판 12: 희생 절연막10: semiconductor substrate 12: sacrificial insulating film
12': 희생 절연막 패턴 14: 감광막 패턴12 ': sacrificial insulating film pattern 14: photosensitive film pattern
14': 측면이 식각된 감광막 패턴14 ': side-etched photoresist pattern
16: 도전막 16': 도전막 패턴16: conductive film 16 ': conductive film pattern
20: 하지층 22: 식각 선택비가 다른 절연막 패턴20: base layer 22: insulating film pattern with different etching selectivity
24': 금속 패턴24 ': metal pattern
상기 목적을 달성하기 위하여 본 발명은 노광장비 및 식각 공정을 이용하여 반도체소자의 미세 패턴을 형성함에 있어서, 반도체기판 상부에 희생 절연막을 증착하는 단계와, 희생 절연막 상부에 미세 패턴의 식각 마스크를 위한 감광막 패턴을 형성하는 단계와, 감광막 패턴의 양측면을 소정 부분 식각하여 그 선폭을 줄이는 단계와, 감광막 패턴을 식각 마스크로 삼아 희생 절연막을 식각해서 희생 절연막 패턴을 형성하고 상기 감광막 패턴을 제거하는 단계와, 결과물에 도전막을 증착하고 이를 식각해서 희생 절연막 패턴 측면에 스페이서 형태의 도전막 패턴을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method for forming a fine pattern of a semiconductor device using an exposure apparatus and an etching process, the method comprising: depositing a sacrificial insulating film on a semiconductor substrate, and forming an etching pattern of a fine pattern on the sacrificial insulating film. Forming a photoresist pattern, etching both sides of the photoresist pattern to a predetermined portion to reduce its line width, etching the sacrificial insulation layer using the photoresist pattern as an etch mask to form a sacrificial insulation pattern and removing the photoresist pattern; And depositing a conductive layer on the resultant and etching the conductive layer to form a spacer layer on the side of the sacrificial insulating layer pattern.
상기 도전막의 증착 두께는 형성하고자 하는 반도체소자의 도전막 패턴의 선폭이 되도록 조정하고, 희생 절연막의 증착 두께는 형성하고자 하는 반도체소자의 도전막 패턴의 높이가 되도록 조정하는 것이 바람직하다.The deposition thickness of the conductive film is preferably adjusted to be the line width of the conductive film pattern of the semiconductor device to be formed, and the deposition thickness of the sacrificial insulating film is adjusted to be the height of the conductive film pattern of the semiconductor device to be formed.
상기 도전막 패턴을 형성한 후에, 희생 절연막 패턴을 선택적으로 제거하는 단계를 추가 포함하는 것을 특징으로 한다.After the conductive film pattern is formed, the method may further include selectively removing the sacrificial insulating film pattern.
상기 다른 목적을 달성하기 위하여 본 발명은 노광장비 및 식각 공정을 이용하여 반도체소자의 미세 패턴을 형성함에 있어서, 반도체기판의 하지층 상부에 희생 절연막을 증착하는 단계와, 희생 절연막 상부에 미세 패턴의 식각 마스크를 위한 감광막 패턴을 형성하는 단계와, 감광막 패턴의 양측면을 소정 부분 식각하여 그 선폭을 줄이는 단계와, 감광막 패턴을 식각 마스크로 삼아 희생 절연막을 식각해서 희생 절연막 패턴을 형성하고 감광막 패턴을 제거하는 단계와, 상기 결과물에 희생 절연막과 식각 선택비가 다른 절연막을 증착하고 이를 식각해서 희생 절연막 패턴 측면에 절연막 식각 패턴을 형성하는 단계와, 희생 절연막 패턴을 제거한 후에 절연막 식각 패턴을 마스크로 삼아 하지층을 식각하는 단계를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above another object, the present invention provides a method for forming a fine pattern of a semiconductor device using an exposure apparatus and an etching process, the method comprising: depositing a sacrificial insulating film on an underlayer of a semiconductor substrate; Forming a photoresist pattern for an etch mask, etching a predetermined portion of both sides of the photoresist pattern to reduce its line width, and using the photoresist pattern as an etch mask to etch a sacrificial insulating film to form a sacrificial insulation pattern and to remove the photoresist pattern And depositing an insulating film having a different etching selectivity from the sacrificial insulating film on the resultant and etching the same to form an insulating film etching pattern on the side of the sacrificial insulating film pattern, and after removing the sacrificial insulating film pattern, using the insulating film etching pattern as a mask Characterized in that it comprises a step of etching .
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1f는 본 발명의 일실시예에 따른 반도체소자의 미세 게이트전극 패턴 제조방법을 설명하기 위한 공정 순서도로서, 이를 참조하면 본 발명의 일 실시예는 다음과 같다.1A to 1F are flowcharts illustrating a method of manufacturing a fine gate electrode pattern of a semiconductor device according to an embodiment of the present invention. Referring to this, an embodiment of the present invention is as follows.
우선, 도 1a에 도시된 바와 같이, 반도체기판(10) 상부에 희생 절연막(12)으로서, 산화막을 50∼500Å 두께 정도 증착하고, 그 위에 질화막을 1000∼4000Å정도 적층한다. 바람직하게는, 상기 희생 산화막이 200Å 정도, 희생 질화막은 2000Å 정도의 두께로 형성한다. 여기서, 상기 희생 절연막(12)의 증착 두께(h1)는 형성하고자 하는 반도체소자의 이후 형성될 도전막 패턴의 높이에 맞도록 조정한다.First, as shown in FIG. 1A, as a sacrificial insulating film 12 on the semiconductor substrate 10, an oxide film is deposited to a thickness of about 50 to 500 GPa, and a nitride film is deposited to about 1000 to 4000 GPa. Preferably, the sacrificial oxide film is formed to a thickness of about 200 kPa, and the sacrificial nitride film is about 2000 kPa. Here, the deposition thickness h1 of the sacrificial insulating layer 12 is adjusted to match the height of the conductive layer pattern to be formed later of the semiconductor device to be formed.
그리고, 상기 희생 절연막(12) 상부에 노광장비를 이용한 미세 패턴의 식각 마스크를 위한 감광막 패턴(14)을 형성한다. 여기서, 감광막 패턴(14)의 폭 수치는 일반적인 게이트전극 패터닝 공정의 일 예로서 본 실시예에서는 약 0.18㎛로 지정하고, 패턴(14) 간격도 약 0.18㎛로 한다. 또한, 이 감광막 패턴(14)의 치수 및그 간격은 노광 장비의 종류에 따라 달라 질 수 있으며 노광 공정에서 허용하는 최소 선폭으로도 할 수 있다.A photoresist pattern 14 is formed on the sacrificial insulating layer 12 for an etching mask having a fine pattern using exposure equipment. Here, the width value of the photosensitive film pattern 14 is set to about 0.18 μm in this embodiment as an example of a general gate electrode patterning process, and the interval of the pattern 14 is also about 0.18 μm. In addition, the dimension of the photosensitive film pattern 14 and its spacing may vary depending on the type of exposure equipment, and may also be the minimum line width allowed in the exposure process.
이어서, 도 1b에 도시된 바와 같이, 감광막 패턴(14)의 양측면을 소정 부분, 예컨대 0.09㎛정도 식각한다. 이로 인해, 식각된 감광막 패턴(14) 사이의 간격이 약 0.28㎛로 된다. 여기서, 식각 공정은 습식 또는 플라즈마를 이용한 공정을 진행하여 패터닝된 감광막의 선폭을 줄인다.(도면 부호 14'참조) 또한, 습식 공정은 허용 가능한 모든 용액을 사용할 수 있으며, 바람직하게는 현상액을 이용할 수 있다.Subsequently, as shown in FIG. 1B, both side surfaces of the photosensitive film pattern 14 are etched by a predetermined portion, for example, about 0.09 μm. For this reason, the space | interval between the etched photosensitive film patterns 14 becomes about 0.28 micrometer. Here, the etching process is a process using a wet or plasma to reduce the line width of the patterned photoresist (see reference numeral 14 '). In addition, the wet process may use any acceptable solution, preferably a developer may be used. have.
반면에, 플라즈마의 경우에는 감광막 패턴(14)의 양측면 부위를 줄일 수 있는 어떠한 플라즈마 가스라도 이용할 수 있으며 바람직하게는 산소 플라즈마를 사용하면 그 조절이 용이하다.On the other hand, in the case of plasma, any plasma gas capable of reducing both side portions of the photoresist pattern 14 may be used, and preferably, an oxygen plasma is used to easily control the plasma gas.
추가적으로, 감광막 패턴(14)의 양측면의 줄임을 위해서는, UV(Ultra Violet) 또는 오븐(oven)을 이용할 수도 있다.In addition, in order to reduce both sides of the photosensitive film pattern 14, UV (Ultra Violet) or an oven may be used.
그 다음, 도 1c에 도시된 바와 같이, 상기 양측면이 식각된 감광막 패턴(14')을 식각 마스크로 삼아 하부의 희생 절연막(12)을 건식 식각해서 희생 절연막 패턴(12')을 형성한다.Next, as shown in FIG. 1C, the sacrificial insulating layer pattern 12 ′ is formed by dry etching the lower sacrificial insulating layer 12 using the photoresist pattern 14 ′ with both side surfaces etched as an etching mask.
그 다음, 게이트 산화막(미도시함)을 소정 두께로 성장시킨 후에 도 1d에 도시된 바와 같이, 상기 결과물에 도전막으로서 도프트 폴리실리콘(16)을 증착한다. 여기서, 폴리실리콘(16)의 증착 두께(h1')는 이후 게이트전극의 선폭이 되므로 해당 게이트전극의 선폭에 맞추어 증착 두께를 조정하는 것이 바람직하다.Next, after the gate oxide film (not shown) is grown to a predetermined thickness, as shown in FIG. 1D, doped polysilicon 16 is deposited on the resultant as a conductive film. Here, since the deposition thickness h1 ′ of the polysilicon 16 becomes the line width of the gate electrode, it is preferable to adjust the deposition thickness according to the line width of the gate electrode.
이어서, 도 1e에 도시된 바와 같이, 상기 도포트 폴리실리콘(16)을 블랭킷 식각해서 상기 희생 절연막 패턴(12') 양측면에 스페이서 형태의 도전막 패턴(16')을 형성한다.Subsequently, as illustrated in FIG. 1E, the doped polysilicon 16 is blanket-etched to form a spacer-type conductive layer pattern 16 ′ on both sides of the sacrificial insulation layer pattern 12 ′.
계속해서, 도 1f에 도시된 바와 같이, 상기 결과물에 인산 용액을 이용한 습식 식각 공정을 진행하면 희생 절연막 패턴(12')이 제거되어 해상도가 2배로 높은 본 발명의 게이트전극용 미세 도전막 패턴(16')이 완성된다.Subsequently, as shown in FIG. 1F, when the wet etching process using the phosphoric acid solution is performed on the resultant, the sacrificial insulating layer pattern 12 ′ is removed to double the resolution of the fine conductive layer pattern for the gate electrode of the present invention ( 16 ') is complete.
한편, 본 발명의 미세 패턴 형성방법을 이용하면, 반도체소자의 게이트전극 형성뿐만 아니라 다른 반도체소자의 미세 패턴 형성에도 응용할 수 있다.On the other hand, if the fine pattern forming method of the present invention is used, it can be applied not only to the gate electrode formation of the semiconductor device but also to the fine pattern formation of other semiconductor devices.
도 2a 내지 도 2b는 본 발명의 다른 실시예에 따른 반도체소자의 금속 배선 패턴 제조방법을 설명하기 위한 공정 순서도이다.2A to 2B are flowcharts illustrating a method of manufacturing a metal wiring pattern of a semiconductor device according to another embodiment of the present invention.
이를 참조하면, 본 발명은 미세한 금속 배선의 패터닝 공정에 이용할 경우 도 2a에 도시된 바와 같이, 반도체기판의 하부 구조물(20) 상부에 배선 간격이 좁고 종횡비(aspect ratio)가 높은 금속 배선의 두께(h2)에 해당하는 희생 절연막 패턴(22)을 형성한다.Referring to this, in the present invention, when used in the patterning process of the fine metal wiring, as shown in FIG. 2A, the thickness of the metal wiring having a narrow wiring interval and a high aspect ratio on the lower structure 20 of the semiconductor substrate ( A sacrificial insulating film pattern 22 corresponding to h2) is formed.
이어서, 도 2b에 도시된 바와 같이, 도전막으로서 금속(24)을 증착한 후에 건식 식각 공정으로 금속(24)을 식각해서 상기 희생 절연막 패턴(22) 측면에 본 발명에 따른 스페이서 형태의 금속 패턴(24')을 형성한다. 이때, 식각 공정시 금속(24)의 증착 두께만큼 식각하면 되므로 식각 시간이 단축된다.Subsequently, as shown in FIG. 2B, after depositing the metal 24 as a conductive film, the metal 24 is etched by a dry etching process to form a spacer-shaped metal pattern on the side surface of the sacrificial insulating layer pattern 22. Forms a 24 '. In this case, the etching time may be reduced by etching the deposition thickness of the metal 24 during the etching process.
참고적으로, 상기와 같은 본 발명의 금속 배선 공정이 완료된 후에 상기 희생 절연막 패턴(22)을 그대로 남기고 층간 절연막 증착 공정을 진행할 수 있는데, 이때, 금속 패턴(24')의 한쪽 상부 모서리가 기울어져 있어 층간 절연물질의 증착 비율을 높여 매립 특성을 향상시킨다.For reference, after the metal wiring process of the present invention is completed, the interlayer insulation film deposition process may be performed while leaving the sacrificial insulation film pattern 22 as it is. At this time, one upper edge of the metal pattern 24 ′ is inclined. This increases the deposition rate of the interlayer insulating material to improve the landfill characteristics.
또한, 본 발명은 도면에 도시되지 않았지만, 상술한 금속 패턴 공정시 상부 모서리 부분이 기울어진 점을 보완하면서 그 해상도를 높이기 위하여 다음과 같은 제조 공정을 수행한다.In addition, although the present invention is not shown in the drawings, the following manufacturing process is performed to increase the resolution while compensating for the inclination of the upper edge portion during the metal pattern process described above.
우선, 상술한 실시예와 동일하게 반도체기판의 하지층 상부에 노광 장비 및 식각 공정을 이용한 희생 절연막 패턴을 형성한다. 이어서, 상기 결과물에 희생 절연막과 식각 선택비가 다른 절연막을 증착하고 이를 식각해서 희생 절연막 패턴 측면에 절연막 식각 패턴을 형성한다. 이때, 절연막의 식각 공정은 건식 또는 습식 식각 공정을 이용하지만 바람직하게는 BOE를 사용한다. 그 다음, 희생 절연막 패턴을 제거한 후에 절연막 식각 패턴을 마스크로 삼아 하지층, 예컨대 도프트 폴리실리콘막 또는 금속막을 식각하여 원하는 반도체소자의 미세 패턴을 형성한다.First, a sacrificial insulating layer pattern using an exposure apparatus and an etching process is formed on the underlayer of the semiconductor substrate in the same manner as in the above-described embodiment. Subsequently, an insulating film having an etch selectivity different from that of the sacrificial insulating film is deposited on the resultant and etched to form an insulating film etching pattern on the side of the sacrificial insulating film pattern. At this time, the etching process of the insulating film uses a dry or wet etching process, but preferably BOE. Subsequently, after removing the sacrificial insulating film pattern, the insulating layer etching pattern is used as a mask to etch a base layer such as a doped polysilicon film or a metal film to form a fine pattern of a desired semiconductor device.
상기한 바와 같이 본 발명은, 현재 노광 공정상 한계가 되고 있는 0.15㎛이하의 선폭 설계 규칙을 가지는 반도체소자의 패터닝 공정이 용이해진다.As described above, the present invention facilitates a patterning process of a semiconductor device having a line width design rule of 0.15 탆 or less, which is currently a limitation in the exposure process.
그리고, 본 발명은 종래의 반도체소자의 패턴 공정에 비하여 소자의 선폭만을 줄이는 효과보다는 패턴의 해상도를 증가시키기 때문에 소자의 집적도를 비약적으로 증가시킬 수 있다. 예를 들어, 최근 반도체소자에 적용되는 노광 장비 중 비교적 가격이 싼 i-라인 스텝퍼를 이용해 0.35㎛로 감광막을 패터닝한 경우, 쉽게 0.18㎛의 설계 규칙으로 해상도를 증가시킬 수 있어서 비교적 고가인 DUV 노광장비를 사용할 필요가 없으므로 생산 원가를 낮출 수 있다.In addition, the present invention increases the resolution of the pattern rather than the effect of reducing only the line width of the device, compared to the conventional patterning process of the semiconductor device can significantly increase the integration degree of the device. For example, when a photosensitive film is patterned to 0.35 μm using a relatively inexpensive i-line stepper among exposure apparatuses applied to a semiconductor device, a relatively expensive DUV exposure can be easily increased by a design rule of 0.18 μm. There is no need to use equipment, which reduces production costs.
또한, 본 발명은 게이트전극 패턴 공정에 이용할 경우 폴리실리콘의 증착 두께에 따라 게이트 선폭의 조절이 쉬어져 0.01㎛이하의 선폭을 가지는 게이트전극을 제작할 수 있다.In addition, in the present invention, when the gate electrode pattern process is used, the gate line width is easily adjusted according to the deposition thickness of the polysilicon, thereby manufacturing a gate electrode having a line width of 0.01 μm or less.
또한, 본 발명은 금속 배선 공정에 응용할 경우, 스페이서 형태로 금속 배선 패턴을 형성할 수 있으며 배선 사이의 절연막을 이미 형성하고 있기 때문에 식각 잔유물에 의한 누설 전류의 발생을 줄일 수 있으며 층간 절연막의 증착을 용이하게 하는 이점이 있다.In addition, when applied to the metal wiring process, the present invention can form a metal wiring pattern in the form of a spacer, and since the insulating film between the wirings is already formed, it is possible to reduce the occurrence of leakage current due to the etching residue and to prevent the deposition of the interlayer insulating film. There is an advantage to facilitate.
한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주내에서 당업자에 의해 여러 가지 변형이 가능하다.On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.
Claims (5)
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| KR1019990032423A KR100310257B1 (en) | 1999-08-07 | 1999-08-07 | Method of forming minute pattern in semiconductor device |
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| KR1019990032423A KR100310257B1 (en) | 1999-08-07 | 1999-08-07 | Method of forming minute pattern in semiconductor device |
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Cited By (4)
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| KR100476924B1 (en) * | 2002-06-14 | 2005-03-17 | 삼성전자주식회사 | Method Of Forming Fine Pattern Of Semiconductor Device |
| WO2010014380A2 (en) * | 2008-07-11 | 2010-02-04 | Applied Materials, Inc. | Within-sequence metrology based process tuning for adaptive self-aligned double patterning |
| WO2010129137A2 (en) * | 2009-05-06 | 2010-11-11 | Micron Technology, Inc. | Methods of forming a plurality of conductive lines in the fabrication of integrated circuitry, methods of forming an array of conductive lines, and integrated circuitry |
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| KR100642886B1 (en) * | 2005-06-27 | 2006-11-03 | 주식회사 하이닉스반도체 | Method of forming a micro pattern in a semiconductor device |
| US7575992B2 (en) | 2005-09-14 | 2009-08-18 | Hynix Semiconductor Inc. | Method of forming micro patterns in semiconductor devices |
| KR100650859B1 (en) * | 2005-11-09 | 2006-11-27 | 주식회사 하이닉스반도체 | Method of forming a micro pattern in a semiconductor device |
| KR100842753B1 (en) * | 2007-06-29 | 2008-07-01 | 주식회사 하이닉스반도체 | Method of fabricting pattern in semiconductor device using spacer |
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| KR100476924B1 (en) * | 2002-06-14 | 2005-03-17 | 삼성전자주식회사 | Method Of Forming Fine Pattern Of Semiconductor Device |
| WO2010014380A2 (en) * | 2008-07-11 | 2010-02-04 | Applied Materials, Inc. | Within-sequence metrology based process tuning for adaptive self-aligned double patterning |
| WO2010014380A3 (en) * | 2008-07-11 | 2010-05-14 | Applied Materials, Inc. | Within-sequence metrology based process tuning for adaptive self-aligned double patterning |
| US8232212B2 (en) | 2008-07-11 | 2012-07-31 | Applied Materials, Inc. | Within-sequence metrology based process tuning for adaptive self-aligned double patterning |
| KR101413661B1 (en) * | 2008-07-11 | 2014-07-01 | 어플라이드 머티어리얼스, 인코포레이티드 | Within-sequence metrology based process tuning for adaptive self-aligned double patterning |
| WO2010129137A2 (en) * | 2009-05-06 | 2010-11-11 | Micron Technology, Inc. | Methods of forming a plurality of conductive lines in the fabrication of integrated circuitry, methods of forming an array of conductive lines, and integrated circuitry |
| WO2010129137A3 (en) * | 2009-05-06 | 2011-01-13 | Micron Technology, Inc. | Methods of forming a plurality of conductive lines in the fabrication of integrated circuitry, methods of forming an array of conductive lines, and integrated circuitry |
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| CN102422411A (en) * | 2009-05-06 | 2012-04-18 | 美光科技公司 | Methods of forming a plurality of conductive lines in the fabrication of integrated circuitry, methods of forming an array of conductive lines, and integrated circuitry |
| US9064935B2 (en) | 2009-05-06 | 2015-06-23 | Micron Technology, Inc. | Methods of forming a plurality of conductive lines in the fabrication of integrated circuitry, methods of forming an array of conductive lines, and integrated circuitry |
| CN112885898A (en) * | 2019-11-29 | 2021-06-01 | 吴俊鹏 | Semiconductor device with reduced line width and method for manufacturing semiconductor device |
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