KR20070021506A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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KR20070021506A
KR20070021506A KR1020050075800A KR20050075800A KR20070021506A KR 20070021506 A KR20070021506 A KR 20070021506A KR 1020050075800 A KR1020050075800 A KR 1020050075800A KR 20050075800 A KR20050075800 A KR 20050075800A KR 20070021506 A KR20070021506 A KR 20070021506A
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film
contact hole
etching
sccm
sod
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KR1020050075800A
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Korean (ko)
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박현식
한기현
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주식회사 하이닉스반도체
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Priority to KR1020050075800A priority Critical patent/KR20070021506A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 제조방법을 개시한다. 개시된 본 발명의 방법은, 하부구조물을 구비한 반도체기판 상에 층간절연막으로서 SOD막을 형성하는 단계와, 상기 SOD막 상에 콘택홀을 정의하는 감광막패턴을 형성하는 단계와, 상기 감광막패턴을 식각장벽으로 이용하고 식각가스로서 C4F8과 CH2F2를 각각 15∼22sccm과 5∼10sccm을 플로우시키는 공정 조건으로 상기 SOD막을 식각하여 하부구조물을 노출시키는 콘택홀을 형성하는 단계를 포함한다. The present invention discloses a method for manufacturing a semiconductor device. The disclosed method includes forming a SOD film as an interlayer insulating film on a semiconductor substrate having a substructure, forming a photoresist pattern defining a contact hole on the SOD film, and etching the photoresist pattern on an etch barrier. And forming a contact hole exposing the lower structure by etching the SOD film under process conditions in which C 4 F 8 and CH 2 F 2 are flowed from 15 to 22 sccm and 5 to 10 sccm, respectively, as an etching gas.

Description

반도체 소자의 제조방법{METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}

도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도. 1A to 1D are cross-sectional views illustrating processes for manufacturing a semiconductor device according to the related art.

도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도.2A to 2C are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

200 : 반도체기판 205 : 하부구조물200: semiconductor substrate 205: substructure

210 : SOD막 220 : 감광막 210: SOD film 220: photosensitive film

220a : 감광막패턴 230 : 콘택홀220a: photoresist pattern 230: contact hole

P : 폴리머P: polymer

본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 콘택홀 형성시 FICD 변동폭 증가 문제를 개선하여 보다 균일한 미세 콘택홀을 구현할 수 있는 반도체 소자의 제조방법에 관한 것이다. The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device that can implement a more uniform fine contact hole by improving the problem of increasing the FICD fluctuation range when forming a contact hole.

반도체 소자의 고집적화가 진행됨에 따라 하부구조물과 상부구조물 간의 전 기적 연결 통로를 제공하는 콘택홀의 폭은 감소하고 있고, 그 깊이는 깊어지고 있는 추세이다. As the integration of semiconductor devices increases, the width of contact holes providing electrical connection paths between the lower and upper structures is decreasing, and the depth of the semiconductor devices is increasing.

이에 따라, 보다 미세한 패턴을 구현할 수 있는 고해상도의 노광장비가 요구되고 있으며, 실제로 반도체 공정에서의 노광장비는 그 광원으로 G-line(λ=436nm) 및 I-line(λ=365nm)을 사용하는 장비에서 KrF(λ=248nm) 및 ArF(λ=193nm)를 사용하는 장비로 바뀌어가고 있다. 또한, 고집적화가 더욱 가속화됨에 따라 차후에는 상기 ArF 보다 더욱 짧은 파장을 갖는 광원을 적용한 노광장비가 필요시되고, 그에 대한 연구가 진행되고 있다. Accordingly, a high resolution exposure apparatus capable of realizing a finer pattern is required, and in fact, an exposure apparatus in a semiconductor process uses G-line (λ = 436 nm) and I-line (λ = 365 nm) as its light source. It is shifting from equipment to equipment using KrF (λ = 248 nm) and ArF (λ = 193 nm). In addition, as high integration is further accelerated, there is a need for an exposure apparatus using a light source having a shorter wavelength than that of ArF.

그러나, 상기 노광장비의 고급화는 상당한 설비 투자 비용이 요구된다. 또한, 상기 ArF 보다 짧은 파장을 갖는 차세대 광원인 F2, Ar2 및 EUV(Extreme Ultra Violet) 등은 현재로서는 상용화하기 어려운 기술적인 문제점을 갖고 있다. However, the high quality of the exposure equipment requires a significant investment in equipment. In addition, F2, Ar2 and EUV (extreme ultra violet), which are next-generation light sources having a wavelength shorter than that of ArF, have technical problems that are difficult to commercialize at present.

이러한 상황에서, 상기 콘택홀과 같은 홀(hole) 타입의 패턴 구현은 워드라인(word line) 및 비트라인(bit line) 등과 같은 직선 타입의 패턴 구현에 비해 보다 정밀한 패턴 구현 기술이 요구되므로 그 패턴을 구현하는데 상대적인 어려움을 겪고 있다. In this situation, the hole type pattern implementation such as the contact hole requires a more precise pattern implementation technique than the linear type implementation such as word lines and bit lines. Are experiencing relative difficulties in implementing

그러므로, 상기 노광장비의 고급화 뿐만 아니라, 그 밖의 다른 방법을 이용하여 미세 콘택홀을 구현하려는 다각적인 연구가 진행되고 있으며, 그와 관련된 기술들이 제안되고 있다. Therefore, various studies have been conducted to implement the fine contact hole using other methods as well as the advancement of the exposure apparatus, and related technologies have been proposed.

일례로, 100nm 이하의 미세 콘택홀을 구현하기 위한 공정 기술로서 RRP(Resist Reflow Process) 기술이 제안되었다. 상기 RRP 기술은 노광장비 해상도 의 한계 문제를 리플로우(reflow) 공정으로 극복하여 미세 패턴을 구현하는 기술이다. As an example, a resist reflow process (RPP) technology has been proposed as a process technology for realizing a fine contact hole of 100 nm or less. The RRP technology is a technology that implements a fine pattern by overcoming the limitation problem of the resolution of an exposure apparatus with a reflow process.

이하에서는, 도 1a 내지 도 1d를 참조하여, 상기 RRP 기술을 포함하는 종래의 콘택홀 형성 기술을 보다 자세하게 설명하도록 한다. Hereinafter, a conventional contact hole forming technique including the RRP technique will be described in more detail with reference to FIGS. 1A to 1D.

도 1a를 참조하면, 소정의 하부구조물(105)이 형성된 반도체기판(100) 상에 층간절연막(110)을 형성하고, 계속해서, 상기 층간절연막(110) 상에 감광막(120)을 증착한다. 여기서, 상기 층간절연막(110)으로는 통상 BPSG(Boro-phospho Silicate Glass)막을 사용한다. Referring to FIG. 1A, an interlayer insulating film 110 is formed on a semiconductor substrate 100 on which a predetermined substructure 105 is formed, and then a photoresist film 120 is deposited on the interlayer insulating film 110. In this case, a BPSG (Boro-phospho Silicate Glass) film is generally used as the interlayer insulating film 110.

도 1b를 참조하면, 상기 감광막을 노광장비와 마스크패턴를 이용하여 노광한 후, 상기 노광된 감광막을 현상(develop)하여 소망하는 콘택홀 크기 보다 큰 폭을 갖는 홀(H1)을 정의하는 제1감광막패턴(120a)을 형성한다. Referring to FIG. 1B, after exposing the photoresist film using an exposure apparatus and a mask pattern, the exposed photoresist film is developed to define a first photoresist film that defines a hole H1 having a width larger than a desired contact hole size. The pattern 120a is formed.

도 1c를 참조하면, 상기 제1감광막패턴을 Tg(Glass Transition Temperature) 이상의 온도로 가열하여 플로우 시켜, 상기 정의된 홀의 크기를 축소시켜 최종적으로 소망하는 콘택홀 크기 정도의 홀(H2)을 갖는 제2감광막패턴(120b)을 형성한다.Referring to FIG. 1C, the first photoresist pattern may be heated to a temperature of at least Tg (Glass Transition Temperature) to flow to reduce the size of the defined hole and finally have a hole H2 having a desired contact hole size. The second photosensitive film pattern 120b is formed.

도 1d를 참조하면, 상기 제2감광막패턴(120b)을 식각장벽으로 이용해서, 노출된 층간절연막(110) 부분을 식각하여 하부구조물(105)을 노출시키는 콘택홀(130)을 형성한다. Referring to FIG. 1D, using the second photoresist layer pattern 120b as an etch barrier, a portion of the exposed interlayer insulating layer 110 is etched to form a contact hole 130 exposing the lower structure 105.

이후, 도시하지는 않았으나, 상기 제2감광막패턴(120b)을 제거하고, 그리고나서, 식각공정시 발생하여 콘택홀(130) 내에 잔류된 부가물들을 세척하는 세정 공정을 수행한다. Subsequently, although not illustrated, the second photoresist layer pattern 120b is removed, and then a cleaning process is performed to clean the adducts generated during the etching process and remaining in the contact hole 130.

그러나, 전술한 종래 기술에서는 리플로우(reflow) 공정시, 도 1c의 A영역과 같이, 제2감광막패턴(120b)의 높이 방향으로의 중앙부가 볼록해지는 현상이 발생하고, 아울러, 기판의 위치 별로 제2감광막패턴(120b) 모양이 불균일해지는 현상이 발생하며, 이로 인해, 상기 층간절연막(110) 내에 형성되는 콘택홀들의 크기도 불균일하게 된다. 다시말해, 콘택홀의 최종 크기를 지칭하는 FICD(Final Inspection Critical Dimension)의 변동폭이 커지는 문제가 유발된다.However, in the above-described prior art, in the reflow process, as shown in area A of FIG. 1C, a phenomenon in which the central portion of the second photoresist pattern 120b is raised in the height direction occurs, and the position of the substrate is also increased. A phenomenon in which the shape of the second photoresist layer pattern 120b is uneven occurs, and thus, the size of the contact holes formed in the interlayer insulating layer 110 is also uneven. In other words, a problem arises in that the variation of Final Inspection Critical Dimension (FICD), which refers to the final size of the contact hole, increases.

따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위하여 안출된 것으로서, 하부구조물과 상부구조물 간의 전기적 연결 통로를 제공하는 콘택홀 형성시 종래 RRP 공정 기술의 취약점인 FICD(Final Inspection Critical Dimension) 변동폭 증가 문제를 개선하여 보다 균일한 미세 콘택홀을 구현할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다. Accordingly, the present invention has been made to solve the above-mentioned conventional problems, the width of the Final Inspection Critical Dimension (FICD) which is a weak point of the conventional RRP process technology when forming a contact hole providing an electrical connection passage between the lower structure and the upper structure It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of realizing a more uniform fine contact hole by improving an increase problem.

상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법, 하부구조물을 구비한 반도체기판 상에 층간절연막으로서 SOD막을 형성하는 단계; 상기 SOD막 상에 콘택홀을 정의하는 감광막패턴을 형성하는 단계; 및 상기 감광막패턴을 식각장벽으로 이용하고 식각가스로서 C4F8과 CH2F2를 각각 15∼22sccm과 5∼10sccm을 플로우시키는 공정 조건으로 상기 SOD막을 식각하여 하부구조물을 노출시키는 콘택홀을 형성하는 단계;를 포함한다. Method of manufacturing a semiconductor device of the present invention for achieving the above object, forming a SOD film as an interlayer insulating film on a semiconductor substrate having a lower structure; Forming a photoresist pattern defining a contact hole on the SOD layer; And forming a contact hole exposing an underlying structure by etching the SOD film under process conditions in which the photoresist pattern is used as an etch barrier and C4F8 and CH2F2 are flowed from 15 to 22 sccm and 5 to 10 sccm, respectively, as an etching gas. do.

여기서, 상기 식각가스는 Ar 가스를 더 포함하며, 이때, 상기 Ar 가스는 400 ∼800sccm 플로우시킨다. Here, the etching gas further includes an Ar gas, in which the Ar gas flows from 400 to 800 sccm.

상기 SOD막 식각은 15∼30mT 압력에서 1300∼1500W의 전력을 사용하여 수행한다. The SOD film etching is performed using a power of 1300 ~ 1500W at 15 ~ 30mT pressure.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도이다. 2A through 2C are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

도 2a를 참조하면, 소정의 하부구조물(205)이 형성된 반도체기판(200)을 마련한다. 그런 다음, 상기 기판(200) 상에 용매(solvent)로 용해되어 유동성을 갖는 절연물질을 스핀(spin) 방식으로 증착한 후, 상기 증착된 절연물질을 750℃ 이하의 온도로 열처리하여 치밀한 구조의 SOD(Spin on Dielectric)막(210)을 형성한다. 그 다음, 상기 SOD막(210) 상에 감광막(220)을 도포한다. Referring to FIG. 2A, a semiconductor substrate 200 on which a predetermined substructure 205 is formed is prepared. Then, after depositing an insulating material having a fluidity by dissolving in a solvent (svent) on the substrate 200 in a spin (spin) method, the deposited insulating material is heat-treated to a temperature of 750 ℃ or less to have a dense structure A SOD (Spin on Dielectric) film 210 is formed. Next, a photosensitive film 220 is coated on the SOD film 210.

그리고, 도시하지는 않았지만, 상기 SOD막(210)과 감광막 사이에는 감광막의 패터닝 특성을 향상시키기 위해 반사방지막(미도시)을 형성함이 바람직하다.Although not shown, an antireflection film (not shown) may be formed between the SOD film 210 and the photoresist film to improve patterning characteristics of the photoresist film.

도 2b를 참조하면, 감광막을 노광장비와 마스크패턴를 이용하여 노광한 후, 상기 노광된 감광막을 현상하여 감광막패턴(220a)을 형성한다. 여기서, 상기 감광막패턴(220a)이 갖는 홀 타입의 패턴 크기는 도 1b에서의 H1의 크기와 동일하며, 패턴 형성을 위해 사용하는 노광장비의 해상도 한계로 인해 형성하고자 하는 콘택홀의 크기 보다 큰 폭을 갖도록 형성될 수 있다. 그리고, 상기 감광막패턴(220a)의 홀 타입의 패턴 크기는 감광막(220) 현상(develop) 후의 패턴 크기로서 DICD(Deveplop Inspection Critical Dimension)라 한다. Referring to FIG. 2B, after exposing the photoresist using an exposure apparatus and a mask pattern, the exposed photoresist is developed to form a photoresist pattern 220a. Here, the size of the hole type pattern of the photoresist pattern 220a is the same as the size of H1 in FIG. 1B and is larger than the size of the contact hole to be formed due to the resolution limitation of the exposure apparatus used for forming the pattern. It can be formed to have. The pattern size of the hole type of the photoresist pattern 220a is a pattern size after development of the photoresist 220 and is referred to as a development inspection critical dimension (DICD).

도 2c를 참조하면, 상기 감광막패턴(220a)을 식각장벽으로 이용하면서, C4F8, CH2F2 및 Ar 가스를 포함하는 식각가스를 플로우시켜 상기 SOD막(210)을 식각하고, 이를 통해, 하부구조물(205)을 노출시키는 콘택홀(230)을 형성한다. Referring to FIG. 2C, while using the photoresist pattern 220a as an etch barrier, an etching gas including C 4 F 8, CH 2 F 2, and Ar gas is flowed to etch the SOD film 210, and thereby, the lower structure 205. ) To form a contact hole 230 exposing).

여기서, 상기 C4F8 가스는 15∼22sccm을 플로우시키고, 상기 CH2F2 가스는 5∼10sccm을 플로우시키며, 상기 Ar 가스는 400∼800sccm을 플로우시킨다. 이때, 상기 C4F8 가스는 그 플로우양이 15sccm 이상이기 때문에 상기 SOD막(210)과 좋은 반응성을 나타낸다. Here, the C4F8 gas flows 15 to 22 sccm, the CH2F2 gas flows 5 to 10 sccm, and the Ar gas flows 400 to 800 sccm. At this time, the C4F8 gas exhibits good reactivity with the SOD film 210 because the flow amount thereof is 15 sccm or more.

한편, 상기 SOD막(210) 식각은 식각시 발생하는 부산물들이 잘 배출될 수 있도록 비교적 낮은 압력인 15∼30mT 압력에서 수행하며, 이때, 사용하는 전력의 범위는 1300∼1500W로 한다. On the other hand, the etching of the SOD film 210 is performed at a pressure of 15-30mT, which is a relatively low pressure so that by-products generated during etching can be well discharged, at this time, the range of power used is 1300-1500W.

이와 같이, 본 발명은 층간절연막으로서 종래의 BPSG 대신에 SOD막을 사용하고, 또한 상기 SOD막을 C4F8(플로우양 : 15sccm 이상)과 CH2F2(플로우양 : 5sccm 이상)를 포함하는 식각가스를 이용해서 식각한다. 이 경우, 상기 SOD막(210) 식각 과정에서 다량의 폴리머(P)가 발생하여 감광막패턴(220)의 홀 내부 측벽에 쌓이기 때문에, 상기 감광막패턴(220)의 DICD 보다 작은 크기의 콘택홀(230)을 형성할 수 있다. 즉, 종래의 리플로우(reflow) 공정 없이도 DICD 보다 작은 폭을 갖는 미세 콘택홀들을 구현할 수 있다. As described above, the present invention uses an SOD film instead of the conventional BPSG as an interlayer insulating film, and etching the SOD film using an etching gas containing C4F8 (flow amount: 15 sccm or more) and CH2F2 (flow amount: 5 sccm or more). . In this case, a large amount of polymer (P) is generated during the etching process of the SOD film 210 and stacked on the inner sidewall of the hole of the photoresist pattern 220, so that the contact hole 230 having a smaller size than the DICD of the photoresist pattern 220 is formed. ) Can be formed. That is, fine contact holes having a width smaller than that of the DICD can be implemented without a conventional reflow process.

그러므로, 본 발명은 리플로우(reflow) 공정시 유발되는 감광막패턴(120b)의 프로파일(profile) 변형(도 1c의 A영역 참조)으로 인한 FICD 변동폭 증가 문제가 발생하지 않아 종래에 비해 콘택홀 패턴의 균일성을 향상시킬 수 있다. 또한, 본 발명은 감광막의 리플로우(reflow) 공정을 수행하지 않으므로 종래에 비해 공정을 단순화시킬 수 있다. Therefore, the present invention does not cause an increase in the FICD fluctuation due to the profile deformation of the photoresist pattern 120b (refer to region A of FIG. 1C) caused during the reflow process. Uniformity can be improved. In addition, since the present invention does not perform a reflow process of the photosensitive film, the process can be simplified.

이후, 도시하지는 않았으나, 상기 감광막패턴(220a) 및 폴리머(P)를 제거하고, 아울러, 식각공정시 발생하여 콘택홀(230) 내에 잔류된 부가물들을 세척하는 세정 공정을 수행한다.Subsequently, although not shown, a cleaning process is performed to remove the photoresist pattern 220a and the polymer P, and to clean the adducts generated during the etching process and remaining in the contact hole 230.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

이상에서와 같이, 본 발명은 층간절연막으로서 SOD막을 사용하고, 상기 SOD막의 식각시 다량이 폴리머가 발생되도록 식각조건을 맞춰줌으로써, 종래의 리플로우(reflow) 공정을 수행하지 않고도 DICD 보다 작은 폭을 갖는 미세 콘택홀들을 형성할 수 있다. As described above, the present invention uses an SOD film as an interlayer insulating film, and adjusts etching conditions such that a large amount of polymer is generated when the SOD film is etched, thereby reducing a width smaller than that of the DICD without performing a conventional reflow process. Fine contact holes may be formed.

그러므로, 본 발명은 리플로우(reflow) 공정을 생략할 수 있는 바, 상기 리플로우(reflow) 공정시 유발되는 감광막패턴의 프로파일(profile) 변형으로 인한 FICD 변동폭 증가 문제가 발생하지 않고, 따라서, 콘택홀 패턴의 균일성을 향상시킬 수 있다. 또한, 본 발명은 감광막의 리플로우(reflow) 공정을 수행하지 않으므 로 종래에 비해 공정을 단순화시킬 수 있다.Therefore, since the present invention can omit the reflow process, the problem of increasing the FICD fluctuation due to the profile deformation of the photoresist pattern caused during the reflow process does not occur. The uniformity of the hole pattern can be improved. In addition, since the present invention does not perform a reflow process of the photoresist film, the process can be simplified.

Claims (4)

하부구조물을 구비한 반도체기판 상에 층간절연막으로서 SOD막을 형성하는 단계; Forming an SOD film as an interlayer insulating film on a semiconductor substrate having a lower structure; 상기 SOD막 상에 콘택홀을 정의하는 감광막패턴을 형성하는 단계; 및Forming a photoresist pattern defining a contact hole on the SOD layer; And 상기 감광막패턴을 식각장벽으로 이용하고 식각가스로서 C4F8과 CH2F2를 각각 15∼22sccm과 5∼10sccm을 플로우시키는 공정 조건으로 상기 SOD막을 식각하여 하부구조물을 노출시키는 콘택홀을 형성하는 단계;를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법. Forming a contact hole exposing an underlying structure by etching the SOD layer under process conditions in which the photoresist pattern is used as an etch barrier and C4F8 and CH2F2 are flowed from 15 to 22 sccm and 5 to 10 sccm, respectively, as an etching gas; Method for manufacturing a semiconductor device, characterized in that. 제 1 항에 있어서, 상기 식각가스는 Ar 가스를 더 포함하는 것을 특징으로 하는 것을 특징으로 하는 반도체 소자의 제조방법. The method of claim 1, wherein the etching gas further comprises Ar gas. 제 2 항에 있어서, 상기 Ar 가스는 400∼800sccm 플로우시키는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 2, wherein the Ar gas flows between 400 and 800 sccm. 제 1 항에 있어서, 상기 SOD막 식각은 15∼30mT 압력에서 1300∼1500W의 전력을 사용하여 수행하는 것을 특징으로 하는 반도체 소자의 제조방법. The method of claim 1, wherein the SOD film is etched using a power of 1300-1500 W at a pressure of 15-30 mT.
KR1020050075800A 2005-08-18 2005-08-18 Method of manufacturing semiconductor device KR20070021506A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100791213B1 (en) * 2006-12-21 2008-01-04 동부일렉트로닉스 주식회사 Forming method of narrow space pattern using anti-reflective coating

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100791213B1 (en) * 2006-12-21 2008-01-04 동부일렉트로닉스 주식회사 Forming method of narrow space pattern using anti-reflective coating

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