KR100301096B1 - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
KR100301096B1
KR100301096B1 KR1019990022935A KR19990022935A KR100301096B1 KR 100301096 B1 KR100301096 B1 KR 100301096B1 KR 1019990022935 A KR1019990022935 A KR 1019990022935A KR 19990022935 A KR19990022935 A KR 19990022935A KR 100301096 B1 KR100301096 B1 KR 100301096B1
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South Korea
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adhesive
conductive contact
conductive
pad
film layer
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KR1019990022935A
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Korean (ko)
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KR20010002885A (en
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밍-퉁 센
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밍-퉁 센
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/184—Components including terminals inserted in holes through the printed circuit board and connected to printed contacts on the walls of the holes or at the edges thereof or protruding over or into the holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/8349—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

반도체 디바이스(4)는 반도체 칩(40)과 유전막층(5) 및 인쇄회로기판(6)을 포함한다. 반도체 칩(40)은 상부에 복수의 접착 패드(41)가 제공된 패드 장착면(42)을 갖는다. 유전막층(5)은 서로 대향하는 제1 및 제2 접착면(50, 51)을 갖는다. 제1 접착면(50)은 제1 반도체칩(40)의 패드장착면(42)에 접착된다. 유전막층(5)에는 접착패드(41)와 일치하는 위치에 홀(52)이 형성되어 있어, 상기 접착 패드(41)를 노출시킨다. 각 홀(52)은 벽(53)에 의해 한정되며, 이 벽(53)은 접착패드(41)중 일치된 패드와 함께 접촉수납공간을 형성한다. 도전접촉부(54, 54', 54')가 각각 접촉수납공간에 놓인다. 인쇄회로기판(6)은 유전막층(5)의 제2접착면(51)상에 접착되는 회로 레이아웃면(61)을 갖는다. 회로 레이아웃면(61)에는 도전접촉부(54, 54', 54')에 접착되는 회로선(circuit trace)(61)이 제공되어있어, 상기 접착패드(41)와 전기적인 접속을 설정해준다. 이와같은 반도체 디바이스(4)를 제조하는 방법 또한 기술되어 있다.The semiconductor device 4 includes a semiconductor chip 40, a dielectric film layer 5, and a printed circuit board 6. The semiconductor chip 40 has a pad mounting surface 42 provided with a plurality of adhesive pads 41 thereon. The dielectric film layer 5 has first and second adhesive surfaces 50 and 51 facing each other. The first adhesive surface 50 is adhered to the pad mounting surface 42 of the first semiconductor chip 40. In the dielectric layer 5, holes 52 are formed at positions corresponding to the adhesive pads 41, thereby exposing the adhesive pads 41. Each hole 52 is defined by a wall 53, which forms a contact storage space with the matched pads in the adhesive pad 41. The conductive contacts 54, 54 ', 54' are placed in the contact storage spaces, respectively. The printed circuit board 6 has a circuit layout surface 61 bonded onto the second bonding surface 51 of the dielectric film layer 5. The circuit layout surface 61 is provided with a circuit trace 61 bonded to the conductive contact portions 54, 54 ′, 54 ′ to establish electrical connection with the adhesive pad 41. A method of manufacturing such a semiconductor device 4 is also described.

Description

반도체 디바이스 및 그 제조방법{SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME}Semiconductor device and its manufacturing method {SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME}

본 발명은 반도체 디바이스 및 그 제조방법에 관한 것으로, 보다 특별하게는 비교적 저비용이면서 높은 생산양품율로 생산될 수 있는 반도체 디바이스 및 그 제조방법에 관한 것이다.The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device and a method of manufacturing the same that can be produced at a relatively low cost and high production yield.

도1 및 도2는 종래의 반도체디바이스(1)를 보인 것으로 반도체칩(10), 유전막층(2) 및 인쇄회로기판(3)을 구비한다.1 and 2 show a conventional semiconductor device 1, which includes a semiconductor chip 10, a dielectric film layer 2, and a printed circuit board 3. As shown in FIG.

반도체칩(10)은 그 위에 복수의 접착패드(11)가 제공된 패드장착면(12)을 가지고 있다. 유전막층(2)은 반도체칩(10)의 패드장착면(12)에 접착되는 접착면(12)과 그리고 접착패드(11)와 일치되어 이 패드를 노출시키는 복수의 홀(20)이 형성되어 있다. 상기 유전막층(2)은 또한 접착면(21)과 대향하는 와이어장착면(22)을 갖는다. 홀(20)을 횡단하는 복수의 와이어(23)가 와이어장착면(22)에 배치된다. 와이어-접착 머신(도시않됨)이 홀(20)에서 와이어(23)가 접착패드(11)에 접착되도록 (도1에서 보인 화살표 방향으로) 홀(20)을 횡단하는 와이어(23)부분을 처리한다. 이어서, 납땜볼(24)이 와이어(23)에 형성된다. 인쇄회로기판(3)에는 납땜볼(24)과 접착되는 회로선(31)이 형성되어있어, 납땜볼(24)과 와이어(23)를 통해 회로선(31)과 접착패드(11)사이에 전기적인 접속이 설정된다.The semiconductor chip 10 has a pad mounting surface 12 provided with a plurality of adhesive pads 11 thereon. The dielectric layer 2 has an adhesive surface 12 adhered to the pad mounting surface 12 of the semiconductor chip 10, and a plurality of holes 20 coincident with the adhesive pad 11 to expose the pad. have. The dielectric film layer 2 also has a wire mounting surface 22 opposite the adhesive surface 21. A plurality of wires 23 traversing the hole 20 are disposed on the wire mounting surface 22. A wire-bonding machine (not shown) processes the portion of the wire 23 that traverses the hole 20 (in the direction of the arrow shown in FIG. 1) so that the wire 23 is bonded to the adhesive pad 11 at the hole 20. do. Subsequently, a solder ball 24 is formed on the wire 23. The printed circuit board 3 has a circuit line 31 bonded to the solder ball 24, and is formed between the circuit line 31 and the adhesive pad 11 through the solder ball 24 and the wire 23. The electrical connection is established.

그러나, 이와같은 종래의 반도체디바이스(1)는 다음과 같은 일부 결점을 가지고 있다.However, such a conventional semiconductor device 1 has some drawbacks as follows.

1. 와이어(23)와 접착패드(11)간 접속을 설정하기 위해서는 값비싼 와이어-접착 머신이 필요로 되어, 생산비용을 증대시킨다. 또한, 와이어-접착 작업시 와이어-접착의 불충분으로 인해 제품 불량이 발생된다.1. To establish a connection between the wire 23 and the adhesive pad 11 requires an expensive wire-bonding machine, which increases the production cost. In addition, product defects occur due to insufficient wire-gluing in the wire-gluing operation.

2. 와이어(23)가 공기에 노출되므로 산화 및 부식이 발생되어 반도체 디바이스(1)의 신뢰성에 영향을 끼치게 된다.2. Since the wire 23 is exposed to air, oxidation and corrosion occur, which affects the reliability of the semiconductor device 1.

3. 인쇄회로기판(3)상의 회로선(3)과 반도체칩(10)간 접속을 설정하기 위해서는 납땜볼(24)이 필요로 된다. 납땜볼(24)은 떨어지거나 또는 전기적 접속을 불안정하게 하여 생산양품율에 악 영향을 야기할 수 있다.3. In order to establish the connection between the circuit line 3 on the printed circuit board 3 and the semiconductor chip 10, a solder ball 24 is required. The solder balls 24 may drop or unstable electrical connections, causing adverse effects on yield.

4. 인쇄회로기판(3)과 반도체칩(10)을 접속하는데 납땜볼(24)이 사용되므로, 상기 기판(3)과 반도체칩(10)간의 접촉영역이 비교적 작고 이들간의 바람직하지못한 분리가 발생될 수 있다.4. Since the solder ball 24 is used to connect the printed circuit board 3 and the semiconductor chip 10, the contact area between the substrate 3 and the semiconductor chip 10 is relatively small and undesired separation therebetween. Can be generated.

그러므로, 본 발명의 주된 목적은 상기 종래기술과 관련된 문제점들을 극복할 수있는 반도체 디바이스 및 그 제조방법을 제공하는 것이다.Therefore, a main object of the present invention is to provide a semiconductor device and a method of manufacturing the same that can overcome the problems associated with the prior art.

본 발명의 한 양상에 따르면, 반도체 디바이스는 그 위에 복수의 접착패드가 제공된 패드장착면을 갖는 반도체칩을 구비하고;According to an aspect of the present invention, a semiconductor device includes a semiconductor chip having a pad mounting surface provided with a plurality of adhesive pads thereon;

서로 대향하는 제1 및 제2 접착면을 갖는 유전막층을 구비하며, 상기 제1 접착면은 반도체칩의 패드장착면에 접착되고, 상기 유전막층에는 접착패드를 노출시키도록 상기 접착패드와 일치하는 위치에 복수의 홀이 형성되어 있으며, 상기 홀 각각은 벽으로 한정되며, 상기 벽은 상기 접착패드중 일치하는 패드와 함께 접촉수납공간을 형성하며;A dielectric film layer having first and second adhesive surfaces facing each other, wherein the first adhesive surface is adhered to a pad mounting surface of a semiconductor chip, and the dielectric layer is consistent with the adhesive pad to expose an adhesive pad. A plurality of holes are formed in positions, each of the holes being defined by a wall, the wall forming a contact storage space with a matching pad of the adhesive pads;

상기 접촉수납공간들에 각각 위치되는 복수의 도전접촉부를 구비하고; 그리고A plurality of conductive contacts respectively positioned in the contact storage spaces; And

상기 유전막층의 제2접촉면에 접착되는 회로레이아웃면을 갖는 인쇄회로기판을 구비하며, 상기 회로레이아웃면에는 상기 도전접촉부에 접착되는 회로선이 형성되어 있어, 상기 접착패드와 전기적인 접속이 설정되게 된다.And a printed circuit board having a circuit layout surface bonded to the second contact surface of the dielectric layer, wherein the circuit layout surface is formed with a circuit line bonded to the conductive contact portion to establish an electrical connection with the adhesive pad. do.

본 발명의 다른 양상에 따르면, 반도체 디바이스를 제조하는 방법은 반도체칩의 패드장착면에 유전막층의 제1 접착면을 접착하는 단계를 구비하고, 상기 유전막층에는 접착패드들을 노출시키도록 상기 접착패드들과 일치하는 위치에 복수의 홀이 형성되어 있으며, 상기 홀 각각은 벽으로 한정되며, 상기 벽은 상기 접착패드들중 일치하는 패드와 함께 접촉수납공간을 형성하며;According to another aspect of the present invention, a method of manufacturing a semiconductor device includes adhering a first adhesive surface of a dielectric film layer to a pad mounting surface of a semiconductor chip, wherein the adhesive pad is exposed to expose the adhesive pads to the dielectric film layer. A plurality of holes are formed at positions coinciding with each other, each of the holes being defined by a wall, the wall forming a contact storage space with a matching pad among the adhesive pads;

상기 접촉수납공간들에 복수의 도전접촉부를 설치하는 단계를 구비하고; 그리고Providing a plurality of conductive contacts in the contact storage spaces; And

상기 제1 접착면에 대향하는 상기 유전막층의 제2 접착면에 인쇄회로기판의 회로레이아웃면을 접착시키고, 그리고 상기 접착패드들과 전기적인 접속이 설정되도록 상기 회로레이아웃면에 형성된 회로선을 상기 도전접촉부들에 접착시키는 단계를 구비한다.Bonding a circuit layout surface of a printed circuit board to a second adhesive surface of the dielectric film layer opposite to the first adhesive surface, and forming a circuit line formed on the circuit layout surface to establish an electrical connection with the adhesive pads; Adhering to conductive contacts.

바람직하게, 상기 제2 접착면에는 도전접촉부의 융점보다 낮은 경화점을 갖는 열경화성 접착재가 제공된다. 따라서, 상기 유전막층에의 상기 인쇄회로기판의 접착 및 상기 도전접촉부에의 상기 회로선의 접착은 상기 회로레이아웃면이 상기 도전접촉부의 용융에 앞서 상기 제2 접착면에 이미 접착되게 하는 식으로 열경화 동작을 통해 동시에 수행될 수 있다.Preferably, the second adhesive surface is provided with a thermosetting adhesive material having a curing point lower than the melting point of the conductive contact portion. Therefore, the adhesion of the printed circuit board to the dielectric film layer and the adhesion of the circuit lines to the conductive contact portion are thermally cured in such a manner that the circuit layout surface is already adhered to the second adhesive surface prior to melting of the conductive contact portion. Operation can be performed simultaneously.

도1은 종래의 반도체 디바이스를 예시하는 부분 확대된 개략도.1 is a partially enlarged schematic diagram illustrating a conventional semiconductor device.

도2는 도1의 반도체 디바이스에 대한 개략도.2 is a schematic view of the semiconductor device of FIG.

도3 내지 도5는 본 발명에 따른 반도체 디바이스의 제1 실시예를 제조하는 방법의 단계들을 예시하는 개략도.3-5 are schematic diagrams illustrating the steps of a method of manufacturing a first embodiment of a semiconductor device according to the present invention.

도6은 본 발명에 따른 반도체 디바이스를 제조하는 제2 실시예의 중간 제작을 예시하는 개략도.6 is a schematic diagram illustrating intermediate fabrication of a second embodiment of manufacturing a semiconductor device in accordance with the present invention.

도7 및 도8은 본 발명에 따른 반도체 디바이스의 제3 실시예를 제조하는 방법에 있어서의 일부 단계를 예시하는 개략도.7 and 8 are schematic diagrams illustrating some steps in a method of manufacturing a third embodiment of a semiconductor device according to the present invention.

본 발명의 기타 특징 및 장점들이 첨부도면을 참조로 한 다음의 바람직한 실시예의 상세한 설명을 통해 명확해질 것이다.Other features and advantages of the present invention will become apparent from the following detailed description of the preferred embodiments with reference to the accompanying drawings.

도3 내지 도5에서, 본 발명에 따른 반도체 디바이스(4)의 제1의 바람직한 실시예가 제1 반도체칩(40), 유전막층(5) 및 인쇄회로기판(6)을 구비하는 것으로 도시되어 있다.3 to 5, the first preferred embodiment of the semiconductor device 4 according to the present invention is shown with a first semiconductor chip 40, a dielectric film layer 5 and a printed circuit board 6. .

반도체칩(40)은 그 위에 복수의 제1 접착패드(41)가 제공된 패드장착면(42)을 갖는다. 유전막층(5)은 서로 대향하는 제1 및 제2 접착면(50, 51)을 갖는다. 열경화 동작시 제1 접착면(50)이 상기 반도체칩(40)의 상기 패드 장착면(42)에 접착될수 있도록 열경화성 접착재(55)가 상기 제1 접착면(50)상에 제공된다. 통상적인 레이저 절단기술을 활용하여, 상기 유전막층(5)에서 상기 접착패드(41)와 일치하는 위치에 복수의 홀(52)을 형성시킴으로써 상기 접착패드가 노출되도록 한다.The semiconductor chip 40 has a pad mounting surface 42 provided with a plurality of first adhesive pads 41 thereon. The dielectric film layer 5 has first and second adhesive surfaces 50 and 51 facing each other. In the thermosetting operation, a thermosetting adhesive 55 is provided on the first adhesive surface 50 so that the first adhesive surface 50 may be adhered to the pad mounting surface 42 of the semiconductor chip 40. By utilizing a conventional laser cutting technique, the adhesive pads are exposed by forming a plurality of holes 52 in the dielectric film layer 5 at positions corresponding to the adhesive pads 41.

상기 홀(52) 각각은 벽(53)에 의해 한정되며, 이 벽은 상기 접착패드들(41)중 상기 일치한 패드와 함께 접촉수납공간을 형성한다. 복수의 도전접촉부(54)가 각각 상기 접촉수납공간들에 놓인다. 이 실시예에서, 주석볼(tin ball)이 상기 접촉수납공간 각각에 삽입되어 도전접촉부(54)로서 역할을 한다.Each of the holes 52 is defined by a wall 53, which forms a contact storage space with the matched pad of the adhesive pads 41. A plurality of conductive contacts 54 are each placed in the contact storage spaces. In this embodiment, tin balls are inserted into each of the contact receiving spaces to serve as conductive contacts 54.

인쇄회로기판(6)은 상기 도전접촉부(54)에 연결되는 회로선들(61)이 형성된 회로레이아웃면(60)을 갖는다. 상기 도전접촉부들(54)을 상기 회로선들(61)에 접착하고 그리고 상기 유전막층(5)의 상기 제2 접착면(51)에 상기 회로레이아웃면(61)을 접착하기위해 열경화 동작이 수행된다. 바람직하게, 상기 제2접착면(51)에는 도전접착부(54)의 융점보다 낮은 경화점을 갖는 열경화성 접착재(55)가 제공된다. 따라서, 상기 회로레이아웃면(60)은 상기도전접착부(54)의 용융에 앞서 이미 상기 접착면(51)에 접착되어 상기 접촉부를 봉합하게되며, 그럼으로써 각 접촉부(54)의 용융이 각각의 접촉수납공간으로부터 흘러나오지 못하도록 하여 인접한 도전접촉부(54)들과의 바람직하지 못한 접속의 형성이 방지된다.The printed circuit board 6 has a circuit layout surface 60 on which circuit lines 61 are connected to the conductive contact portion 54. A thermosetting operation is performed to bond the conductive contacts 54 to the circuit lines 61 and to bond the circuit layout surface 61 to the second adhesive surface 51 of the dielectric layer 5. do. Preferably, the second adhesive surface 51 is provided with a thermosetting adhesive material 55 having a curing point lower than the melting point of the conductive adhesive portion 54. Accordingly, the circuit layout surface 60 is already bonded to the adhesive surface 51 to seal the contact portion prior to melting the conductive adhesive portion 54, whereby the melting of each contact portion 54 causes each contact. Preventing the flow out of the storage space prevents the formation of undesired connections with adjacent conductive contacts 54.

도6은 본발명에 따른 반도체 디바이스의 제2 실시예를 보인것으로써, 주석볼을 도전접촉부로서 사용하는 대신에, 도전성 실버 페이스트와 같은 도전 페이스트로 각각의 접촉부(54')를 형성한다.6 shows a second embodiment of the semiconductor device according to the present invention, in which each contact portion 54 'is formed of a conductive paste such as conductive silver paste instead of using a tin ball as the conductive contact portion.

도7 및 8은 본 발명에 따른 반도체칩 모듈의 제3 실시예를 보인것으로써, 각 접촉수납공간에 금 또는 알루미늄 볼과 같은 도전금속물질(56)을 설치함으로써 각 접촉부(54')를 형성한다. 이어서, 상기 인쇄회로기판(도시않됨)상에서 상기 회로선과 접착하기에 앞서 각 접촉부(54')를 완성하기위해 화학적인 일렉트로플레이팅 공정(chemical electroplating process)이 수행된다.7 and 8 show a third embodiment of the semiconductor chip module according to the present invention, in which each contact portion 54 'is formed by providing a conductive metal material 56 such as gold or aluminum ball in each contact storage space. do. Subsequently, a chemical electroplating process is performed to complete each contact 54 'prior to bonding with the circuit line on the printed circuit board (not shown).

전술한 실시예들에서는 인쇄회로기판(6)에 단지 하나의 반도체칩(40)을 배치하는 것에 대해서만 기술하였지만은 실제로 필요에 따라 상기 기판(6)에 두개이상의 반도체칩(40)들을 장착할 수도 있다.In the above-described embodiments, only the placement of one semiconductor chip 40 on the printed circuit board 6 has been described. However, two or more semiconductor chips 40 may be mounted on the substrate 6 as necessary. have.

본 발명에 따른 반도체디바이스(4)의 일부 장점들은 다음과 같다.Some advantages of the semiconductor device 4 according to the invention are as follows.

1. 와이어-접착 머신이 불필요하므로, 생산비용이 크게 감소될 수 있다. 더욱이, 반도체 디바이스(4)의 생산양품율에 있어서의 와이어 접착의 역효과가 또한 제거된다.1. Since the wire-gluing machine is unnecessary, the production cost can be greatly reduced. Moreover, the adverse effect of wire bonding on the yield of the semiconductor device 4 is also eliminated.

2. 도전접촉부(54,54',54')가 봉합을 통해 인쇄회로 기판(6) 및 유전막층(5)으로 한정되므로, 도전 접촉부(54,54',54')가 산화 또는 부식으로부터 보호될 수 있다.2. The conductive contacts 54, 54 ', 54' are sealed to the printed circuit board 6 and the dielectric layer 5 by sealing, so that the conductive contacts 54, 54 ', 54' are protected from oxidation or corrosion. Can be.

3. 인쇄회로기판(6)의 회로레이아웃면(60)과 유전막층(5)의 접착면(51)사이에 납땜볼이 존재하지 않으므로, 인쇄회로기판(6)이 서로간에 비교적 큰 접촉영역을 가지면서 유전막층(5)상에 직접 장착될 수 있으며, 그럼으로써 인쇄회로기판(6)이 유전막층(5)로부터 분리되는 것이 방지될 수 있다.3. Since no solder ball exists between the circuit layout surface 60 of the printed circuit board 6 and the adhesive surface 51 of the dielectric film layer 5, the printed circuit board 6 has a relatively large contact area therebetween. And can be mounted directly on the dielectric film layer 5, thereby preventing the printed circuit board 6 from being separated from the dielectric film layer 5.

4. 본 발명의 반도체디바이스(4)에 도전접촉부(54, 54', 54')를 설계하므로, 납땜볼을 사용하는 종래의 반도체디바이스와 비교하여 생산양품률을 크게 높아진다.4. Since the conductive contact portions 54, 54 ', 54' are designed in the semiconductor device 4 of the present invention, the production yield is significantly increased as compared with the conventional semiconductor devices using solder balls.

지근까지 가장 실용적이고 바람직한 실시예들과 관계하여 본 발명을 기술하였지만은 본 발명은 전술한 실시에로만 한정됨이 없이 본 발명의 정신 및 범주내에서 모든 변형 및 균둥적인 배열이 가능하다.Although the present invention has been described with reference to the most practical and preferred embodiments, the present invention is not limited to the foregoing embodiments, but all modifications and variations are possible within the spirit and scope of the present invention.

Claims (11)

그 위에 복수의 접착패드(41)가 제공된 패드장착면(42)을 갖는 반도체칩(40)을 구비하고;A semiconductor chip 40 having a pad mounting surface 42 provided with a plurality of adhesive pads 41 thereon; 서로 대향하는 제1 및 제2 접착면(50, 51)을 갖는 유전막층(5)을 구비하며, 상기 제1 접착면(50)은 반도체칩(40)의 패드장착면(42)에 접착되고, 상기 유전막층(5)에는 접착패드(41)를 노출시키도록 상기 접착패드(41)와 일치하는 위치에 복수의 홀(52)이 형성되어 있으며, 상기 홀(52) 각각은 벽(53)으로 한정되며, 상기 벽(53)은 상기 접착패드(41)중 일치하는 패드와 함께 접촉수납공간을 형성하며;A dielectric film layer 5 having first and second adhesive surfaces 50 and 51 facing each other, wherein the first adhesive surface 50 is bonded to the pad mounting surface 42 of the semiconductor chip 40. In the dielectric layer 5, a plurality of holes 52 are formed at positions corresponding to the adhesive pads 41 to expose the adhesive pads 41, and each of the holes 52 has a wall 53. The wall (53) forms a contact storage space with the matching pads in the adhesive pad (41); 상기 접촉수납공간들에 각각 위치되는 복수의 도전접촉부(54, 54', 54')를 구비하고; 그리고A plurality of conductive contact portions (54, 54 ', 54') positioned in the contact storage spaces, respectively; And 상기 유전막층(5)의 제2접촉면(51)에 접착되는 회로레이아웃면(60)을 갖는 인쇄회로기판(6)을 구비하며, 상기 회로레이아웃면(60)에는 상기 접착패드(41)와 전기적인 접속이 설정되도록 상기 도전접촉부(54, 54', 54')에 접착되는 회로선(61)이 형성된 것을 특징으로하는 반도체 디바이스.A printed circuit board 6 having a circuit layout surface 60 adhered to the second contact surface 51 of the dielectric film layer 5, wherein the circuit layout surface 60 is electrically connected with the adhesive pad 41. And a circuit line (61) bonded to said conductive contact portion (54, 54 ', 54') so as to establish a proper connection. 제1항에 있어서,The method of claim 1, 상기 제2 접착면(51)에는 상기 도전접촉부(54, 54', 54')의 융점보다 낮은 경화점을 갖는 열경화성 접착재(55)가 제공된 것을 특징으로하는 반도체 디바이스.And the second adhesive surface (51) is provided with a thermosetting adhesive material (55) having a curing point lower than the melting point of the conductive contact portion (54, 54 ', 54'). 제1항에 있어서,The method of claim 1, 상기 도전접촉부(54, 54', 54')각각은 주석볼인 것을 특징으로하는 반도체 디바이스.And each conductive contact portion (54, 54 ', 54') is a tin ball. 제1항에 있어서,The method of claim 1, 상기 도전접촉부(54')각각은 도전페이스트로 형성되는 것을 특징으로하는 반도체 디바이스.And each conductive contact portion (54 ') is formed of a conductive paste. 제1항에 있어서,The method of claim 1, 상기 도전접촉부(54')각각은 상기 회로선(61)과 접착하기에 앞서 화학적인 일렉트로플레이팅 공정이 수행되는 도전물질(56)로 형성되는 것을 특징으로하는 반도체 디바이스.Wherein each of the conductive contact portions (54 ') is formed of a conductive material (56) subjected to a chemical electroplating process prior to adhering to the circuit lines (61). 반도체칩(40)의 패드장착면(42)에 유전막층(5)의 제1 접착면(50)을 접착하는 단계를 구비하고, 상기 유전막층(5)에는 접착패드(41)를 노출시키도록 상기 접착패드(4)와 일치하는 위치에 복수의 홀(52)이 형성되어 있으며, 상기 홀(52) 각각은 벽(53)으로 한정되며, 상기 벽(53)은 상기 접착패드(41)중 일치하는 패드와 함께 접촉수납공간을 형성하며;Adhering the first adhesive surface 50 of the dielectric layer 5 to the pad mounting surface 42 of the semiconductor chip 40, and exposing the adhesive pad 41 to the dielectric layer layer 5. A plurality of holes 52 are formed at a position coincident with the adhesive pad 4, and each of the holes 52 is defined by a wall 53, and the wall 53 is one of the adhesive pads 41. Forming a contact storage space with the matching pads; 상기 접촉수납공간들에 복수의 도전접촉부(54, 54', 54')를 설치하는 단계를구비하고; 그리고Providing a plurality of conductive contact portions (54, 54 ', 54') in the contact storage spaces; And 상기 제1 접착면(50)에 대향하는 상기 유전막층(5)의 제2 접착면(51)에 인쇄회로기판(6)의 회로레이아웃면(60)을 접착시키고, 그리고 상기 접착패드(41)들과 전기적인 접속이 설정되도록 상기 회로레이아웃면(60)에 형성된 회로선(61)을 상기 도전접촉부(54, 54', 54')들에 접착시키는 단계를 구비하는 것을 특징으로 하는 반도체 디바이스 제조방법.Bonding the circuit layout surface 60 of the printed circuit board 6 to the second adhesive surface 51 of the dielectric film layer 5 opposite the first adhesive surface 50, and the adhesive pad 41. Bonding the circuit lines 61 formed on the circuit layout surface 60 to the conductive contact portions 54, 54 ', 54' so as to establish electrical connection with them. Way. 제6항에 있어서,The method of claim 6, 상기 제2 접착면(51)에는 도전접촉부(54, 54', 54')의 융점보다 낮은 경화점을 갖는 열경화성 접착재(55)를 제공하고, 상기 유전막층(5)에의 상기 인쇄회로기판(6)의 접착 및 상기 도전접촉부(54, 54', 54')에의 상기 회로선(61)의 접착을 상기 회로레이아웃면(60)이 상기 도전접촉부(54, 54', 54')의 융용에 앞서 상기 제2 접착면(51)에 이미 접착되게 하는 식으로 열경화 동작을 통해 동시에 수행하는 것을 특징으로 하는 반도체 디바이스의 제조방법.The second adhesive surface 51 is provided with a thermosetting adhesive material 55 having a curing point lower than the melting points of the conductive contacts 54, 54 ′, 54 ′, and the printed circuit board 6 to the dielectric film layer 5. ) And adhesion of the circuit line 61 to the conductive contact portions 54, 54 ′, 54 ′ prior to the melting of the conductive contact portions 54, 54 ′, 54 ′. A method of manufacturing a semiconductor device, characterized in that to be carried out at the same time through the thermosetting operation in such a manner that is already bonded to the second adhesive surface (51). 제6항에 있어서,The method of claim 6, 상기 반도체칩(40)에의 상기 유전막층(5)의 접착은 제1접착면(50)에 제공된 열경화성 접착재(55)를 열경화시킴으로써 달성되는 것을 특징으로하는 반도체 디바이스의 제조방법.The adhesion of the dielectric film layer (5) to the semiconductor chip (40) is achieved by thermosetting the thermosetting adhesive material (55) provided on the first bonding surface (50). 제6항에 있어서,The method of claim 6, 상기 도전접촉부(54, 54', 54') 각각은 주석볼인 것을 특징으로하는 반도체 디바이스의 제조방법.And each conductive contact portion (54, 54 ', 54') is a tin ball. 제6항에 있어서,The method of claim 6, 상기 도전접촉부(54')각각은 도전페이스트로 형성하는 것을 특징으로하는 반도체 디바이스의 제조방법.And each conductive contact portion (54 ') is formed of a conductive paste. 제6항에 있어서,The method of claim 6, 상기 도전접촉부(54')각각은 상기 회로선(61)과 접착하기에 앞서 화학적인 일렉트로플레이팅 공정이 수행되는 도전물질(56)로 형성하는 것을 특징으로하는 반도체 디바이스의 제조방법.Wherein each of the conductive contact portions (54 ') is formed of a conductive material (56) subjected to a chemical electroplating process prior to adhering to the circuit lines (61).
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