KR100296125B1 - Gate electrode formation method of semiconductor device - Google Patents

Gate electrode formation method of semiconductor device Download PDF

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KR100296125B1
KR100296125B1 KR1019980057263A KR19980057263A KR100296125B1 KR 100296125 B1 KR100296125 B1 KR 100296125B1 KR 1019980057263 A KR1019980057263 A KR 1019980057263A KR 19980057263 A KR19980057263 A KR 19980057263A KR 100296125 B1 KR100296125 B1 KR 100296125B1
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forming
nitride film
pattern
gate electrode
substrate
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KR20000041404A (en
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여인석
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박종섭
주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 반도체기판상에 게이트산화막과, 도핑된 다결정실리콘층 및 질화막을 차례로 형성하는 단계와, 사진식각공정에 의해 상기 질화막과 도핑된 다결정실리콘층을 게이트전극 패턴으로 패터닝하는 단계, 소오스 및 드레인 형성을 위한 이온주입을 행하는 단계, 상기 질화막패턴을 제외한 기판부분상에 절연막을 형성하여 질화막패턴만 선택적으로 노출시키는 단계, 상기 질화막패턴을 선택적으로 제거하여 상기 도핑된 다결정실리콘패턴 표면을 선택적으로 노출시키는 단계, 상기 기판상에 타이타늄을 증착하고 열처리하여 상기 다결정실리콘패턴 상부에만 타이타늄 실리사이드를 형성하는 단계, 및 반응하지 않은 타이타늄을 선택적으로 식각하는 단계를 포함하여 이루어지는 반도체소자의 게이트전극 형성방법을 제공함으로써 낮은 저항을 갖는 게이트를 형성하고 공정의 안정성을 이룰 수 있도록 하여 수율 향상 및 저저항 게이트에 의해 고속소자 형성을 가능하게 한다.According to the present invention, a gate oxide layer, a doped polysilicon layer, and a nitride layer are sequentially formed on a semiconductor substrate, and the patterned pattern of the nitride layer and the doped polysilicon layer is formed as a gate electrode pattern by a photolithography process. Performing ion implantation for formation, forming an insulating film on a portion of the substrate other than the nitride film pattern to selectively expose only the nitride film pattern, and selectively removing the nitride film pattern to selectively expose the doped polysilicon pattern surface Forming a titanium silicide only on the polysilicon pattern by depositing and thermally treating titanium on the substrate, and selectively etching unreacted titanium, thereby forming a gate electrode forming method of a semiconductor device. Low resistance By to form a gate and achieve the stability of the process allows for high speed devices formed by the yield and the low-resistance gate.

Description

반도체소자의 게이트전극 형성방법Gate electrode formation method of semiconductor device

본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 초고집적 소자의 게이트전극 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a gate electrode of an ultra high density device.

반도체소자의 게이트전극 재료로서는 도핑된 다결정실리콘이 가장 많이 이용되고 있다. 이러한 다결정실리콘을 사용한 게이트전극은 공정이 안정하다는 장점이 있지만 다결정실리콘의 높은 비저항으로 인해 디자인룰이 작아짐에 따라 소자의 동작속도 향상이 문제가 된다. 이러한 문제를 해결하기 위해 비저항이 낮은 타이타늄 실리사이드(TiSix)등의 고융점금속을 게이트전극으로 사용하는 방법이 제안되었다. 도 1은 타이타늄 실리사이드를 게이트전극으로 사용한 경우의 종래기술을 도시한 것으로, 반도체기판(1)상에 게이트절연막(2)을 형성하고, 이위에 도핑된 다결정실리콘(3)을 증착하고, 마스크를 이용하여 게이트전극 형태로 패터닝한 다음, 패터닝시 게이트전극 및 게이트절연막이 받은 손상을 회복시킨다. 이어서 CVD산화막을 전면 증착한 후 건식식각하여 스페이서(6')를 형성하고, 소오스 및 드레인 이온주입을 행한 다음, 타이타늄 실리사이드(9)를 다결정실리콘(3)상에 증착하고 후속열처리하여 TiSix를 형성한다. 다음에 반응하지 않은 Ti 및 TiN을 선택적으로 식각하고 후속열처리를 수행한 후, 기판 전면에 CVD산화막을 증착한다.As the gate electrode material of the semiconductor device, doped polycrystalline silicon is most often used. The gate electrode using the polysilicon has the advantage that the process is stable, but due to the high specific resistance of the polysilicon, as the design rule becomes smaller, the operation speed of the device becomes a problem. In order to solve this problem, a method of using a high melting point metal such as titanium silicide (TiSix) having a low resistivity as a gate electrode has been proposed. FIG. 1 shows a prior art in which titanium silicide is used as a gate electrode. A gate insulating film 2 is formed on a semiconductor substrate 1, a doped polysilicon 3 is deposited thereon, and a mask is formed. After the patterning is performed in the form of a gate electrode, damage to the gate electrode and the gate insulating layer is recovered during patterning. Subsequently, the CVD oxide film is deposited on the entire surface, followed by dry etching to form spacers 6 ', source and drain ion implantation, followed by deposition of titanium silicide 9 on polycrystalline silicon 3 and subsequent heat treatment to form TiSix. do. Next, Ti and TiN which have not reacted are selectively etched and subjected to subsequent heat treatment, and then a CVD oxide film is deposited on the entire surface of the substrate.

상술한 종래의 TiSi2 살리사이드(salicide) 게이트전극 형성방법은 공정이 복잡하고, 타이타늄 실리사이드가 소오스 및 드레인 접합부위에도 형성되므로 이로 인한 누설전류때문에 DRAM에 적용하기 어려운 문제가 있다.The conventional TiSi2 salicide gate electrode forming method described above has a complicated process, and since titanium silicide is also formed at the source and drain junctions, it is difficult to apply to DRAM due to the leakage current.

본 발명은 상술한 문제점을 해결하기 위한 것으로, 질화막을 이용하여 게이트전극위에만 타이타늄 실리사이드를 형성함으로써 DRAM에 적용이 가능하고 낮은 저항을 갖는 게이트를 얻을 수 있는 반도체소자의 게이트전극 형성방법에 관한 것이다.SUMMARY OF THE INVENTION The present invention is directed to a method of forming a gate electrode of a semiconductor device, which is applicable to DRAM and obtains a gate having low resistance by forming titanium silicide only on the gate electrode using a nitride film. .

상기 목적을 달성하기 위한 본 발명의 반도체소자의 게이트전극 형성방법은 반도체기판상에 게이트산화막과, 도핑된 다결정실리콘층 및 질화막을 차례로 형성하는 단계와, 사진식각공정에 의해 상기 질화막과 도핑된 다결정실리콘층을 게이트전극 패턴으로 패터닝하는 단계, 소오스 및 드레인 형성을 위한 이온주입을 행하는 단계, 상기 질화막패턴을 제외한 기판부분상에 절연막을 형성하여 질화막패턴만 선택적으로 노출시키는 단계, 상기 질화막패턴을 선택적으로 제거하여 상기 도핑된 다결정실리콘패턴 표면을 선택적으로 노출시키는 단계, 상기 기판상에 타이타늄을 증착하고 열처리하여 상기 다결정실리콘패턴 상부에만 타이타늄 실리사이드를 형성하는 단계, 및 반응하지 않은 타이타늄을 선택적으로 식각하는 단계를 포함하여 이루어진다.A method of forming a gate electrode of a semiconductor device of the present invention for achieving the above object is to form a gate oxide film, a doped polysilicon layer and a nitride film in sequence on a semiconductor substrate, and the nitride film and the doped polycrystal by a photolithography process Patterning a silicon layer into a gate electrode pattern, performing ion implantation to form a source and a drain, selectively forming only an insulating film pattern on the substrate portion except for the nitride film pattern, selectively exposing the nitride film pattern Selectively exposing the surface of the doped polysilicon pattern to deposit titanium, depositing and thermally treating titanium on the substrate to form titanium silicide only on the polysilicon pattern, and selectively etching unreacted titanium A step is made.

도 1은 종래의 타이타늄 실리사이드 게이트전극 형성방법을 도시한 단면도,1 is a cross-sectional view showing a conventional method of forming a titanium silicide gate electrode;

도 2a 내지 2g는 본 발명의 일실시예에 의한 타이타늄 살리사이드 게이트전극 형성방법을 도시한 공정순서도,2A to 2G are flowcharts illustrating a method of forming a titanium salicide gate electrode according to an embodiment of the present invention;

도 3a 내지 3g는 본 발명의 다른 실시예에 의한 타이타늄 살리사이드 게이트전극 형성방법을 도시한 공정순서도.3A to 3G are flowcharts showing a method of forming a titanium salicide gate electrode according to another embodiment of the present invention.

*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

1.반도체기판 2.게이트산화막1. Semiconductor substrate 2. Gate oxide film

3.도핑된 다결정실리콘층 4.질화막3. Doped polysilicon layer 4. Nitride film

5.열산화막 6'.측벽 스페이서5.Thermal Oxide 6'.Side Wall Spacer

7.CVD산화막 8.타이타늄막7.CVD oxide film 8.Titanium film

9.타이타늄 실리사이드 10.CVD산화막9.Titanium silicide 10.CVD oxide film

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 2a 내지 2g에 본 발명의 일실시예에 의한 반도체소자의 타이타늄 살리사이드 게이트전극 형성방법을 공정순서에 따라 단면도로 나타내었다.2A to 2G, a method of forming a titanium salicide gate electrode of a semiconductor device according to an embodiment of the present invention is shown in cross-section according to a process sequence.

먼저, 도 2a를 참조하면, 반도체기판(1)상에 열산화에 의해 게이트산화막(2)을 형성하고, 이위에 도핑된 다결정실리콘(3)과 질화막(4)을 차례로 형성한 후, 사진식각공정에 의해 상기 질화막(4)과 도핑된 다결정실리콘층(3)을 게이트전극 패턴으로 패터닝한 다음, 도 2b에 나타낸 바와 같이 산화분위기에서 열처리를 행하여 게이트전극 측면에 열산화막(5)을 형성한 후, LDD이온주입을 행한다. 상기 도핑된 다결정실리콘은 1000-2500Å 두께로 형성하고, 질화막은 500-1000Å 두께로 형성하는 것이 바람직하다.First, referring to FIG. 2A, a gate oxide film 2 is formed by thermal oxidation on a semiconductor substrate 1, and then a polycrystalline silicon 3 and a nitride film 4 doped thereon are sequentially formed, followed by photolithography. The nitride film 4 and the doped polysilicon layer 3 were patterned by a gate electrode pattern by a process, and then thermally oxidized in the oxidation atmosphere as shown in FIG. 2B to form a thermal oxide film 5 on the side of the gate electrode. After that, LDD ion implantation is performed. The doped polysilicon is preferably formed to have a thickness of 1000-2500 kPa, and the nitride film is formed to have a thickness of 500-1000 kPa.

다음에 도 2c를 참조하면, 기판 전면에 산화막을 형성한 후, 마스크없이 전면 건식식각하여 산화막 스페이서(6')를 상기 질화막 및 도핑된 다결정실리콘층 패턴의 측면에 형성한 다음, 소오스 및 드레인 이온주입을 행한다. 상기 스페이서는 질화막으로 형성할 수도 있다.Next, referring to FIG. 2C, after the oxide film is formed on the entire surface of the substrate, the entire surface is dry-etched without a mask to form the oxide spacer 6 ′ on the side of the nitride film and the doped polysilicon layer pattern, and then source and drain ions. Inject. The spacer may be formed of a nitride film.

이어서 도 2d를 참조하면, 기판 전면에 CVD절연막(7)을 충분한 두께, 예컨대 3000-5000Å 두께로 형성한 후, 도 2e에 나타낸 바와 같이 CMP(chemical mechanical polishing)공정을 통해 상기 CVD절연막(7)을 연마하여 질화막 및 다결정실리콘패턴을 노출시킨 다음, 기판을 H3PO4에 담그어 질화막을 제거해 냄으로써 도핑된 다결정실리콘패턴(3)만 선택적으로 노출되도록 한다.Next, referring to FIG. 2D, a CVD insulating film 7 is formed on the entire surface of the substrate to a sufficient thickness, for example, 3000-5000 mm thick, and then the CVD insulating film 7 is subjected to a chemical mechanical polishing (CMP) process as shown in FIG. 2E. After polishing, the nitride film and the polysilicon pattern are exposed, and then the substrate is immersed in H3PO4 to remove the nitride film so that only the doped polysilicon pattern 3 is selectively exposed.

다음에 도 2f에 나타낸 바와 같이 기판상에 타이타늄(8)을 300-600Å 두께로 증착한 후, 500-700℃의 온도로 전기로에서 열처리를 행하거나 또는 650-800℃의 온도로 RTP에서 열처리를 행하여 상기 다결정실리콘패턴 상부에 타이타늄 실리사이드(9)를 형성한 후, 도 2g에 나타낸 바와 같이 반응하지 않은 타이타늄을 선택적으로 예컨대 습식식각한 후, 기판 전면에 CVD절연막(10)을 형성한 다음 후속공정을 진행한다.Next, as shown in FIG. 2F, titanium (8) is deposited on the substrate to a thickness of 300-600 kPa, and then heat-treated in an electric furnace at a temperature of 500-700 ° C or heat-treated in RTP at a temperature of 650-800 ° C. After forming the titanium silicide 9 on the polysilicon pattern, and selectively wet etching the unreacted titanium as shown in FIG. 2G, and then forming a CVD insulating film 10 on the entire surface of the substrate, followed by a subsequent step. Proceed.

다음에 도 3a 내지 3g를 참조하여 본 발명의 다른 실시예에 의한 타이타늄 살리사이드 게이트전극 형성방법을 설명한다.Next, a method of forming a titanium salicide gate electrode according to another embodiment of the present invention will be described with reference to FIGS. 3A to 3G.

먼저, 도 3a를 참조하면, 반도체기판(1)상에 열산화에 의해 게이트산화막(2)을 형성하고, 이위에 도핑된 다결정실리콘(3)과 질화막(4)을 차례로 형성한 후, 사진식각공정에 의해 상기 질화막(4)과 도핑된 다결정실리콘층(3)을 게이트전극 패턴으로 패터닝한 다음, 도 2b에 나타낸 바와 같이 산화분위기에서 열처리를 행하여 게이트전극 측면에 열산화막(5)을 형성한 후, LDD이온주입을 행한다. 상기 도핑된 다결정실리콘은 1000-2500Å 두께로 형성하고, 질화막은 1000-2500Å 두께로 형성하는 것이 바람직하다.First, referring to FIG. 3A, a gate oxide film 2 is formed by thermal oxidation on a semiconductor substrate 1, and then a polycrystalline silicon 3 and a nitride film 4 doped thereon are sequentially formed, followed by photolithography. The nitride film 4 and the doped polysilicon layer 3 were patterned by a gate electrode pattern by a process, and then thermally oxidized in the oxidation atmosphere as shown in FIG. 2B to form a thermal oxide film 5 on the side of the gate electrode. After that, LDD ion implantation is performed. The doped polysilicon is preferably formed to have a thickness of 1000-2500 kPa, and the nitride film is formed to have a thickness of 1000-2500 kPa.

다음에 도 3c를 참조하면, 기판 전면에 산화막을 형성한 후, 마스크없이 전면 건식식각하여 산화막 스페이서(6')를 상기 질화막 및 도핑된 다결정실리콘층 패턴의 측면에 형성한 다음, 소오스 및 드레인 이온주입을 행한다.Next, referring to FIG. 3C, after the oxide film is formed on the entire surface of the substrate, the entire surface is dry-etched without a mask to form the oxide spacer 6 ′ on the side of the nitride film and the doped polysilicon layer pattern, and then source and drain ions. Inject.

이어서 도 3d를 참조하면, 산화분위기에서 열처리를 하여 열산화막(7)을 소오스 및 드레인영역 상부에 충분히 두껍게 성장시킨다. 상기 열산화막은 습식 또는 건식 산화분위기에서 성장시킬 수 있으며, 그 두께는 100-300Å 정도로 하는 것이 바람직하다. 또한, 열산화막(7)의 성장시 소오스 및 드레인 이온주입된 영역이 활성화되게 된다.Next, referring to FIG. 3D, the thermal oxide film 7 is sufficiently thickly grown on the source and drain regions by heat treatment in an oxidizing atmosphere. The thermal oxide film can be grown in a wet or dry oxidation atmosphere, the thickness is preferably about 100-300Å. In addition, the source and drain ion implanted regions are activated when the thermal oxide film 7 is grown.

다음에 도 3e에 나타낸 바와 같이 등방성식각에 의해 상기 질화막(4)을 선택적으로 제거하여 다결정실리콘패턴(3)을 노출시킨다. 이때 질화막은 HF와 높은 온도의 H3PO4를 이용한 습식식각에 의해 제거하거나 건식식각에 의해 제거할 수 있다.Next, as shown in FIG. 3E, the nitride film 4 is selectively removed by isotropic etching to expose the polysilicon pattern 3. In this case, the nitride film may be removed by wet etching using HF and H 3 PO 4 of high temperature or by dry etching.

이어서 도 3f에 나타낸 바와 같이 기판상에 타이타늄(8)을 300-600Å 두께로 증착한 후, 500-700℃의 온도로 전기로에서 열처리를 행하거나 또는 650-800℃의 온도로 RTP에서 열처리를 행하여 상기 다결정실리콘패턴(3) 상부에 타이타늄 실리사이드(9)를 형성한 후, 도 3g에 나타낸 바와 같이 반응하지 않은 타이타늄을 선택적으로 예컨대 NH4OH, H2O2, H2O 혼합용액에서 습식식각한 후, 기판 전면에 CVD절연막(10)을 형성한 다음 후속공정을 진행한다.Subsequently, as shown in FIG. 3F, titanium (8) was deposited on the substrate to a thickness of 300-600 kPa, and then heat-treated in an electric furnace at a temperature of 500-700 ° C. or heat-treated in RTP at a temperature of 650-800 ° C. After the titanium silicide 9 was formed on the polysilicon pattern 3, the unreacted titanium was selectively wetted in a mixed solution of NH 4 OH, H 2 O 2 , and H 2 O as shown in FIG. 3G. After that, the CVD insulating film 10 is formed on the entire surface of the substrate, and then a subsequent process is performed.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

본 발명에 의한 게이트전극 형성방법에 의하면, 타이타늄 실리사이드를 게이트전극위에만 형성시킬 수 있어 DRAM에 적용이 가능하고, 또한 주위의 절연막에 의해 라인간의 브릿지(bridge)를 막아주므로 낮은 저항을 갖는 게이트를 형성할 수 있으며, 질화막이 CMP시 정지막으로 작용하여 공정의 안정성을 이룰 수 있다. 따라서 수율 향상 및 저저항 게이트에 의해 고속소자 형성이 가능하게 된다.According to the gate electrode forming method according to the present invention, since titanium silicide can be formed only on the gate electrode, it can be applied to a DRAM, and a gate having a low resistance is prevented because a bridge between lines is prevented by a surrounding insulating film. The nitride film may serve as a stop film during CMP, thereby achieving stability of the process. Therefore, the high speed device can be formed by the yield improvement and the low resistance gate.

Claims (8)

반도체기판상에 게이트산화막과, 도핑된 다결정실리콘층 및 질화막을 차례로 형성하는 단계와;Sequentially forming a gate oxide film, a doped polysilicon layer, and a nitride film on the semiconductor substrate; 사진식각공정에 의해 상기 질화막과 도핑된 다결정실리콘층을 게이트전극 패턴으로 패터닝하는 단계;Patterning the nitride film and the doped polysilicon layer into a gate electrode pattern by a photolithography process; 소오스 및 드레인 형성을 위한 이온주입을 행하는 단계;Performing ion implantation for source and drain formation; 상기 질화막패턴을 제외한 기판부분상에 절연막을 형성하여 질화막패턴만 선택적으로 노출시키는 단계;Selectively forming only an nitride film pattern by forming an insulating film on a portion of the substrate other than the nitride film pattern; 상기 질화막패턴을 선택적으로 제거하여 상기 도핑된 다결정실리콘패턴 표면을 선택적으로 노출시키는 단계;Selectively removing the nitride film pattern to selectively expose a surface of the doped polysilicon pattern; 상기 기판상에 타이타늄을 증착하고 열처리하여 상기 다결정실리콘패턴 상부에만 타이타늄 실리사이드를 형성하는 단계; 및Depositing and heat treating titanium on the substrate to form titanium silicide only on the polysilicon pattern; And 반응하지 않은 타이타늄을 선택적으로 식각하는 단계를 포함하는 반도체소자의 게이트전극 형성방법.A method of forming a gate electrode of a semiconductor device comprising the step of selectively etching titanium not reacted. 제1항에 있어서,The method of claim 1, 상기 질화막패턴을 제외한 기판부분상에 절연막을 형성하여 질화막패턴만 선택적으로 노출시키는 단계는The step of selectively exposing only the nitride film pattern by forming an insulating film on the substrate portion excluding the nitride film pattern 기판 전면에 CVD절연막을 충분한 두께로 형성하는 공정과,Forming a CVD insulating film in a sufficient thickness over the entire substrate; CMP공정에 의해 상기 CVD절연막을 연마하여 질화막패턴을 노출시키는 공정으로 이루어지는 것을 특징으로 하는 반도체소자의 게이트전극 형성방법.And forming a nitride film pattern by grinding the CVD insulating film by a CMP process. 제1항에 있어서,The method of claim 1, 상기 질화막패턴을 제외한 기판부분상에 절연막을 형성하여 질화막패턴만 선택적으로 노출시키는 단계는 산화분위기에서 열처리를 하여 열산화막을 소오스 및 드레인영역 상부에 충분한 두께로 성장시키는 공정으로 이루어지는 것을 특징으로 하는 반도체소자의 게이트전극 형성방법.Selectively exposing only the nitride film pattern by forming an insulating film on a portion of the substrate except for the nitride film pattern is a step of growing a thermal oxide film to a sufficient thickness on the source and drain regions by heat treatment in an oxidizing atmosphere Method for forming a gate electrode of the device. 제3항에 있어서,The method of claim 3, 상기 열산화막은 습식 또는 건식 산화분위기에서 성장시키는 것을 특징으로 하는 반도체소자의 게이트전극 형성방법.And the thermal oxide film is grown in a wet or dry oxidation atmosphere. 제3항에 있어서,The method of claim 3, 상기 열산화막은 100-300Å 두께로 성장시키는 것을 특징으로 하는 반도체소자의 게이트전극 형성방법.The thermal oxide film is a gate electrode forming method of a semiconductor device, characterized in that to grow to a thickness of 100-300Å. 제3항에 있어서,The method of claim 3, 상기 열산화막 성장시 소오스 및 드레인 이온주입된 영역이 활성화되는 것을 특징으로 하는 반도체소자의 게이트전극 형성방법.The method of forming a gate electrode of a semiconductor device, wherein the source and drain ion implanted regions are activated when the thermal oxide film is grown. 제1항에 있어서,The method of claim 1, 상기 질화막은 HF와 높은 온도의 H3PO4를 이용한 습식식각에 의해 제거하거나 건식식각에 의해 제거하는 것을 특징으로 하는 반도체소자의 게이트전극 형성방법.The nitride film is a gate electrode forming method of a semiconductor device, characterized in that the removal by wet etching or dry etching using HF and H3PO4 of high temperature. 제1항에 있어서,The method of claim 1, 상기 반응하지 않은 타이타늄은 상기 기판을 NH4OH, H2O2, H2O 혼합용액에 담가 제거하는 것을 특징으로 하는 반도체소자의 게이트전극 형성방법.The method of claim 1 , wherein the unreacted titanium is immersed and removed in the NH 4 OH, H 2 O 2 , and H 2 O mixed solution.
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