KR100265849B1 - A method for fabricating MOSFET - Google Patents

A method for fabricating MOSFET Download PDF

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Publication number
KR100265849B1
KR100265849B1 KR1019960067622A KR19960067622A KR100265849B1 KR 100265849 B1 KR100265849 B1 KR 100265849B1 KR 1019960067622 A KR1019960067622 A KR 1019960067622A KR 19960067622 A KR19960067622 A KR 19960067622A KR 100265849 B1 KR100265849 B1 KR 100265849B1
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silicon substrate
layer
film
forming
gate electrode
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KR1019960067622A
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KR19980048967A (en
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홍상희
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Abstract

PURPOSE: A method for manufacturing a field effect transistor is to effectively remove an anti-reflection coating without damage of a silicon substrate, thereby avoiding process failure due to a residual substance produced in a process for forming of a self aligned silicide. CONSTITUTION: A gate insulating layer, a polysilicon layer and an anti-reflective oxynitride layer are successively formed on a silicon substrate(10). The oxynitride layer, the polysilicon layer and the gate insulating layer are selectively etched to form a gate electrode. An impurity region in low concentration is formed on the silicon substrate. A spacer insulating layer is formed on the sidewall of the gate electrode. An impurity region in high concentration is formed on the silicon substrate. An oxide layer is formed on the exposed silicon substrate. The oxide layer and the oxidized nitride layer are removed by an etchant. A self-aligned silicide layer(19) is formed on the exposed gate electrode and the silicon substrate.

Description

전계 효과 트랜지스터 제조방법{A method for fabricating MOSFET}Field effect transistor manufacturing method {A method for fabricating MOSFET}

본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자의 기본적인 소자인 전계 효과 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a method for manufacturing a field effect transistor, which is a basic device of a semiconductor device.

반도체 소자의 집적도가 증가하고, 패턴의 미세화가 진행됨에 따라 사진 공정에서 디자인 룰의 축소를 계속하여 모색하고 있으나, 하부층이 반사율이 클 경우 미세 마스크 패턴을 형성하는데 어려움이 있다. 이러한 높은 반사율은 마스크 패턴으로 사용되는 포토레지스트 패턴 형성시 노칭(notching), 포토레지스트 패턴의 형상 불량 및 형성하고자 하는 패턴의 밀집도 및 방향에 따른 패턴 크기의 불균일 등의 문제점을 야기한다. 이러한 현상은 패턴 크기가 줄어들수록 더욱 심각해지는 경향을 보인다. 특히, 패턴 크기가 0.35㎛ 이하에서는 반사 방지막을 채용하지 않고서는 안정적인 사진 공정과 식각 공정을 진행하는데 어려움이 있다.As the degree of integration of semiconductor devices increases and pattern refinement proceeds, design rules are continuously reduced in the photographing process. However, when the lower layer has a large reflectance, it is difficult to form a fine mask pattern. Such high reflectance causes problems such as notching in forming the photoresist pattern used as the mask pattern, poor shape of the photoresist pattern, and uneven pattern size according to the density and direction of the pattern to be formed. This phenomenon tends to be more severe as the pattern size decreases. In particular, when the pattern size is 0.35 μm or less, it is difficult to proceed with a stable photographic process and an etching process without employing an antireflection film.

특히, 자기정렬 실리사이드막을 형성할 때, 게이트 형성후 실리사이드 형성을 위하여 티타늄(Ti), 코발트(Co), 백금(Pt) 등의 물질막을 증착한 다음 급속 열처리에 의하여 실리콘 기판과 증착 물질간의 반응에 의하여 TixSiy막, CoxSiy막, PtxSiy막 등이 형성된다.In particular, when forming a self-aligned silicide film, a material film such as titanium (Ti), cobalt (Co), platinum (Pt), etc. is deposited to form silicide after gate formation, and then a rapid heat treatment is performed to react the silicon substrate with the deposition material. As a result, a Ti x Si y film, a Co x Si y film, a Pt x Si y film, and the like are formed.

이러한 공정의 수행을 위해서는 폴리실리콘막으로 구성된 게이트 전극 상부와 활성 영역에 실리사이드 반응을 억제하는 산화막 또는 질화막 등이 존재하면 안된다. 그러나, 대부분의 경우 게이트 전극 상부의 반사 방지막의 잔류로 인하여 실리사이드 반응이 잘 일어나지 않기 때문에 반사 방지막 사용이 제한되는 문제점이 있었다.In order to perform such a process, an oxide film or a nitride film that suppresses the silicide reaction should not be present in the upper portion of the gate electrode composed of the polysilicon film and in the active region. However, in most cases, there is a problem that the use of the anti-reflection film is limited because the silicide reaction does not easily occur due to the remaining of the anti-reflection film on the gate electrode.

본 발명은 자기정렬 실리사이드막 형성시 반사 방지막이 잔류하지 않도록 효과적으로 제거할 수 있는 전계 효과 트랜지스터 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a field effect transistor which can effectively remove an antireflection film so that it does not remain when a self-aligned silicide film is formed.

도 1a 내지 도 1e는 본 발명의 일 실시예에 따른 전계 효과 트랜지스터 제조 공정도.1A to 1E are diagrams illustrating a field effect transistor fabrication process according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

10 : 실리콘 기판 11 : 게이트 산화막10 silicon substrate 11 gate oxide film

12 : 폴리실리콘막 12a : 게이트 전극12 polysilicon film 12a gate electrode

13 : 산화질화막 14 : 포토레지스트 패턴13 oxynitride film 14 photoresist pattern

15a : n-소오스 15b : n-드레인15a: n - source 15b: n - drain

16 : 산화막 스페이서 17a : n+소오스16: oxide film spacer 17a: n + source

17b : n+드레인 18 : 산화막17b: n + drain 18: oxide film

19 : 자기정렬 실리사이드막19: self-aligned silicide film

상기의 기술적 과제를 달성하기 위한 본 발명의 특징적인 전계 효과 트랜지스터 제조방법은, 실리콘 기판 상에 게이트 절연막, 폴리실리콘막 및 반사 방지용 산화질화막을 차례로 형성하는 제1 단계; 상기 산화질화막, 상기 폴리실리콘막 및 상기 게이트 절연막을 차례로 선택 식각하여 게이트 전극을 형성하는 제2 단계; 상기 실리콘 기판에 저농도 불순물 영역을 형성하는 제3 단계; 상기 게이트 전극 측벽 부분에 스페이서 절연막을 형성하는 제4 단계; 상기 실리콘 기판 상에 고농도 불순물 영역을 형성하는 제5 단계; 상기 제5 단계 수행 후 노출된 상기 실리콘 기판 표면에 산화막을 형성하는 제6 단계; 인산을 포함하는 식각제를 사용하여 상기 산화막 및 상기 산화질화막을 습식 제거하는 제7 단계; 및 상기 제7 단계 수행 후 노출된 상기 게이트 전극 및 상기 실리콘 기판 표면에 자기정렬 실리사이드막을 형성하는 제8 단계를 포함하여 이루어진다.A characteristic field effect transistor manufacturing method of the present invention for achieving the above technical problem comprises a first step of sequentially forming a gate insulating film, a polysilicon film and an antireflection oxynitride film on a silicon substrate; A second step of forming a gate electrode by selectively etching the oxynitride layer, the polysilicon layer, and the gate insulating layer; Forming a low concentration impurity region in the silicon substrate; Forming a spacer insulating film on the sidewall portion of the gate electrode; Forming a high concentration impurity region on the silicon substrate; A sixth step of forming an oxide film on the exposed surface of the silicon substrate after performing the fifth step; A seventh step of wet removing the oxide film and the oxynitride film using an etchant including phosphoric acid; And an eighth step of forming a self-aligned silicide layer on the exposed surface of the gate electrode and the silicon substrate after performing the seventh step.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

첨부된 도면 도 1a 내지 도 1e는 본 발명의 일 실시예에 따른 전계 효과 트랜지스터 제조 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.1A to 1E illustrate a process of manufacturing a field effect transistor according to an embodiment of the present invention, which will be described below with reference to the drawings.

본 실시예에 따른 공정은 먼저, 도 1a에 도시된 바와 같이 실리콘 기판(10) 상에 게이트 산화막(11)을 성장시키고, 그 상부에 폴리실리콘막(12)을 증착한 다음, 그 상부에 반사 방지막인 산화질화막(13)을 형성한다. 계속하여, 전체구조 상부에 포토레지스트를 도포하고, 이를 패터닝하여 게이트 전극 형성을 위한 포토레지스트 패턴(14)을 형성한다.In the process according to the present embodiment, first, as shown in FIG. 1A, a gate oxide film 11 is grown on a silicon substrate 10, a polysilicon film 12 is deposited thereon, and then a reflection thereon. An oxynitride film 13, which is a prevention film, is formed. Subsequently, a photoresist is applied over the entire structure and patterned to form a photoresist pattern 14 for forming a gate electrode.

다음으로, 도 1b에 도시된 바와 같이 포토레지스트 패턴(14)을 식각 장벽으로 하여 산화질화막(13), 폴리실리콘막(12) 및 게이트 산화막(11)을 선택 식각하여 게이트 전극(12a)을 형성한 다음, 포토레지스트 패턴(14)을 제거한다. 계속하여, 저농도 n형 불순물 이온주입을 실시하여 실리콘 기판(10) 상에 n-소오스/드레인(15a, 15b)을 형성한다.Next, as illustrated in FIG. 1B, the gate electrode 12a is formed by selectively etching the oxynitride layer 13, the polysilicon layer 12, and the gate oxide layer 11 using the photoresist pattern 14 as an etch barrier. Next, the photoresist pattern 14 is removed. Subsequently, low concentration n-type impurity ion implantation is performed to form n − sources / drains 15a and 15b on the silicon substrate 10.

이어서, 도 1c에 도시된 바와 같이 전체구조 상부에 산화막을 증착하고, 이를 비등방성 전면 식각하여 게이트 전극(12a)의 측벽 부분에 스페이서 산화막(16)을 형성한다. 여기서, 스페이서 산화막(15)은 저농도 도핑 드레인 구조 형성을 위한 것이며, 이후의 공정에서 게이트 전극(12a)의 산화를 방지한다. 계속하여, 고농도의 n형 불순물 이온주입을 실시하여 실리콘 기판(10) 상에 n+소오스/드레인(17a, 17b)을 형성한다.Subsequently, an oxide film is deposited on the entire structure as shown in FIG. 1C and anisotropically etched to form a spacer oxide film 16 on the sidewall portion of the gate electrode 12a. Here, the spacer oxide film 15 is for forming a low concentration doped drain structure, and prevents oxidation of the gate electrode 12a in a subsequent process. Subsequently, a high concentration of n-type impurity ions are implanted to form n + sources / drains 17a and 17b on the silicon substrate 10.

다음으로, 도 1d에 도시된 바와 같이 700℃ 내지 950℃ 온도 범위에서 적정 유량으로 산소와 질소를 공급하면서 n+소오스/드레인(17a, 17b) 표면을 산화시켜 산화막(18)을 형성한다. 이때, 산화막(18)의 두께는 30Å 내지 200Å이다. 그리고, 산화질화막(13)은 최소한 1000℃ 이상의 고온에서 산화가 일어나므로 거의 영향을 받지 않는다.Next, as illustrated in FIG. 1D, the surface of n + source / drain 17a and 17b is oxidized while supplying oxygen and nitrogen at an appropriate flow rate in the temperature range of 700 ° C. to 950 ° C. to form an oxide film 18. At this time, the thickness of the oxide film 18 is 30 kPa to 200 kPa. The oxynitride film 13 is hardly affected because oxidation occurs at a high temperature of at least 1000 ° C.

다음으로, 도 1e에 도시된 바와 같이 인산(H3PO4) 용액을 사용하여 산화질화막(13) 및 산화막(18)을 식각한다. 이때, 사용되는 인산 용액은 120℃ 내지 200℃ 온도가 적당하며, 10분 내지 30분 동안 식각을 수행한다. 또한, 식각되는 산화막(18)에 대한 산화질화막(13)의 식각 선택비는 30:1 이상이며, 산화질화막(13)의 충분한 제거를 위하여 산화질화막(13) 두께의 2배 정도를 식각 타겟으로 한다. 이후, 노출된 반도체 기판(10) 및 게이트 전극(12a) 표면에 자기정렬 실리사이드막(19)을 형성한다.Next, as illustrated in FIG. 1E, the oxynitride film 13 and the oxide film 18 are etched using a phosphoric acid (H 3 PO 4 ) solution. At this time, the phosphoric acid solution used is suitable for 120 ℃ to 200 ℃ temperature, the etching is carried out for 10 to 30 minutes. In addition, the etching selectivity of the oxynitride film 13 to the etched oxide film 18 is 30: 1 or more, and about twice the thickness of the oxynitride film 13 is used as an etch target for sufficient removal of the oxynitride film 13. do. Thereafter, a self-aligned silicide film 19 is formed on the exposed semiconductor substrate 10 and the gate electrode 12a.

상기와 같은 본 발명을 실시하면 게이트 전극 형성시 반사 방지막을 효과적으로 제거할 수 있기 때문에, 후속 자기정렬 실리사이드 공정을 효과적으로 진행할 수 있다.According to the present invention as described above, since the anti-reflection film can be effectively removed when the gate electrode is formed, the subsequent self-aligned silicide process can be effectively performed.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

상기한 바와 같이 본 발명은 실리콘 기판에 손상을 가하지 않으면서 효과적으로 반사 방지막을 제거하여 후속 자기정렬 실리사이드 공정시 잔유물에 의한 공정 실패를 방지하는 효과가 있다.As described above, the present invention has the effect of effectively preventing the anti-reflection film without damaging the silicon substrate to prevent the process failure by the residue during the subsequent self-aligned silicide process.

Claims (5)

실리콘 기판 상에 게이트 절연막, 폴리실리콘막 및 반사 방지용 산화질화막을 차례로 형성하는 제1 단계;A first step of sequentially forming a gate insulating film, a polysilicon film, and an antireflection oxynitride film on the silicon substrate; 상기 산화질화막, 상기 폴리실리콘막 및 상기 게이트 절연막을 차례로 선택 식각하여 게이트 전극을 형성하는 제2 단계;A second step of forming a gate electrode by selectively etching the oxynitride layer, the polysilicon layer, and the gate insulating layer; 상기 실리콘 기판에 저농도 불순물 영역을 형성하는 제3 단계;Forming a low concentration impurity region in the silicon substrate; 상기 게이트 전극 측벽 부분에 스페이서 절연막을 형성하는 제4 단계;Forming a spacer insulating film on the sidewall portion of the gate electrode; 상기 실리콘 기판 상에 고농도 불순물 영역을 형성하는 제5 단계;Forming a high concentration impurity region on the silicon substrate; 상기 제5 단계 수행 후 노출된 상기 실리콘 기판 표면에 산화막을 형성하는 제6 단계;A sixth step of forming an oxide film on the exposed surface of the silicon substrate after performing the fifth step; 인산을 포함하는 식각제를 사용하여 상기 산화막 및 상기 산화질화막을 습식 제거하는 제7 단계; 및A seventh step of wet removing the oxide film and the oxynitride film using an etchant including phosphoric acid; And 상기 제7 단계 수행 후 노출된 상기 게이트 전극 및 상기 실리콘 기판 표면에 자기정렬 실리사이드막을 형성하는 제8 단계An eighth step of forming a self-aligned silicide layer on the exposed gate electrode and the silicon substrate after performing the seventh step 를 포함하여 이루어진 전계 효과 트랜지스터 제조방법.Field effect transistor manufacturing method comprising a. 제1항에 있어서,The method of claim 1, 상기 산화막이,The oxide film, 30Å 내지 200Å 두께인 것을 특징으로 하는 전계 효과 트랜지스터 제조방법.A method for manufacturing a field effect transistor, characterized in that it is 30 to 200 kHz thickness. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 산화막이,The oxide film, 700℃ 내지 950℃ 온도에서 성장된 것을 특징으로 하는 전계 효과 트랜지스터 제조방법.Method for producing a field effect transistor, characterized in that grown at a temperature of 700 ℃ to 950 ℃. 제1항에 있어서,The method of claim 1, 상기 인산을 포함하는 식각제가,The etchant containing the phosphoric acid, 120℃ 내지 200℃의 온도인 것을 특징으로 하는 전계 효과 트랜지스터 제조방법.Method for producing a field effect transistor, characterized in that the temperature of 120 ℃ to 200 ℃. 제4항에 있어서,The method of claim 4, wherein 상기 산화막 및 상기 산화질화막을 식각하는 단계가,Etching the oxide film and the oxynitride film, 10분 내지 30분 동안 수행되는 것을 특징으로 하는 전계 효과 트랜지스터 제조방법.Method for producing a field effect transistor, characterized in that performed for 10 to 30 minutes.
KR1019960067622A 1996-12-18 1996-12-18 A method for fabricating MOSFET KR100265849B1 (en)

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