KR100283107B1 - Copper wiring formation method of semiconductor device - Google Patents

Copper wiring formation method of semiconductor device Download PDF

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KR100283107B1
KR100283107B1 KR1019980062752A KR19980062752A KR100283107B1 KR 100283107 B1 KR100283107 B1 KR 100283107B1 KR 1019980062752 A KR1019980062752 A KR 1019980062752A KR 19980062752 A KR19980062752 A KR 19980062752A KR 100283107 B1 KR100283107 B1 KR 100283107B1
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copper
layer
forming
seed layer
wiring
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KR1019980062752A
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KR20000046076A (en
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최경근
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

Abstract

본 발명은 반도체 소자의 구리(Cu) 배선 형성 방법에 관한 것으로, 비아홀 및 트렌치가 형성된 웨이퍼의 표면에 배리어 메탈층 및 구리 시드층을 형성하고, 급속 열 공정 처리하여 구리 시드층을 균일하고 조밀하게 하면서 핀홀이 없게 한 후, 비아홀 및 트렌치가 매립되도록 구리층을 형성하고, 화학적 기계적 연마 공정을 실시하여 비아홀 및 트렌치에 구리 플러그와 구리 배선을 형성하고, 구리 배선 상에 캡핑층을 형성하여 구리 배선을 완성시키므로써, 구리 시드층의 급속 열 공정 처리로 인해 이후에 형성되는 구리층의 구리 상이 (111)로 배향 성장되어 구리 배선의 신뢰성을 향상시킬 수 있는 반도체 소자의 구리 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a copper (Cu) wiring of a semiconductor device, wherein a barrier metal layer and a copper seed layer are formed on a surface of a wafer on which via holes and trenches are formed, and a rapid thermal process is performed to uniformly and densely form a copper seed layer. After removing the pinhole, the copper layer is formed to fill the via hole and the trench, and a chemical mechanical polishing process is performed to form the copper plug and the copper wiring in the via hole and the trench, and a capping layer is formed on the copper wiring to form the copper wiring. The present invention relates to a method for forming a copper wiring of a semiconductor device capable of improving the reliability of a copper wiring by oriented growth of the copper phase of a copper layer subsequently formed by (111) due to the rapid thermal process treatment of the copper seed layer. .

Description

반도체 소자의 구리 배선 형성 방법Copper wiring formation method of semiconductor device

본 발명은 반도체 소자의 구리(Cu) 배선 형성 방법에 관한 것으로, 특히 구리 시드층(seed layer)을 형성한 후에 급속 열 공정(Rapid Thermal Process; RTP) 처리하여 구리 시드층을 균일하고 조밀하게 하면서 핀홀이 없게하므로써, 구리 시드층상에 형성되는 구리층의 구리 상이 (111)로 배향 성장되어 구리 배선의 신뢰성을 향상시킬 수 있는 반도체 소자의 구리 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming copper (Cu) wiring of a semiconductor device, and in particular, after forming a copper seed layer, a rapid thermal process (RTP) treatment is performed to make the copper seed layer uniform and dense. The present invention relates to a method for forming a copper wiring of a semiconductor device in which the copper phase of the copper layer formed on the copper seed layer is oriented and grown to 111 to improve the reliability of the copper wiring.

일반적으로, 반도체 소자의 금속 배선으로 널리 사용하는 금속으로 알루미늄(Al), 알루미늄 합금 및 텅스텐(W) 등이 있다. 그러나, 이러한 금속들은 반도체 소자가 고집적화됨에 따라 낮은 융점과 높은 비저항으로 인하여 초고집적 반도체 소자에 더 이상 적용이 어렵게 되었다. 따라서, 금속배선의 대체 재료에 대한 개발 필요성이 대두되고 있는 실정이다. 대체 재료로 전도성이 우수한 물질인 구리(Cu), 금(Au), 은(Ag), 코발트(Co), 크롬(Cr), 니켈(Ni) 등이 있으며, 이러한 물질들 중 비저항이 낮고, 전자 이동(electromigration; EM)과 스트레스 이동(stress migration; SM) 등의 신뢰성이 우수하며, 생산원가가 저렴한 구리 및 구리 합금이 널리 적용되고 있는 추세이다.Generally, metals widely used as metal wirings of semiconductor devices include aluminum (Al), aluminum alloys, and tungsten (W). However, these metals are no longer applicable to ultra-high density semiconductor devices due to the low melting point and high resistivity as semiconductor devices are highly integrated. Therefore, there is a need for development of alternative materials for metal wiring. Alternative materials include copper (Cu), gold (Au), silver (Ag), cobalt (Co), chromium (Cr), and nickel (Ni), which are highly conductive materials. Copper and copper alloys with excellent reliability, such as electromigration (EM) and stress migration (SM), and low production costs are widely applied.

이러한 장점을 인해 반도체 소자 제조 공정시 금속 배선 및 플러그로 구리를 많이 사용한다. 구리를 사용하여 금속 배선 및 플러그를 형성함에 있어, 식각 공정을 실시하여야 하는데, 일반적인 식각 공정으로는 구리를 양호한 형상(profile)을 갖도록 식각하기 어려워 다마신(damascene) 공정을 적용하고 있다. 다마신 공정으로 구리층을 형성하는 방법은 전해도금(electroplating) 방법, 물질적 기상 증착(PVD) 방법, 화학적 기상 증착(CVD) 방법, 무전해 도금(electroless plating) 방법 등이 있다. 물리적 기상 증착 방법은 층덮힘이 불량하며, 무전해 도금 방법은 증착 속도가 매우 늦고 상용화된 장비가 없어 실제 사용이 어렵고, 화학적 기상 증착 방법은 구리 상이 (111) 및 (200) 등의 혼재된 상으로 증착되어 전자 이동의 신뢰성이 떨어지고, 증착 속도가 느리다는 단점이 있다. 따라서, 비아홀(또는 콘택홀)과 트렌치(trench)에 구리 시드층을 먼저 형성하고, 이후 구리 전해도금 방법으로 비아홀 및 트렌치를 매립하는 2단계 공정을 주로 적용하고 있다. 이 방법은 화학적 기상 증착 방법으로만 구리층을 형성하는 것보다 비용도 낮은 장점이 있다. 일반적으로 구리 시드층은 화학적 기상 증착이나 물리적 기상 증착 방법으로 형성하는데, 이후에 형성되는 구리층의 신뢰성은 구리 시드층의 형성 상태에 따라 좌우된다.Due to these advantages, copper is often used as a metal wire and a plug in a semiconductor device manufacturing process. In forming metal wires and plugs using copper, an etching process must be performed, and a damascene process is applied because it is difficult to etch copper to have a good profile. The copper layer may be formed by a damascene process using an electroplating method, a physical vapor deposition (PVD) method, a chemical vapor deposition (CVD) method, an electroless plating method, and the like. The physical vapor deposition method is poor in layer covering, and the electroless plating method is very difficult to use due to the very low deposition rate and the lack of commercialized equipment, and the chemical vapor deposition method is a mixed phase of copper phase (111) and (200). As a result of the deposition, the reliability of electron transfer is reduced, and the deposition rate is slow. Therefore, the copper seed layer is first formed in the via hole (or the contact hole) and the trench, and then a two-step process of filling the via hole and the trench by copper electroplating is mainly applied. This method has a lower cost than forming a copper layer only by chemical vapor deposition. In general, the copper seed layer is formed by chemical vapor deposition or physical vapor deposition, and the reliability of the copper layer formed thereafter depends on the formation state of the copper seed layer.

화학적 기상 증착이나 물리적 기상 증착 방법으로 형성된 구리 시드층은 그 상이 (111) 및 (200) 등의 혼재된 상태이며, 첨부된 도 1(b) 및 도 2에 나타난 바와 같이, 표면이 거칠고 핀홀(pin hole; 10)이 존재하고 있다. 이러한 상태에서 구리를 성장 시키면, 거친 표면과 핀홀(10)로 인하여 구리의 성장이 균일하지 않고 조밀하게 성장되지 못하며, 구리를 성장시켜 형성된 구리층은 그 상이 (111) 및 (200) 등이 혼재된 상으로 존재하게 되어 배선의 신뢰성을 저하시키는 문제가 있다.The copper seed layer formed by chemical vapor deposition or physical vapor deposition has a mixed state of (111) and (200), and the like, and as shown in FIGS. 1 (b) and 2, the surface is rough and pinholes ( pin hole; 10) exists. When the copper is grown in this state, the growth of copper is not uniform and densely grown due to the rough surface and the pinhole 10, and the copper layers formed by growing the copper have different (111) and (200) mixtures thereof. There exists a problem of being present in the phase which degrades the reliability of wiring.

따라서, 본 발명은 구리 시드층을 형성한 후에 급속 열 공정 처리하여 구리 시드층을 균일하고 조밀하게 하면서 핀홀이 없게하므로써, 구리 시드층상에 형성되는 구리층의 상이 우수한 (111) 우선 배향 방향으로 성장 되도록하여 구리 배선의 신뢰성을 향상시킬 수 있는 반도체 소자의 구리 배선 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention grows in the (111) preferred orientation in which the phase of the copper layer formed on the copper seed layer is excellent by forming a copper seed layer followed by a rapid thermal process to make the copper seed layer uniform and dense without pinholes. It is an object of the present invention to provide a method for forming a copper wiring of a semiconductor device that can improve the reliability of the copper wiring.

이러한 목적을 달성하기 위한 본 발명의 구리 배선 형성 방법은 비아홀 및 트렌치가 형성된 기판이 제공되는 단계; 상기 기판 표면에 배리어 메탈층을 형성하는 단계; 상기 배리어 메탈층상에 구리 시드층을 형성하고, 상기 구리 시드층을 급속 열 공정 처리하는 단계; 상기 비아홀 및 트렌치가 매립되도록 구리 전해도금 방법으로 상기 구리 시드층상에 구리층을 형성하는 단계; 화학적 기계적 연마 공정으로 구리층을 연마하여 상기 비아홀 및 트렌치에 구리 플러그와 구리 배선을 형성하는 단계; 및 상기 구리 배선 상에 캡핑층을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.Copper wiring forming method of the present invention for achieving the above object comprises the steps of providing a substrate having a via hole and a trench formed; Forming a barrier metal layer on the substrate surface; Forming a copper seed layer on the barrier metal layer and subjecting the copper seed layer to a rapid thermal process; Forming a copper layer on the copper seed layer by copper electroplating to fill the via holes and trenches; Polishing the copper layer by a chemical mechanical polishing process to form a copper plug and a copper wiring in the via hole and the trench; And forming a capping layer on the copper wiring.

도 1(a) 내지 도 1(f)는 본 발명의 실시예에 따른 반도체 소자의 구리 배선 형성 방법을 설명하기 위해 도시한 소자의 단면도.1 (a) to 1 (f) are cross-sectional views of a device for explaining a method of forming a copper wiring of a semiconductor device according to an embodiment of the present invention.

도 2는 구리 시드층을 형성한 후의 AFM 사진.2 is an AFM photograph after forming a copper seed layer.

도 3은 구리 시드층을 RTP 처리한 후의 AFM 사진.3 is an AFM photograph after RTP treatment of a copper seed layer.

〈도면의 주요 부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>

1: 기판 2: 도전층1: substrate 2: conductive layer

3: 층간 절연막 4: 비아홀 (또는 콘택홀)3: interlayer insulating film 4: via hole (or contact hole)

5: 트렌치 6: 배리어 메탈층5: trench 6: barrier metal layer

7: 구리 시드층 8: 구리층7: copper seed layer 8: copper layer

8A: 구리 배선 8B: 구리 플러그8A: copper wiring 8B: copper plug

9: 캡핑층 10: 핀홀9: capping layer 10: pinhole

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1(a) 내지 도 1(f)는 본 발명의 실시예에 따른 반도체 소자의 구리 배선 형성 방법을 설명하기 위해 도시한 소자의 단면도이고, 도 2는 구리 시드층을 형성한 후의 AFM(Atomic Force Microscope) 사진이며, 도 3은 구리 시드층을 RTP 처리한 후의 AFM 사진이다.1 (a) to 1 (f) are cross-sectional views of a device for explaining a method of forming a copper wiring of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is an AFM (Atomic) after forming a copper seed layer. Force Microscope) picture, Figure 3 is an AFM picture after the RTP treatment of the copper seed layer.

도 1(a)를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판(1)에 도전층(2)을 형성한다. 도전층(2)을 포함한 기판(1) 전체구조상에 층간 절연층(3)을 형성한다. 다마신 공정을 진행하기 위해 층간 절연층(3)에 비아홀 또는 콘택홀(4) 및 트렌치(5)를 형성한다.Referring to FIG. 1A, a conductive layer 2 is formed on a substrate 1 having a structure in which various elements for forming a semiconductor device are formed. An interlayer insulating layer 3 is formed on the entire structure of the substrate 1 including the conductive layer 2. In order to proceed with the damascene process, a via hole or a contact hole 4 and a trench 5 are formed in the interlayer insulating layer 3.

상기에서, 층간 절연층(3)은 저 유전 상수 값을 갖는 유전체 물질로 형성하거나 실리콘 산화물 예를 들어, 고밀도 플라즈마(HDP) 또는 스핀 온 글라스(SOG)를 증착하여 형성한다.In the above, the interlayer insulating layer 3 is formed of a dielectric material having a low dielectric constant value or by depositing silicon oxide, for example, high density plasma (HDP) or spin on glass (SOG).

도 1(b)를 참조하면, 비아홀(4) 및 트렌치(5)가 형성된 층간 절연층(3)의 표면에 배리어 메탈층(6)을 형성한다. 배리어 메탈층(6) 상에 구리를 전해도금하기 위한 구리 시드층(Cu seed layer; 7)을 형성시킨다.Referring to FIG. 1B, the barrier metal layer 6 is formed on the surface of the interlayer insulating layer 3 on which the via holes 4 and the trench 5 are formed. A copper seed layer 7 for electroplating copper is formed on the barrier metal layer 6.

상기에서, 배리어 메탈층(6)은 200 내지 500Å의 두께로 탄탈륨 나이트라이드(TaN)를 물리적 기상 증착 또는 화학적 기상 증착 방법으로 증착하여 형성되며, 이 배리어 메탈층(6)은 후에 형성되는 구리층으로부터의 구리 원자가 층간 절연층(3)으로 확산하는 것을 방지하는 역할을 한다. 구리 시드층(7)은 물리적 기상 증착 또는 화학 기상 증착 방법에 의해 200 내지 1000Å의 두께로 증착하여 형성시킨다. 이렇게 형성된 구리 시드층(7)은, 도 1(b) 도 2에 나타난 바와 같이, 그 상이 (111) 및 (200) 등의 혼재된 상태이며, 표면이 거칠고 조밀하지 않으며 핀홀(pin hole; 10)이 존재하고 있다. 이러한 상태에서 구리를 성장 시키면, 전술한 바와 같이, 거친 표면과 핀홀(10)로 인하여 구리의 성장이 균일하지 않고 조밀하게 성장되지 못하며, 구리를 성장시켜 형성된 구리층은 그 상이 (111) 및 (200) 등이 혼재된 상으로 존재하게 되어 배선의 신뢰성을 저하시킨다.In the above, the barrier metal layer 6 is formed by depositing tantalum nitride (TaN) in a thickness of 200 to 500 kPa by physical vapor deposition or chemical vapor deposition, and the barrier metal layer 6 is formed after the copper layer. Serves to prevent diffusion of copper atoms from the interlayer insulating layer 3. The copper seed layer 7 is formed by depositing a thickness of 200 to 1000 mm by physical vapor deposition or chemical vapor deposition. The copper seed layer 7 thus formed is in a mixed state, such as (111) and (200), as shown in FIG. 1 (b) and FIG. 2, and the surface is rough and not dense and has a pin hole; ) Exists. When copper is grown in such a state, as described above, the growth of copper is not uniform and densely grown due to the rough surface and the pinhole 10, and the copper layer formed by growing copper is different from the (111) and ( 200), etc., are present in a mixed phase, reducing the reliability of the wiring.

도 1(c)를 참조하면, 급속 열 공정 장비에서 300 내지 650℃의 온도, 질소(N2), 수소(H2) 또는 질소와 수소 혼합 가스(N2/H2) 분위기로 10 내지 300초 급속 열 공정 처리하여, 최초 형성된 구리 시드층(7)의 구리 원소를 표면 확산시켜 표면이 균일하고 조밀하면서 핀홀(10)이 없고, 또한 구리 원소의 배향성이 (111)으로 우선 배향된 새로운 구리 시드층(7)이 형성된다.Referring to FIG. 1 (c), 10 to 300 in a rapid thermal process equipment at a temperature of 300 to 650 ° C., nitrogen (N 2 ), hydrogen (H 2 ), or a nitrogen-hydrogen mixed gas (N 2 / H 2 ) atmosphere. The ultra-fast thermal process, surface-diffusion of the copper element of the initially formed copper seed layer 7 to make the surface uniform and dense, no pinholes 10, and the new copper whose orientation of the copper element is first oriented to (111). The seed layer 7 is formed.

도 1(d)를 참조하면, 비아홀 및 트렌치가 매립되도록 구리 전해도금 방법으로 구리층(8)을 형성한다.Referring to FIG. 1D, a copper layer 8 is formed by a copper electroplating method so that via holes and trenches are embedded.

도 1(e)를 참조하면, 화학적 기계적 연마 공정으로 구리층(8)을 연마하여, 비아홀(4) 및 트렌치(5)에 구리 플러그(8B)와 구리 배선(8A)을 형성한다.Referring to FIG. 1E, the copper layer 8 is polished by a chemical mechanical polishing process to form a copper plug 8B and a copper wiring 8A in the via hole 4 and the trench 5.

도 1(f)를 참조하면, 구리 배선(8A) 상에 캡핑층(capping layer; 9)을 형성하여 본 발명의 구리 배선(8A)을 완성시킨다.Referring to FIG. 1F, a capping layer 9 is formed on the copper wiring 8A to complete the copper wiring 8A of the present invention.

상기에서, 캡핑층(9)은 배리어 메탈층(6)과 동일한 물질을 증착하여 형성되며, 역할 또한 배리어 메탈층(6)과 동일하다.In the above, the capping layer 9 is formed by depositing the same material as the barrier metal layer 6, and also serves as the barrier metal layer 6.

상술한 바와 같이, 본 발명은 물리적 기상 증착 또는 화학적 기상 증착 방법으로 형성된 구리 시드층을 급속 열 공정 처리하여 균일하고 조밀하면서 핀홀이 없고, 또한 구리 원소의 배향성이 (111)으로 우선 배향된 구리 시드층으로 변화시키므로써, 이후에 구리 전해도금 방법으로 형성되는 구리층의 구리 상이 (111)로 배향 성장되어 구리 배선의 신뢰성을 향상시킬 수 있다.As described above, the present invention is a copper seed in which the copper seed layer formed by the physical vapor deposition or chemical vapor deposition method is subjected to a rapid thermal process to uniformly and densely pinhole free and the orientation of the copper element is first oriented to (111). By changing the layer, the copper phase of the copper layer formed by the copper electroplating method can be oriented and grown to (111) to improve the reliability of the copper wiring.

Claims (4)

비아홀 및 트렌치가 형성된 기판이 제공되는 단계;Providing a substrate on which via holes and trenches are formed; 상기 기판 표면에 배리어 메탈층을 형성하는 단계;Forming a barrier metal layer on the substrate surface; 상기 배리어 메탈층상에 구리 시드층을 형성하고, 상기 구리 시드층을 급속 열 공정 처리하는 단계;Forming a copper seed layer on the barrier metal layer and subjecting the copper seed layer to a rapid thermal process; 상기 비아홀 및 트렌치가 매립되도록 구리 전해도금 방법으로 상기 구리 시드층상에 구리층을 형성하는 단계;Forming a copper layer on the copper seed layer by copper electroplating to fill the via holes and trenches; 화학적 기계적 연마 공정으로 구리층을 연마하여 상기 비아홀 및 트렌치에 구리 플러그와 구리 배선을 형성하는 단계; 및Polishing the copper layer by a chemical mechanical polishing process to form a copper plug and a copper wiring in the via hole and the trench; And 상기 구리 배선 상에 캡핑층을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.And forming a capping layer on the copper wirings. 제 1 항에 있어서,The method of claim 1, 상기 배리어 메탈층 및 상기 캡핑층 각각은 탄탈륨 나이트라이드(TaN)를 증착하여 형성되는 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.Each of the barrier metal layer and the capping layer is formed by depositing tantalum nitride (TaN). 제 1 항에 있어서,The method of claim 1, 상기 구리 시드층은 물리적 기상 증착 방법 및 화학적 기상 증착 방법중 어느 하나의 방법으로 형성되는 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.And the copper seed layer is formed by any one of a physical vapor deposition method and a chemical vapor deposition method. 제 1 항에 있어서,The method of claim 1, 상기 급속 열 공정 처리는 급속 열 공정 장비에서 300 내지 650℃의 온도, 질소(N2), 수소(H2) 또는 질소와 수소 혼합 가스(N2/H2) 분위기로 10 내지 300초 실시하는 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The rapid thermal process is carried out in a rapid thermal process equipment at a temperature of 300 to 650 ℃, nitrogen (N 2 ), hydrogen (H 2 ) or nitrogen and hydrogen mixed gas (N 2 / H 2 ) atmosphere for 10 to 300 seconds A copper wiring forming method of a semiconductor device, characterized in that.
KR1019980062752A 1998-12-31 1998-12-31 Copper wiring formation method of semiconductor device KR100283107B1 (en)

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