KR100282988B1 - A manufacturing method of wires for a semicontuctor device - Google Patents

A manufacturing method of wires for a semicontuctor device Download PDF

Info

Publication number
KR100282988B1
KR100282988B1 KR1019990007158A KR19990007158A KR100282988B1 KR 100282988 B1 KR100282988 B1 KR 100282988B1 KR 1019990007158 A KR1019990007158 A KR 1019990007158A KR 19990007158 A KR19990007158 A KR 19990007158A KR 100282988 B1 KR100282988 B1 KR 100282988B1
Authority
KR
South Korea
Prior art keywords
insulating film
wiring
interlayer insulating
forming
metal
Prior art date
Application number
KR1019990007158A
Other languages
Korean (ko)
Other versions
KR20000059514A (en
Inventor
이동준
박영택
Original Assignee
황인길
아남반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 황인길, 아남반도체주식회사 filed Critical 황인길
Priority to KR1019990007158A priority Critical patent/KR100282988B1/en
Publication of KR20000059514A publication Critical patent/KR20000059514A/en
Application granted granted Critical
Publication of KR100282988B1 publication Critical patent/KR100282988B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

Abstract

텅스텐 등의 물질로 콘택이 형성되어 있는 폴리-금속간 절연막 위에 층간 절연막을 CVD 방법으로 10,000∼20,000Å 두께로 증착한 다음, 층간 절연막을 식각하여 배선이 형성될 부분에 콘택홀을 형성한다. 티타늄/질화 티타늄막을 스퍼터링 방식으로 증착하여 베리어층을 형성하고, 텅스텐, 몰리브덴, 니켈, 마그네슘, 금, 은 등의 금속막을 CVD 방법으로 증착하거나, 텅스텐, 알루미늄, 몰리브덴, 니켈, 금, 은 등의 액상 금속을 스핀 코팅 한 후, 경화시켜 금속막을 형성한다. 스핀 코팅시에는 회전축에 100∼1,000 KHz의 미세 진동을 적용하거나, 메가소닉 스프레이를 실시한다. 이후, 화학적·기계적 연마를 실시하여, 연마 이전의 층간 절연막의 두께의 10∼50% 정도, 약 3,000∼6,000Å의 두께가 감소되도록 하여 배선을 형성한다.An interlayer insulating film is deposited to a thickness of 10,000 to 20,000 Å by a CVD method on a poly-intermetal insulating film on which a contact is formed of a material such as tungsten, and then the interlayer insulating film is etched to form a contact hole in a portion where wiring is to be formed. The titanium / titanium nitride film is deposited by sputtering to form a barrier layer, and a metal film such as tungsten, molybdenum, nickel, magnesium, gold, and silver is deposited by CVD, or tungsten, aluminum, molybdenum, nickel, gold, silver, or the like. After spin coating the liquid metal, it is cured to form a metal film. At the time of spin coating, micro-vibration of 100 to 1,000 KHz is applied to the rotating shaft or megasonic spray is applied. Thereafter, chemical and mechanical polishing are performed to form a wiring such that a thickness of about 10 to 50% of the thickness of the interlayer insulating film before polishing and a thickness of about 3,000 to 6,000 kPa are reduced.

Description

반도체 소자의 배선 형성 방법{A MANUFACTURING METHOD OF WIRES FOR A SEMICONTUCTOR DEVICE}A wiring method of a semiconductor device {A MANUFACTURING METHOD OF WIRES FOR A SEMICONTUCTOR DEVICE}

본 발명은 반도체 소자의 배선을 형성하는 방법에 관한 것이다.The present invention relates to a method for forming wiring of a semiconductor element.

최근, 반도체 집적 회로가 고집적화됨에 따라 제한된 면적 내에 배선과 배선을 효과적으로 연결하는 방법들이 제시되고 있다. 그 중, 집적 회로에서의 배선을 다층화하는 다층 배선 방법이 주로 사용되고 있다. 다층 배선 방법에서는, 배선과 배선 사이에는 층간 절연막이 형성되고, 이 층간 절연막에 뚫려 있는 콘택을 통해서 두 배선이 접촉된다. 따라서, 반도체 소자 간에 배선이 통과하는 평면적 공간이 줄어들기 때문에 반도체 칩의 크기를 작게 가져갈 수 있다.Recently, as semiconductor integrated circuits are highly integrated, methods for effectively connecting wirings and wirings within a limited area have been proposed. Among them, a multilayer wiring method for multilayering wiring in an integrated circuit is mainly used. In the multilayer wiring method, an interlayer insulating film is formed between the wirings and the wirings, and the two wirings are contacted through the contacts drilled through the interlayer insulating film. Therefore, the size of the semiconductor chip can be reduced because the planar space through which the wiring passes between the semiconductor elements is reduced.

그러면, 첨부한 도면을 참고로 하여 종래의 기술에 따른 반도체 소자의 콘택 및 배선 형성 방법에 대하여 설명한다.Next, a method of forming a contact and a wiring of a semiconductor device according to the related art will be described with reference to the accompanying drawings.

도 1a 내지 도 1 f는 종래의 기술에 따른 반도체 소자의 콘택 및 배선 형성 방법을 공정 순서에 따라 도시한 단면도이다.1A to 1F are cross-sectional views illustrating a conventional method for forming a contact and wiring of a semiconductor device according to a process sequence.

도 1a에 도시한 바와 같이, 반도체 소자(도시하지 않음) 및 트랜치(도시하지 않음) 등이 형성되어 있는 규소 기판(10) 위에 규소 티타늄(TiSi) 등의 실리사이드 (silicide)막(20)을 형성하고, 그 위에 TEOS (thetraethyle orthosilicate)막, NSG (non-doped silicate glass)막, BPSG (borophosphosilicate glass) 등의 단일막 또는 이중막으로 구성된 폴리-금속 간 절연막(30)을 형성한 다음, 도 1b에서와 같이, 폴리-금속 간 절연막(30)을 식각하여 콘택홀(c)을 형성한다.As shown in FIG. 1A, a silicide film 20 such as silicon titanium (TiSi) is formed on a silicon substrate 10 on which semiconductor devices (not shown), trenches (not shown), and the like are formed. And a poly-metal interlayer insulating film 30 composed of a single film or a double film such as a tetraethyle orthosilicate (TEOS) film, a non-doped silicate glass (NSG) film, a borophosphosilicate glass (BPSG), and the like. As in, the poly-metal interlayer insulating film 30 is etched to form a contact hole (c).

도 1c에 도시한 바와 같이, 그 위에 티타늄(Ti) 또는 질화 티타늄(TiN)을 증착한 다음, 어닐링(annealing)하여 전기적 접촉 특성을 향상시키기 위한 오믹 접촉 금속층(40)을 형성한다.As shown in FIG. 1C, titanium (Ti) or titanium nitride (TiN) is deposited thereon and then annealed to form an ohmic contact metal layer 40 to improve electrical contact properties.

다음, 도 1d에 도시한 바와 같이, 화학 기상 증착 (chemical vapor deposition : CVD) 방식으로 텅스텐 등을 증착하여 플러그 형성을 위한 금속막(50)을 형성하고, 이 금속막(50)을 화학적·기계적 연마 혹은 배면 식각을 실시하여 도 1e에서와 같은 콘택 패턴(51)을 형성한다.Next, as illustrated in FIG. 1D, tungsten or the like is deposited by chemical vapor deposition (CVD) to form a metal film 50 for plug formation, and the metal film 50 is chemically and mechanically formed. Polishing or back etching is performed to form the contact pattern 51 as shown in FIG. 1E.

다음, 도 1f에 나타난 바와 같이, 배선을 위한 알루미늄(Al) 금속막을 증착하고 식각한 후, 클리닝(cleaning) 공정을 거쳐 배선(61)을 형성한다. 이 배선(61)은 콘택(51)을 통해 하부의 반도체 소자 등에 전기적으로 접속된다.Next, as shown in FIG. 1F, an aluminum (Al) metal film for wiring is deposited and etched, and then the wiring 61 is formed through a cleaning process. The wiring 61 is electrically connected to the lower semiconductor element or the like through the contact 51.

이러한 종래의 기술에 따른 반도체 소자의 배선 형성 방법에서는 브릿지(bridge)나 단락 등의 배선 식각 불량이 발생하기 쉽고, 식각 중에 폴리머(polymer)가 발생할 우려가 있다. 또한, 클리닝 시 또는 그 이후에 알루미늄 배선이 대기나 화학액 등의 외부 환경에 노출되므로 부식이나 배선 손실 등이 생길 수 있다.In the method of forming a wiring of a semiconductor device according to the related art, a wiring etch defect such as a bridge or a short circuit is likely to occur, and a polymer may be generated during etching. In addition, since the aluminum wiring is exposed to the external environment such as the atmosphere or the chemical liquid during or after cleaning, corrosion or wiring loss may occur.

종래의 기술이 가지는 문제점을 해결하기 위한 본 발명의 과제는 배선 식각시에 배선 간의 브릿지 및 단락 등과 같은 불량이 발생하는 것을 방지하는 반도체 소자의 배선 형성 방법을 제공하는 것이다.SUMMARY OF THE INVENTION An object of the present invention for solving the problems of the prior art is to provide a method for forming a wiring of a semiconductor device which prevents defects such as bridges and short circuits between wirings during wiring etching.

본 발명의 다른 과제는 배선 형성 시 폴리머가 형성되는 것을 막는 것이다.Another object of the present invention is to prevent the formation of a polymer when forming the wiring.

본 발명의 다른 과제는 외부 환경에 의한 배선의 부식이나 손실을 방지하는 것이다.Another object of the present invention is to prevent corrosion or loss of wiring by an external environment.

도 1a 내지 도 1f는 종래의 기술에 따른 반도체 소자의 배선 형성 방법을 공정 순서에 따라 나타낸 단면도이고,1A to 1F are cross-sectional views illustrating a method of forming a wiring of a semiconductor device according to the prior art, according to a process sequence;

도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 배선 형성 방법을 공정 순서에 따라 나타낸 단면도이다.2A through 2D are cross-sectional views illustrating a method of forming a wiring of a semiconductor device in accordance with an embodiment of the present invention, in the order of a process.

이러한 과제를 해결하기 위해서 본 발명에서는 콘택 금속부를 드러내는 콘택홀을 가지는 층간 절연막과 층간 절연막 상부에 형성된 금속막을 동시에 화학적·기계적 연마하여 갈아냄으로써, 콘택 금속부와 접속되는 배선을 형성한다.In order to solve this problem, in the present invention, an interlayer insulating film having a contact hole exposing a contact metal part and a metal film formed on the interlayer insulating film are simultaneously chemically and mechanically polished and ground to form a wiring connected to the contact metal part.

본 발명의 실시예에 따른 반도체 소자의 배선 형성 방법에서는 폴리-금속간 절연막 위에 제1 두께를 가지는 층간 절연막을 형성하고, 이 층간 절연막을 식각하여 배선을 형성하기 위한 콘택홀을 콘택 금속부가 드러나도록 형성한 다음, 층간 절연막 상부에 콘택홀을 통해 콘택 금속부와 연결되는 금속막을 형성한다. 이후, 금속막과 층간 절연막을 화학적·기계적 연마 방식으로 갈아내어 배선을 형성한다.In the method for forming a wiring of a semiconductor device according to an embodiment of the present invention, an interlayer insulating film having a first thickness is formed on the poly-intermetal insulating film, and the contact metal part is exposed to expose the contact hole for forming the wiring by etching the interlayer insulating film. Next, a metal film is formed on the interlayer insulating layer to be connected to the contact metal part through the contact hole. Thereafter, the metal film and the interlayer insulating film are ground by chemical and mechanical polishing to form wiring.

여기에서, 금속막은 화학 기상 증착 방식으로 증착할 수 있으며, 이 경우 텅스텐, 몰리브덴, 니켈, 마그네슘, 금 또는 은 등의 재료를 사용하는 것이 바람직하다.Here, the metal film can be deposited by chemical vapor deposition, in which case it is preferable to use a material such as tungsten, molybdenum, nickel, magnesium, gold or silver.

또한, 금속막은 액상 금속을 스핀 코팅하고 경화시켜 형성할 수 있는데, 스핀 코팅 시에 주파수 100∼1,000KHz 의 미세 진동을 적용하여 스핀 코팅이 잘 이루어지도록 하는 것이 바람직하다. 이 방법의 경우, 금속막의 재료로 알루미늄, 텅스텐, 몰리브덴, 니켈, 은 또는 금을 사용하는 것이 바람직하다.In addition, the metal film may be formed by spin coating and curing the liquid metal, and during spin coating, it is preferable to apply fine vibration with a frequency of 100 to 1,000 KHz to make the spin coating well. In this method, it is preferable to use aluminum, tungsten, molybdenum, nickel, silver or gold as the material of the metal film.

화학적·기계적 연마는 층간 절연막의 제1 두께의 10∼50% 정도, 즉 3,000∼6,000Å를 제거하는 것이 좋다.Chemical and mechanical polishing preferably removes about 10 to 50% of the first thickness of the interlayer insulating film, that is, 3,000 to 6,000 Pa.

또한, 층간 절연막은 화학 기상 증착 방법으로 형성할 수 있다.In addition, the interlayer insulating film can be formed by a chemical vapor deposition method.

이처럼, 반도체 소자의 배선을 화학적·기계적 연마 방식으로 형성하므로, 배선 간의 브릿지 및 단락 등의 결함을 방지할 수 있을 뿐만 아니라, 대기 또는 화학 약품 등에 의한 배선의 부식이나 손실을 최소화할 수 있다.As described above, since the wiring of the semiconductor element is formed by chemical and mechanical polishing, defects such as bridges and short circuits between the wirings can be prevented, and corrosion and loss of the wiring by air or chemicals can be minimized.

그러면, 첨부한 도면을 참고로 하여 본 발명의 실시예에 대하여 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 상세하게 설명한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 배선 형성 방법을 공정 순서에 따라 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a method of forming wirings of a semiconductor device in accordance with an embodiment of the present invention, according to a process sequence.

먼저, 도 1a 내지 도 1e에 도시한 바와 같은 방법으로 반도체 소자(도시하지 않음), 트랜치(도시하지 않음) 등이 형성되어 있는 규소 기판(10) 위에 실리사이드막(20), 폴리-금속간 절연막(32), 베리어층(41) 및 콘택 패턴(51)을 형성한다.First, the silicide film 20 and the poly-intermetallic insulating film on the silicon substrate 10 on which semiconductor elements (not shown), trenches (not shown), etc. are formed in the same manner as shown in FIGS. 1A to 1E. (32), barrier layer 41 and contact pattern 51 are formed.

다음, 도 2a에 도시한 바와 같이, 콘택 패턴(51) 및 폴리-금속 간 절연막(32) 위에 층간 절연 물질을 CVD 방법으로 10,000∼20,000Å 두께로 증착하여 층간 절연막(70)을 형성한다.Next, as shown in FIG. 2A, an interlayer insulating material is deposited on the contact pattern 51 and the poly-metal interlayer insulating film 32 to a thickness of 10,000 to 20,000 Å by CVD to form an interlayer insulating film 70.

도 2b에 도시한 바와 같이, 층간 절연막(70) 식각하여 배선을 형성하기 위한 콘택홀을 형성한다. 이때, 콘택홀을 통해 콘택 패턴(51) 또한 드러난다. 이러한 콘택홀이 뚫려 있는 층간 절연막(71)은 후속 배선 형성 공정에서 배선의 틀을 제공한다.As shown in FIG. 2B, the interlayer insulating layer 70 is etched to form contact holes for forming wiring. At this time, the contact pattern 51 is also exposed through the contact hole. The interlayer insulating film 71 through which such contact holes are drilled provides a wiring frame in a subsequent wiring forming process.

다음, 배선 및 콘택을 형성하기 위한 금속막을 CVD 방식으로 층간 절연막(71) 상부 및 콘택홀 안쪽으로 증착한다. 이때, 금속막은 텅스텐(W), 몰리브덴(Mo), 니켈(Ni), 마그네슘(Mg), 금(Au), 은(Ag) 등으로 형성한다.Next, a metal film for forming wirings and contacts is deposited on the interlayer insulating film 71 and into the contact holes by CVD. In this case, the metal film is formed of tungsten (W), molybdenum (Mo), nickel (Ni), magnesium (Mg), gold (Au), silver (Ag), or the like.

한편, 금속막은 텅스텐, 알루미늄, 몰리브덴, 니켈, 금, 은 등의 액상 금속을 이용하여 스핀 코팅(spin coating) 방식으로 형성할 수도 있는데, CVD 방식에서 사용되는 대부분의 금속이 그 재료로 사용될 수 있다. 스핀 코팅시, 액체 상태의 금속액이 용이하게 코팅되도록 하기 위해 회전축에 100∼1,000 KHz의 미세 진동(micro vibration)을 적용하거나, 메가소닉 스프레이(megasonic spray)를 실시한다. 이후, 열처리를 통해 코팅된 금속막을 경화시킨다.Meanwhile, the metal film may be formed by spin coating using liquid metals such as tungsten, aluminum, molybdenum, nickel, gold, and silver, and most metals used in the CVD method may be used as the material. . During spin coating, in order to easily coat the liquid metal liquid, 100 to 1,000 KHz of micro vibration is applied to the rotating shaft or a megasonic spray is performed. Thereafter, the coated metal film is cured through heat treatment.

이후, 화학적·기계적 연마(chemical-mecanical polishing:CMP)를 실시하여, 도 2c에 도시한 바와 같이, 층간 절연막(72)으로 측면이 둘러싸인 배선(62)을 형성한다. 이때, 화학적·기계적 연마는 연마 이전의 층간 절연막(도 2b의 도면부호 71)의 두께 5,000∼15,000Å의 10∼50% 정도, 약 3,000∼6,000Å의 두께가 감소되도록 충분히 연마하여, 층간 절연막(도 2b의 도면부호 71) 상부의 금속층과 베리어층은 제거하고, 콘택 안쪽에만 금속층 및 베리어층을 남긴다. 이 과정에서, 배선(62) 간에 발생하는 브릿지 및 단락이 제거된다.Subsequently, chemical-mechanical polishing (CMP) is performed to form the wiring 62 surrounded by the interlayer insulating film 72 as shown in FIG. 2C. At this time, the chemical and mechanical polishing is sufficiently polished so that the thickness of the interlayer insulating film (reference numeral 71 of FIG. 2B) before polishing is reduced by about 10 to 50% of the thickness of 5,000 to 15,000 kPa and about 3,000 to 6,000 kPa. 2b, the upper metal layer and the barrier layer are removed, leaving only the metal layer and the barrier layer inside the contact. In this process, bridges and short circuits occurring between the wirings 62 are eliminated.

다음, 도 2d에 도시한 바와 같이, 앞선 단계에서 형성된 배선(62)이 후속 공정에서 형성될 상부 배선과 분리되도록 10,000∼20,000Å 두께의 층간 절연막(80)을 더 형성한다.Next, as shown in FIG. 2D, an interlayer insulating film 80 of 10,000 to 20,000 Å thickness is further formed so that the wiring 62 formed in the previous step is separated from the upper wiring to be formed in a subsequent process.

이상에서와 같이, 본 발명에 따른 반도체 소자의 배선 형성 방법에서는 폴리-금속간 절연막 위에 배선을 형성하기 위한 콘택홀을 가지는 층간 절연막을 더 형성하고, 이를 화학적·기계적 연마 방식으로 충분히 갈아내는 방식으로 배선을 형성하기 때문에 배선 간의 브릿지 및 단락 등의 결함을 방지할 수 있고, 외부로 드러나는 배선의 면적이 좁아져 대기 또는 화학 약품 등에 의한 배선의 부식이나 손실을 최소화할 수 있다. 또한, 액상 금속을 스핀 코팅하여 금속막을 형성하는 경우, 콘택 부분에서의 보이드(void) 등의 결함을 제거할 수 있다.As described above, in the method for forming a wiring of a semiconductor device according to the present invention, an interlayer insulating film having a contact hole for forming a wiring is further formed on the poly-metal insulating film, and the method is sufficiently ground by chemical and mechanical polishing methods. Since the wiring is formed, defects such as bridges and short circuits between the wirings can be prevented, and the area of the wiring exposed to the outside becomes narrow, thereby minimizing corrosion or loss of the wiring due to air or chemicals. In addition, when forming a metal film by spin coating a liquid metal, defects such as voids and the like in the contact portion can be removed.

Claims (9)

규소 기판을 덮고 있으며 상기 규소 기판의 일부를 드러내는 콘택홀이 뚫려 있는 폴리-금속간 절연막, 및 상기 콘택홀 내에 형성되어 있는 콘택 금속부를 포함하는 반도체 소자에서,In a semiconductor device comprising a poly-intermetal insulating film covering a silicon substrate and a contact hole for exposing a portion of the silicon substrate, and a contact metal portion formed in the contact hole, 상기 폴리-금속간 절연막 위에 제1 두께를 가지는 층간 절연막을 형성하는 단계,Forming an interlayer insulating film having a first thickness on the poly-intermetal insulating film, 상기 층간 절연막을 식각하여 배선을 형성하기 위한 콘택홀을 상기 콘택 금속부가 드러나도록 형성하는 단계,Forming a contact hole for etching the interlayer insulating layer to expose the contact metal part; 상기 층간 절연막 상부에 상기 콘택홀을 통해 상기 콘택 금속부와 연결되는 금속막을 형성하는 단계, 및Forming a metal film on the interlayer insulating film to be connected to the contact metal part through the contact hole; and 상기 금속막과 상기 층간 절연막을 화학적·기계적 연마 방식으로 갈아내어 배선을 형성하는 단계를 포함하는 반도체 소자의 배선 형성 방법.And forming a wiring by grinding the metal film and the interlayer insulating film by chemical and mechanical polishing methods. 제1항에서,In claim 1, 상기 금속막은 화학 기상 증착 방식으로 증착하는 반도체 소자의 배선 형성 방법.And forming the metal film by chemical vapor deposition. 제2항에서,In claim 2, 상기 금속막은 텅스텐, 몰리브덴, 니켈, 마그네슘, 금 또는 은으로 형성하는 반도체 소자의 배선 형성 방법.And the metal film is formed of tungsten, molybdenum, nickel, magnesium, gold, or silver. 제1항에서,In claim 1, 상기 금속막을 형성하는 단계는,Forming the metal film, 액상 금속을 스핀 코팅하는 단계 및 경화시키는 단계를 포함하는 반도체 소자의 배선 형성 방법.A method of forming a wiring in a semiconductor device, comprising the step of spin coating and hardening a liquid metal. 제4항에서,In claim 4, 상기 스핀 코팅 시에 주파수 100∼1,000KHz 의 미세 진동을 적용하는 반도체 소자의 배선 형성 방법.A method for forming a wiring of a semiconductor device to which fine vibrations with a frequency of 100 to 1,000 KHz are applied during the spin coating. 제4항에서,In claim 4, 상기 금속막의 재료로 알루미늄, 텅스텐, 몰리브덴, 니켈, 은 또는 금을 사용하는 반도체 소자의 배선 형성 방법.A method for forming a wiring of a semiconductor device using aluminum, tungsten, molybdenum, nickel, silver or gold as the material of the metal film. 제1항에서,In claim 1, 상기 화학적·기계적 연마는 상기 층간 절연막의 상기 제1 두께의 10∼50%가 제거될 때까지 실시하는 반도체 소자의 배선 형성 방법.Wherein said chemical and mechanical polishing is performed until 10 to 50% of said first thickness of said interlayer insulating film is removed. 제1항에서,In claim 1, 상기 화학적·기계적 연마 시, 상기 층간 절연막의 상기 제1 두께를 3,000∼6,000Å를 제거하는 반도체 소자의 배선 형성 방법.A method for forming a wiring of a semiconductor device in which said first thickness of said interlayer insulating film is removed in the chemical and mechanical polishing process. 제1항에서,In claim 1, 상기 층간 절연막은 화학 기상 증착 방법으로 형성하는 반도체 소자의 배선 형성 방법.And the interlayer insulating film is formed by a chemical vapor deposition method.
KR1019990007158A 1999-03-04 1999-03-04 A manufacturing method of wires for a semicontuctor device KR100282988B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019990007158A KR100282988B1 (en) 1999-03-04 1999-03-04 A manufacturing method of wires for a semicontuctor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019990007158A KR100282988B1 (en) 1999-03-04 1999-03-04 A manufacturing method of wires for a semicontuctor device

Publications (2)

Publication Number Publication Date
KR20000059514A KR20000059514A (en) 2000-10-05
KR100282988B1 true KR100282988B1 (en) 2001-02-15

Family

ID=19575576

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019990007158A KR100282988B1 (en) 1999-03-04 1999-03-04 A manufacturing method of wires for a semicontuctor device

Country Status (1)

Country Link
KR (1) KR100282988B1 (en)

Also Published As

Publication number Publication date
KR20000059514A (en) 2000-10-05

Similar Documents

Publication Publication Date Title
KR100288496B1 (en) Method of forming a self-aligned copper diffusion barrier in vias
JP2000150521A (en) Integrated circuit
JPH11260917A (en) Barrier layer and its manufacture
US20060194426A1 (en) Method for manufacturing dual damascene structure with a trench formed first
TWI300244B (en) Uniform passivation method for conductive feature
US6677231B1 (en) Method for increasing adhesion ability of dielectric material in semiconductor
KR100282988B1 (en) A manufacturing method of wires for a semicontuctor device
KR100701375B1 (en) Method for fabricating metal line in a semiconductor
US20020127849A1 (en) Method of manufacturing dual damascene structure
KR19980063840A (en) How to Form a Buried Plug and Interconnect
KR100552815B1 (en) Method for fabricating the dual damascene interconnection in semiconductor device
WO2002054483A2 (en) A dual damascene integration scheme using a bilayer interlevel dielectric
US20060094245A1 (en) Methods of fabricating metal wiring in semiconductor devices
KR20000059515A (en) Forming methods of a contact and a wyre for a semicontuctor device
JPH11186274A (en) Dual damascene technique
KR20040029865A (en) Semiconductor device and fabrication method thereof
KR100467815B1 (en) Semiconductor device and fabrication method thereof
KR100450241B1 (en) Method for forming contact plug and semiconductor device has the plug
JP2000183061A (en) Manufacture of semiconductor device
JP2004072107A (en) Metallic wiring forming method for semiconductor element using deformed dual damascene process
KR100430680B1 (en) A metal line of semiconductor device and A method for forming of the same
KR100954685B1 (en) Method of forming metal line of semiconductor devices
KR20000056852A (en) Method of fabricating a metal-interconnect structure in integrated circuit
KR100307985B1 (en) A semiconductor device and a manufacturing process therefor
KR100546296B1 (en) Method of manufacturing metal line preventing metal bridge for semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20111121

Year of fee payment: 12

LAPS Lapse due to unpaid annual fee