KR100271627B1 - A memory cell structure exclusive of external refresh control - Google Patents

A memory cell structure exclusive of external refresh control Download PDF

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KR100271627B1
KR100271627B1 KR1019970037355A KR19970037355A KR100271627B1 KR 100271627 B1 KR100271627 B1 KR 100271627B1 KR 1019970037355 A KR1019970037355 A KR 1019970037355A KR 19970037355 A KR19970037355 A KR 19970037355A KR 100271627 B1 KR100271627 B1 KR 100271627B1
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refresh
word line
cell
bit line
data
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KR19990015322A (en
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최견규
전용원
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김영환
현대반도체주식회사
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells

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Abstract

PURPOSE: A memory cell structure is provided to improve a read/write speed of data and simply control the memory by performing in itself within the memory device a refresh operation performed by control of the outside . CONSTITUTION: A memory cell structure includes a row decoder(20) for driving a word line(WL). A cell array(21) has a plurality of cells at a cross point of the word line(WL) and a bit line(BL) and at a cross point of a refresh word line(RWL) and a refresh bit line(RBL). A sense amplifier(22) senses/amplifies data read from the cell array(21). An oscillator(23) generates a refresh RAS signal. An address generator(24) generates a refresh address depending on the refresh RAS signal from the oscillator(23). A refresh decoder(25) decodes the refresh address from the refresh address generator(23) to drive the refresh word line(RWL) depending on the refresh RAS signal. A refresh sense amplifier(26) senses/amplifies the cell data from the plurality of cells upon a refresh operation.

Description

외부 리프레쉬 제어가 필요없는 메모리셀 구조{A MEMORY CELL STRUCTURE EXCLUSIVE OF EXTERNAL REFRESH CONTROL}Memory cell structure that does not require external refresh control {A MEMORY CELL STRUCTURE EXCLUSIVE OF EXTERNAL REFRESH CONTROL}

본 발명은 외부로부터의 리프레쉬제어가 필요없는 디램(DRAM)의 셀 구조에 관한 것으로,특히, 데이터의 리드/라이트동작과는 무관하게 리프레쉬를 내부적으로 수행함으로써, 데이터의 리드/라이트속도를 향상시킬 수 있는 메모리셀 구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell structure of a DRAM that does not require external refresh control. In particular, the data read / write speed can be improved by performing the refresh internally regardless of the data read / write operation. It relates to a memory cell structure that can be.

도 1은 종래 DRAM의 셀 구조로서, 로우어드레스를 디코딩하여 워드라인(WL)을 구동하는 로우디코더(10)와, 워드라인(WL)과 비트라인(BL)의 교차점에 복수의 셀들이 위치하는 셀어레이(11)와, 셀어레이(11)의 셀들로부터 리드된 데이터를 증폭하는 센스앰프(12)로 구성된다.FIG. 1 is a cell structure of a conventional DRAM, in which a row decoder 10 for driving a word line WL by decoding a low address, and a plurality of cells are located at an intersection point of a word line WL and a bit line BL. It consists of a cell array 11 and a sense amplifier 12 for amplifying data read from the cells of the cell array 11.

이때, 상기 복수의 셀들은 동일한 구성을 가지며, 그 중에서 셀(11A)은 게이트는 워드라인(WLO),드레인은 비트라인(BL)에 접속된 엔모스트랜지스터(NM1)와, 그 엔모스트랜지스터(NM1)의 소스와 접지사이에 연결된 셀캐패시터(C1)로 구성된다.In this case, the plurality of cells have the same configuration, wherein the cell 11A has an NMOS transistor NM1 connected to a gate of a word line WLO and a drain of a bit line BL, and an NMOS transistor thereof. It consists of a cell capacitor C1 connected between the source of NM1 and ground.

이와같이 구성된 종래 DRAM의 셀 구조를 설명하면 다음과 같다.The cell structure of a conventional DRAM configured as described above is as follows.

먼저, 복수의 셀들중에서 셀(11A)이 선택되는 경우를 예로들어 설명한다.First, a case where the cell 11A is selected from among a plurality of cells will be described as an example.

리드동작시, 로우디코더(10)가 외부로부터 입력된 로우어드레스를 디코딩하여 워드라인(WL0)을 인에이블시키면, 셀(11A)의 엔모스트랜지스터(NM1)가 턴온된다.During the read operation, when the low decoder 10 decodes the low address input from the outside and enables the word line WL0, the n-MOS transistor NM1 of the cell 11A is turned on.

따라서, 셀캐패시터(C1)에 저장된 데이터가 전하공유(Charge Sharing)에 의해 비트라인(BL)에 실리고, 센스앰프(12)는 상기 비트라인(BL)에 실린 데이터를 증폭하여 데이터 버스라인(미도시)으로 출력한다.Accordingly, the data stored in the cell capacitor C1 is loaded on the bit line BL by charge sharing, and the sense amplifier 12 amplifies the data loaded on the bit line BL to prevent the data bus line (not shown). Will be displayed.

반면에 라이트동작시, 로우디코더(10)가 입력된 로우어드레스를 디코딩하여 워드라인(WL0)을 인에이블시키면, 엔모스트랜지스터(NM1)가 턴온된다.On the other hand, during the write operation, when the low decoder 10 decodes the input low address and enables the word line WL0, the nMOS transistor NM1 is turned on.

따라서, 데이터 버스라인(미도시)을 통하여 입력된 데이터는 센스앰프(12)에서 증폭된 후, 상기 턴온된 엔모스트랜지스터(NM1)를 통하여 셀캐패시터(C1)에 저장된다.Accordingly, the data input through the data bus line (not shown) is amplified by the sense amplifier 12 and then stored in the cell capacitor C1 through the turned-on nMOS transistor NM1.

그런데, 상기와 같이 셀이 하나의 엔모스트랜지스터와 하나의 셀캐패시터로 이루어진 메모리셀 구조에서, 셀캐패시터(C1)에 저장된 데이터는 누설전류(Leakage Current)형태로 외부로 소멸된다. 따라서, DRAM에서는 셀데이터를 보존하기 위하여 셀데이타를 주기적으로 리프레쉬시켜주어야 한다.However, as described above, in the memory cell structure in which a cell includes one NMOS transistor and one cell capacitor, data stored in the cell capacitor C1 is extinguished to the outside in the form of a leakage current. Therefore, in DRAM, the cell data must be refreshed periodically to preserve the cell data.

즉, 외부로부터 리프레쉬용 로우어드레스와 리프레쉬제어신호를 주기적으로 발생시키면, 그 리프레쉬 제어신호에 따라 로우디코더(10)가 리프레쉬용 로우어드레스를 디코딩하여 순차적으로 워드라인을 인에이블시킴으로써 리프레쉬동작이 수행되며, 보통 데이터의 리드동작과 동일하다.That is, when the refresh low address and the refresh control signal are periodically generated from the outside, the refresh operation is performed by the low decoder 10 decoding the refresh low addresses and enabling word lines sequentially according to the refresh control signal. This is the same as the normal data read operation.

그리고, 리프레쉬동작은 데이터의 리드/라이트동작중에 이루어지며, 보통 주기적으로 리드/라이트동작 →리프레쉬 →리드/라이트동작과 같은 패턴을 갖는다.The refresh operation is performed during the read / write operation of data, and usually has a pattern such as read / write operation → refresh → read / write operation periodically.

따라서, 종래 DRAM의 셀 구조에서 리프레쉬동작은 리드/라이트동작과 병행하여 이루어지기 때문에, 리프레쉬동작에 의해 데이터의 리드/라이트동작이 그만큼 늦어지는 문제점이 발생된다.Therefore, in the conventional DRAM cell structure, since the refresh operation is performed in parallel with the read / write operation, a problem arises in that the read / write operation of data is delayed by the refresh operation.

따라서, 본 발명의 목적은, 외부의 제어에 의해 수행되는 리프레쉬동작을 메모리소자의 내부에서 자체적으로 수행함으로써, 데이터의 리드/라이트속도를 향상시키고 간단하게 메모리를 제어할 수 있는 메모리셀 구조를 제공하는데 있다.Accordingly, an object of the present invention is to provide a memory cell structure capable of improving the read / write speed of data and controlling the memory simply by performing a refresh operation performed by an external control in the memory element itself. It is.

상기와 같은 목적을 달성하기 위하여 본 발명은, 워드라인과 비트라인의 교차점 및 리프레쉬 워드라인과 리프레쉬 비트라인의 교차점에 복수의 셀들이 위치하는 셀어레이와; 일정시간마다 리프레쉬 RAS(Row Address Strobe)신호를 발생하는 오실레이터와; 상기 오실레이터에서 출력된 리프레쉬 RAS신호를 카운트하여 리프레쉬 어드레스를 발생하는 리프레쉬 어드레스 발생기와; 상기 오실레이터에서 출력된 리프레쉬 RAS신호에 따라, 상기 리프레쉬 어드레스 발생기에서 출력된 리프레쉬 어드레스를 디코딩하여 리프레쉬 워드라인을 구동하는 리프레쉬 디코더와; 리프레쉬동작시 복수의 셀로부터 출력된 셀데이타를 감지하여 증폭하는 리프레쉬 센스앰프를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a cell array including a plurality of cells located at an intersection point of a word line and a bit line and an intersection point of a refresh word line and a refresh bit line; An oscillator for generating a refresh RAS (Row Address Strobe) signal at a predetermined time; A refresh address generator for generating a refresh address by counting a refresh RAS signal output from the oscillator; A refresh decoder for decoding a refresh address output from the refresh address generator and driving a refresh word line according to the refresh RAS signal output from the oscillator; And a refresh sense amplifier for sensing and amplifying the cell data output from the plurality of cells during the refresh operation.

도 1은 종래 메모리셀 구조의 개략도.1 is a schematic diagram of a conventional memory cell structure.

도 2는 본 발명에 의한 외부 리프레쉬 제어가 필요없는 메모리셀 구조.2 is a memory cell structure requiring no external refresh control according to the present invention.

***** 도면의주요부분에대한부호설명********** Symbol description for main parts of drawing *****

20 : 로우디코더 21 : 셀어레이20: Low Decoder 21: Cell Array

22 : 센스앰프 23 : 오실레이터22: sense amplifier 23: oscillator

24 : 리프레쉬 어드레스 발생기 25 : 리프레쉬 디코더24: refresh address generator 25: refresh decoder

26 : 리프레쉬 센스앰프 RWL : 리프레쉬 워드라인26: Refresh Sense Amplifier RWL: Refresh Word Line

RBL : 리프레쉬 비트라인RBL: Refresh Bitline

본 발명의 기술에 의한 메모리셀 구조는 도 2에 도시된 바와같이, 워드라인(WL)을 구동하는 로우디코더(20)와, 워드라인(WL)과 비트라인(BL)의 교차점 및 리프레쉬 워드라인(RWL)과 리프레쉬 비트라인(RBL)의 교차점에 복수의 셀들이 위치하는 셀어레이(21)와, 셀어레이(21)로부터 리드된 데이터를 감지하여 증폭하는 센스앰프(22)와, 리프레쉬 RAS신호를 발생하는 오실레이터(23)와, 그 오실레이터(23)에서 발생된 리프레쉬 RAS신호에 따라, 리프레쉬 어드레스를 발생하는 리프레쉬 어드레스 발생기(24)와, 상기 리프레쉬 RAS신호에 따라, 상기 리프레쉬 어드레스 발생기(23)에서 출력된 리프레쉬 어드레스를 디코딩하여 리프레쉬 워드라인(RWL)을 구동하는 리프레쉬 디코더(25)와, 리프레쉬동작시 상기 복수의 셀로부터 출력된 셀데이타를 감지하여 증폭하는 리프레쉬 센스앰프(26)로 구성된다.As shown in FIG. 2, the memory cell structure according to the present inventive concept has a row decoder 20 for driving a word line WL, an intersection point between a word line WL and a bit line BL, and a refresh word line. A cell array 21 in which a plurality of cells are located at an intersection point of the RWLL and the refresh bit line RBL, a sense amplifier 22 that senses and amplifies data read from the cell array 21, and a refresh RAS signal. The oscillator 23 for generating a signal, the refresh address generator 24 for generating a refresh address in accordance with the refresh RAS signal generated by the oscillator 23, and the refresh address generator 23 in accordance with the refresh RAS signal. A refresh decoder 25 that decodes the refresh address outputted from the NCR to drive the refresh word line RWL, and a refresh sensor that senses and amplifies cell data output from the plurality of cells during the refresh operation. It consists of the amplifier 26.

상기 복수의 셀들은 구성이 동일하며, 그 중에서 셀(21A)은 게이트는 워드라인(WL0), 드레인은 비트라인(BL)에 접속된 엔모스트랜지스터(NM1)와, 소스는 엔모스트랜지스터(NM1의 소스, 게이트는 리프레쉬 워드라인(RWL0), 드레인은 리프레쉬 비트라인(RBL)에 접속된 엔모스트랜지스터(NM2)와, 상기 엔모스트랜지스터(NM1),(NM2)의 소스에 병렬연결된 셀캐패시터(C1)로 구성된다.The plurality of cells have the same configuration, wherein cell 21A has an MOS transistor NM1 connected to a gate of word line WL0, a drain of bit line BL, and a source of MOS transistor NM1. The NMOS transistor NM2 connected to the source and gate of the refresh word line RWL0 and the drain thereof is connected to the refresh bit line RBL, and a cell capacitor connected in parallel to the sources of the NMOS transistors NM2 and NM2. C1).

이와같이 구성된 본 발명의 기술에 의한 메모리셀 구조를 첨부된 도면을 참조하여 설명하면 다음과 같다.Referring to the accompanying drawings, a memory cell structure according to the present invention configured as described above is as follows.

먼저, 데이터의 리드/라이트동작은 종래와 동일하게 이루어진다.First, the read / write operation of data is performed in the same manner as in the prior art.

즉, 리드동작시, 로우디코더(20)는 입력된 로우어드레스를 디코딩하여, 복수의 워드라인(WL)중에서 워드라인(WL0)을 인에이블시키면, 셀(21A)내의 엔모스트랜지스터(NM1)가 턴온된다.That is, during the read operation, the low decoder 20 decodes the input low address and enables the word line WL0 among the plurality of word lines WL, whereby the enMOS transistor NM1 in the cell 21A is turned on. Is turned on.

따라서, 셀캐패시터(C1)에 저장된 데이터가 전하공유(Charge Sharing)에 의해 비트라인(BL)에 실리고, 센스앰프(22)는 비트라인(BL)에 실린 데이터를 증폭한 후 데이터 버스라인(미도시)으로 출력한다.Therefore, the data stored in the cell capacitor C1 is loaded on the bit line BL by charge sharing, and the sense amplifier 22 amplifies the data loaded on the bit line BL and then the data bus line (not shown). Will be displayed.

반면에, 데이터의 라이트동작시, 로우디코더(20)가 입력된 로우어드레스를 디코딩하여 워드라인(WL0)을 인에이블시키면, 엔모스트랜지스터(NM1)가 턴온된다.On the other hand, in the data write operation, when the low decoder 20 decodes the input low address and enables the word line WL0, the nMOS transistor NM1 is turned on.

따라서, 데이터 버스라인(미도시)을 통하여 입력된 데이터는 센스앰프(22)에서 증폭된 후, 상기 턴온된 엔모스트랜지스터(NM1)를 통하여 셀캐패시터(C1)에 저장된다.Therefore, the data input through the data bus line (not shown) is amplified by the sense amplifier 22 and then stored in the cell capacitor C1 through the turned-on nMOS transistor NM1.

그런데, 리프레쉬동작은 상기 데이터의 리드/라이트동작과는 무관하게 이루어진다.However, the refresh operation is performed irrespective of the read / write operation of the data.

즉, 리프레쉬동작시, 오실레이터(23)는 리프레쉬 RAS신호를 출력하고, 카운터역할을 하는 리프레쉬 어드레스 발생기(24)는 상기 리프레쉬 RAS신호를 카운트하여 리프레쉬 어드레스를 발생한다.That is, in the refresh operation, the oscillator 23 outputs the refresh RAS signal, and the refresh address generator 24 serving as a counter counts the refresh RAS signal to generate a refresh address.

이어서, 리프레쉬 디코더(25)는 상기 오실레이터(23)에서 출력된 리프레쉬 RAS신호에 의해 인에블되어, 리프레쉬 어드레스 발생기(24)에서 출력된 리프레쉬 어드레스를 디코딩하여 복수의 리프레쉬 워드라인(RWL0,RWL1,..,RWln)들을 구동함으로써, 리프레쉬동작을 수행한다.Then, the refresh decoder 25 is enabled by the refresh RAS signal output from the oscillator 23, and decodes the refresh addresses output from the refresh address generator 24 so that a plurality of refresh word lines RWL0, RWL1, By driving RWln), the refresh operation is performed.

예를들어, 리프레쉬 디코더(25)가 리프레쉬 워드라인(RWL0)을 구동한다고 가정하면, 셀(21A)내의 엔모스트랜지스터(NM2)가 턴온되어, 셀캐패시터(C1)에 저장된 데이터는 리프레쉬 비트라인(RBL)에 실리게 된다.For example, assuming that the refresh decoder 25 drives the refresh word line RWL0, the NMOS transistor NM2 in the cell 21A is turned on, so that the data stored in the cell capacitor C1 is refreshed with the refresh bit line. RBL).

따라서, 리프레쉬 비트라인(RBL)에 실린 셀데이터는 리프레쉬 센스앰프(26)에서 증폭되며, 그 후 증폭된 데이터는 리프레쉬 비트라인(RBL)과 턴온된 엔모스트랜지스터(NM2)를 통하여 다시 셀캐패시터(C1)에 저장됨으로써, 리프레쉬 동작을 완료한다. 그리고, 리프레쉬 디코더(25)가 리프레쉬 워드라인(RWL1,..,RWLn)을 구동하는 경우에도 리프레쉬동작은 동일하게 이루어진다.Accordingly, the cell data loaded on the refresh bit line RBL is amplified by the refresh sense amplifier 26, and then the amplified data is again restored through the refresh bit line RBL and the turned-on NMOS transistor NM2. By storing in C1), the refresh operation is completed. The refresh operation is the same even when the refresh decoder 25 drives the refresh word lines RWL1, ..., RWLn.

즉, 본 발명은 데이터의 리드/라이트동작중에, 외부로부터 리프레쉬용 로우어드레스와 리프레쉬제어신호를 주기적으로 발생시켜 리프레쉬동작을 수행하지 않고, 리드/라이트동작과는 무관하게 내부적으로 리프레쉬동작을 수행한다.That is, the present invention periodically generates a refresh low address and a refresh control signal from the outside during the data read / write operation, and does not perform the refresh operation, and performs the internal refresh operation independently of the read / write operation. .

또한, 상기 실시예는 단지 한 예로서 청구범위를 한정하지 않으며, 여러가지의 대안, 수정 및 변경들이 통상의 지식을 갖춘자에게 자명한 것이 될 것이다.In addition, the above embodiments are not limited by the claims as an example only, and various alternatives, modifications, and changes will be apparent to those skilled in the art.

상기에서 상세히 설명한 바와같이, 본 발명은 리드/라이트동작중에 외부로부터 입력된 리프레쉬용 로우어드레스와 리프레쉬제어신호에 따라 주기적으로 리프레쉬동작을 수행하지 않고, 리드/라이트동작과는 무관하게 내부적으로 리프레쉬동작을 수행함으로써, 데이터의 리드/라이트속도를 향상시킴은 물론 메모리제어를 간단하게 수행할 수 있는 효과가 있다.As described in detail above, the present invention does not periodically perform the refresh operation according to the refresh low address and the refresh control signal input from the outside during the read / write operation, and performs the internal refresh operation independently of the read / write operation. By doing this, the read / write speed of the data can be improved and the memory control can be easily performed.

Claims (2)

워드라인과 비트라인의 교차점 및 리프레쉬 워드라인과 리프레쉬 비트라인의 교차점에 복수의 셀들이 위치하는 셀어레이(21)와;A cell array 21 in which a plurality of cells are positioned at the intersection of the word line and the bit line and the intersection of the refresh word line and the refresh bit line; 일정시간마다 리프레쉬 RAS신호를 발생하는 오실레이터(23)와;An oscillator 23 for generating a refresh RAS signal every predetermined time; 상기 오실레이터(23)에서 출력된 리프레쉬 RAS신호를 카운트하여 리프레쉬 어드레스를 발생하는 리프레쉬 어드레스 발생기(24)와;A refresh address generator 24 which counts the refresh RAS signals output from the oscillator 23 and generates a refresh address; 상기 오실레이터(23)에서 출력된 리프레쉬 RAS신호에 따라, 상기 리프레쉬 어드레스 발생기(24)에서 출력된 리프레쉬 어드레스를 디코딩하여 상기 셀어레이(21)의 리프레쉬 워드라인을 구동하는 리프레쉬 디코더(25)와;A refresh decoder 25 for decoding the refresh address output from the refresh address generator 24 and driving the refresh word line of the cell array 21 according to the refresh RAS signal output from the oscillator 23; 리프레쉬동작시 상기 셀어레이(21)의 복수의 셀로부터 출력된 셀데이터를 감지하여 증폭하는 리프레쉬 센스앰프(26)로 구성된 것을 특징으로 하는 메모리셀 구조.And a refresh sense amplifier (26) for sensing and amplifying cell data output from a plurality of cells of the cell array (21) during a refresh operation. 제1항에 있어서, 상기 셀어레이(21)의 복수의 셀은 게이트는 워드라인, 드레인은 비트라인에 접속된 제1 엔모스트랜지스터와, 소스는 상기 제1엔모스트랜지스터의 소스, 게이트는 리프레쉬 워드라인(RWL), 드레인은 리프레쉬 비트라인(RBL)에 접속된 제2 엔모스트랜지스터와, 상기 제1,제2엔모스트랜지스터의 소스에 병렬연결된 셀캐패시터(C1)로 구성된 것을 특징으로 하는 메모리셀 구조.2. The cell of claim 1, wherein the plurality of cells of the cell array 21 has a first NMOS transistor connected with a gate of a word line and a drain of a bit line, a source of the first NMOS transistor, and a gate of the first NMOS transistor. The word line RWL and the drain may include a second NMOS transistor connected to the refresh bit line RBL, and a cell capacitor C1 connected in parallel to the sources of the first and second NMOS transistors. Cell structure.
KR1019970037355A 1997-08-05 1997-08-05 A memory cell structure exclusive of external refresh control KR100271627B1 (en)

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