KR100265361B1 - Method for improving etching selectivity of photoresist - Google Patents

Method for improving etching selectivity of photoresist Download PDF

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KR100265361B1
KR100265361B1 KR1019970072812A KR19970072812A KR100265361B1 KR 100265361 B1 KR100265361 B1 KR 100265361B1 KR 1019970072812 A KR1019970072812 A KR 1019970072812A KR 19970072812 A KR19970072812 A KR 19970072812A KR 100265361 B1 KR100265361 B1 KR 100265361B1
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photoresist
etching
photoresist pattern
semiconductor device
pattern
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KR1019970072812A
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KR19990053211A (en
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강수진
오세영
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0275—Photolithographic processes using lasers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Optics & Photonics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)

Abstract

PURPOSE: A method for improving an etching selection ratio of a photoresist is provided to increase the stability of a manufacturing process by improving an etching selection ratio of a photoresist to an etching object layer. CONSTITUTION: A photoresist is coated on an upper portion of an etching object layer(11). An exposure process for the photoresist is selectively performed. A developing process for the photoresist is performed. A photoresist pattern(13) is formed by performing the exposure process and the developing process. An excimer laser exposure process is performed. A heat treatment is performed to increase a hardness of the photoresist pattern(13). The etching object layer(11) is etched selectively by using the photoresist pattern(13) as an etching mask.

Description

포토레지스트의 식각 선택비 개선방법How to improve the etching selectivity of photoresist

본 발명은 반도체 제조 분야에 관한 것으로, 특히 리소그래피 공정시 식각 대상층에 대한 포토레지스트의 식각 선택비를 개선하는 방법에 관한 것이다.TECHNICAL FIELD The present invention relates to the field of semiconductor manufacturing, and more particularly, to a method of improving the etching selectivity of a photoresist with respect to an etching target layer in a lithography process.

반도체 장치의 고집적화에 따라 포토레지스트를 사용하여 각종 패턴을 디파인하기 위한 사진 및 식각 공정은 반도체 장치의 집적도 및 성능을 결정하는 요소로서 자리잡게 되었다.BACKGROUND With the increasing integration of semiconductor devices, photolithography and etching processes for defining various patterns using photoresists have become a factor in determining the integration and performance of semiconductor devices.

i-라인 포토레지스트의 해상도 한계(0.25㎛)에 따라 64M DRAM급 이상의 고집적 반도체 장치에서는 원자외선(DUV) 포토레지스트 리소그래피 공정이 도입되고 있다. 그런데, 원자외선 포토레지스트 패턴을 식각 마스크로 사용하는 식각 공정시 식각 대상층에 대한 포토레지스트 패턴의 식각 선택비 특성이 i-라인 메커니즘에 비해 떨어지는 문제점이 있었다.Due to the resolution limit (0.25 mu m) of i-line photoresist, deep ultraviolet (DUV) photoresist lithography processes are being introduced in 64M DRAM or higher integrated semiconductor devices. However, in the etching process using the far ultraviolet photoresist pattern as an etching mask, the etching selectivity characteristic of the photoresist pattern with respect to the etching target layer is inferior to that of the i-line mechanism.

원자외선 포토레지스트를 이용한 식각 공정시 포토레지스트 패턴의 식각 속도를 '1'로 할 때, 각 식각 대상층(기판)의 식각 선택비는 실리콘 산화막(콘택홀 공정)에서 2.2∼2.5, 폴리실리콘막은 1.8 정도, 금속막은 1.1 정도를 나타낸다. 이처럼 원자외선 포토레지스트 패턴의 식각 선택비 특성이 열악한 관계로 포토레지스트 패턴을 0.78㎛ ∼ 1.2㎛의 두께로 두껍게 코팅하여 사용하고 있다.When the etching rate of the photoresist pattern is set to '1' in the etching process using the far-infrared photoresist, the etching selectivity of each etching target layer (substrate) is 2.2 to 2.5 in the silicon oxide film (contact hole process) and 1.8 for the polysilicon film. The degree and the metal film represent about 1.1. Since the etching selectivity characteristics of the far-infrared photoresist pattern are poor, the photoresist pattern is thickly coated to a thickness of 0.78 μm to 1.2 μm.

이처럼 두꺼운 두께의 포토레지스트를 사용할 경우, 포토레지스트의 소비량 증가를 차제하더라도 포토레지스트 패턴의 쓰러짐 현상 및 패턴의 균일도 저하(웨이퍼 전체 또는 단위 공정에 투입되는 25장의 웨이퍼에서 패턴 크기의 균일도가 저하됨) 등의 문제가 대두된다. 또한, 이와 같은 문제점은 반도체 장치의 고집적화 따른 패턴의 미세화 및 단차비(aspect ratio)의 증가에 따라 더욱 심각한 문제점을 유발한다.In the case of using such a thick photoresist, even if the consumption of the photoresist is subtracted, the photoresist pattern collapses and the pattern uniformity decreases (the uniformity of the pattern size is reduced on the entire wafer or 25 wafers inserted into the unit process). The problem arises. In addition, such a problem causes a more serious problem as the pattern becomes smaller and the aspect ratio increases due to the higher integration of the semiconductor device.

본 발명은 포토레지스트의 두께를 증가시키지 않으면서 식각 대상층에 대한 포토레지스트의 식각 선택비 특성을 개선하여 사진 및 식각 공정의 안정성과 공정 마진을 개선하는 반도체 장치 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device which improves the stability and process margin of a photo and etching process by improving the etching selectivity characteristics of the photoresist with respect to an etching target layer without increasing the thickness of the photoresist.

도 1a 내지 도 1d는 본 발명의 일실시예에 따른 반도체 장치의 미세 패턴 형성 공정도.1A to 1D are diagrams illustrating a fine pattern forming process of a semiconductor device according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

10 : 실리콘 기판 11 : 식각 대상층10 silicon substrate 11 etching target layer

12 : 원자외선 포토레지스트 13 : 포토레지스트 패턴12: far ultraviolet photoresist 13: photoresist pattern

14 : 미세 패턴 20 : 포토마스크14: fine pattern 20: photomask

포토레지스트의 식각 선택비 특성을 개선하기 위해서는 포토레지스트의 물리적 성질을 개선시켜야 한다. 원자외선 포토레지스트는 유기 용제, 강산 발산제, 고분자 수지, 첨가제 등의 복합물질이다. 고분자 수지는 폴리하이드록시 스틸렌 수지에 25∼30%의 용해억제 기능기가 부착되어 있다. 폴리하이드록시 스틸렌 수지에 용해억제 기능기가 부착되면, 폴리 하이드록시 스틸렌 고유의 물성이 변화된다. 즉, 용해억제 기능기가 부착되면 고분자 수지의 유리전이 온도(glass transition temperature)가 감소하게 되고 고분자 수지의 경도가 감소하게 되어 결과적으로, 활성화된 화학물질과 물리적 충격에 대한 내성이 감소된다. 즉, 식각 선택비 특성이 저하된다. 본 발명에 따라 고분자 수지에 부착된 용해억제 기능기를 빛을 사용하여 탈기시키면 고분자 수지의 유리전이 온도가 다시 증가하게 되고, 폴리 하이드록시 스틸렌 수지의 경도가 증가하게 된다. 결국, 고분자 수지의 화학적 내성이 증가하게 되며, 폴리 하이드록시 스틸렌 수지 경도의 증가는 화학물질과 물리적 충격에 대한 포토레지스트의 내성 증가를 유발하며, 이를 통해 포토레지스트의 식각 선택비 특성을 개선할 수 있다.In order to improve the etching selectivity characteristics of the photoresist, it is necessary to improve the physical properties of the photoresist. The far ultraviolet photoresist is a composite material such as an organic solvent, a strong acid dispersant, a polymer resin, and an additive. The polymer resin has a 25-30% dissolution inhibiting functional group attached to the polyhydroxy styrene resin. When the dissolution inhibiting functional group is attached to the polyhydroxy styrene resin, the physical properties inherent to the polyhydroxy styrene are changed. That is, when the dissolution inhibiting functional group is attached, the glass transition temperature of the polymer resin is reduced and the hardness of the polymer resin is reduced, resulting in reduced resistance to activated chemicals and physical impact. That is, the etching selectivity characteristic is lowered. Degassing the dissolution inhibiting functional group attached to the polymer resin according to the present invention by using light to increase the glass transition temperature of the polymer resin again, the hardness of the poly hydroxy styrene resin is increased. As a result, the chemical resistance of the polymer resin is increased, and the increase in the hardness of the polyhydroxy styrene resin causes an increase in the resistance of the photoresist to chemicals and physical impact, thereby improving the etch selectivity characteristics of the photoresist. have.

상술한 본 발명의 기술적 원리로부터 제공되는 특징적인 반도체 장치 제조방법은 소정의 식각 대상층 상부에 포토레지스트를 코팅하는 제1 단계; 상기 포토레지스트를 선택적으로 노광하고, 현상하여 포토레지스트 패턴을 형성하는 제2 단계; 엑시머 레이저 전면 노광을 실시하는 제3 단계; 상기 포토레지스트 패턴의 경도를 증가시키기 위하여 열처리를 실시하는 제4 단계; 및 상기 포토레지스트 패턴을 식각 마스크로 사용하여 상기 식각 대상층을 선택적으로 식각하는 제5 단계를 포함하여 이루어진다.A characteristic semiconductor device manufacturing method provided from the above-described technical principles of the present invention includes a first step of coating a photoresist on a predetermined etching target layer; Selectively exposing and developing the photoresist to form a photoresist pattern; A third step of performing excimer laser front exposure; A fourth step of performing heat treatment to increase the hardness of the photoresist pattern; And a fifth step of selectively etching the etching target layer using the photoresist pattern as an etching mask.

이하, 첨부된 도면을 참조하여 본 발명을 상술한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

첨부된 도면 도 1a 내지 도 1d는 본 발명의 일실시예에 따른 미세 패턴 형성 공정을 도시한 것이다.1A to 1D illustrate a fine pattern forming process according to an embodiment of the present invention.

우선, 도 1a에 도시된 바와 같이 실리콘 기판(10) 상부에 형성된 식각 대상층(11) 상에 원자외선 포토레지스트(12)를 도포한 다음, 소정의 포토마스크(20)를 사용하여 원자외선 노광을 실시한다.First, as shown in FIG. 1A, an ultraviolet ray photoresist 12 is coated on an etching target layer 11 formed on a silicon substrate 10, and then ultraviolet ray exposure is performed using a predetermined photomask 20. Conduct.

계속하여, 현상 공정을 통해 포토레지스트 패턴(13)을 형성하고, 도 1b에 도시된 바와 같이 193∼400㎚ 파장을 가진 엑시머 레이저(excimer laser)를 사용하여 전면 노광을 실시한다. 이때, 온도는 0∼180℃ 범위에서 조절하며, 노광 에너지는 1∼200mJ/㎠ 범위에서 조절한다.Subsequently, the photoresist pattern 13 is formed through a developing process, and front surface exposure is performed using an excimer laser having a wavelength of 193 to 400 nm as shown in FIG. 1B. At this time, the temperature is adjusted in the range of 0 ~ 180 ℃, the exposure energy is adjusted in the range of 1 ~ 200mJ / ㎠.

이어서, 도 1c에 도시된 바와 같이 엑시머 레이저 처리된 포토레지스트 패턴(13)의 경도를 높이기 위하여 20∼180℃에서 열처리를 실시한다. 이때, 진공 기술을 사용하면 효과적이다. 진공은 0.1∼600mmHg로 조절한다. 이러한 공정을 진행하면 포토레지스트 패턴(13)으로부터 저분자가 제거되고, 포토레지스트 패턴(13)의 두께는 5∼10% 정도 감소하게 된다.Subsequently, heat treatment is performed at 20 to 180 ° C. to increase the hardness of the excimer laser-treated photoresist pattern 13 as shown in FIG. 1C. At this time, the use of vacuum technology is effective. The vacuum is adjusted to 0.1 to 600 mmHg. In this process, low molecules are removed from the photoresist pattern 13, and the thickness of the photoresist pattern 13 is reduced by about 5 to 10%.

다음으로, 도 1d에 도시된 바와 같이 포토레지스트 패턴(13)을 식각 마스크로 사용하여 식각 대상층(11)을 선택 식각하여 미세 패턴(14)을 형성하고, 포토레지스트 패턴(13)을 제거한다. 여기서, 경도가 증가된 포토레지스트 패턴(13)을 식각 마스크로 사용함에 따라 포토레지스트 패턴(13)의 식각 선택비 특성이 50∼100% 정도 향상된다.Next, as illustrated in FIG. 1D, the etching target layer 11 is selectively etched using the photoresist pattern 13 as an etching mask to form the fine pattern 14, and the photoresist pattern 13 is removed. Here, the etching selectivity characteristics of the photoresist pattern 13 may be improved by about 50 to 100% by using the photoresist pattern 13 having an increased hardness as an etching mask.

상술한 일실시예는 원자외선 메커니즘을 일례로 들어 설명하였으나, 본 발명은 아르곤 플로라이드(ArF) 포토레지스트를 비롯한 다른 종류의 포토레지스트를 사용한 리소그래피 공정시에도 적용할 수 있다.Although the above-described embodiment has been described using an example of an ultraviolet ray mechanism, the present invention can be applied to a lithography process using another kind of photoresist, including an argon fluoride (ArF) photoresist.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

이상에서와 같이 본 발명은 포토레지스트 패턴의 식각 선택비 특성을 향상시킴으로써 식각 공정을 안정화할 수 있으며, 이에 따라 포토레지스트의 두께 감소가 가능해지므로 사진 공정이 안정화되어 재공정 빈도가 줄어들게 되고 포토레지스트의 사용량을 줄여 원가 절감 효과를 기대할 수 있다. 또한, 포토레지스트 두께의 감소로 인하여 0.18㎛, 0.16㎛ 선폭의 미세 패턴 형성 기술이 확보되어 차세대 반도체 제조시 조기 양산을 기대할 수 있다.As described above, the present invention can stabilize the etching process by improving the etch selectivity characteristic of the photoresist pattern, and thus the thickness of the photoresist can be reduced, so that the photo process is stabilized, thereby reducing the frequency of reprocessing. Cost savings can be expected by reducing usage. In addition, due to the reduction in the thickness of the photoresist, a fine pattern forming technology of 0.18 μm and 0.16 μm line widths is secured, and thus, early production may be expected in next-generation semiconductor manufacturing.

Claims (5)

소정의 식각 대상층 상부에 포토레지스트를 코팅하는 제1 단계;Coating a photoresist on a predetermined etching target layer; 상기 포토레지스트를 선택적으로 노광하고, 현상하여 포토레지스트 패턴을 형성하는 제2 단계;Selectively exposing and developing the photoresist to form a photoresist pattern; 엑시머 레이저 전면 노광을 실시하는 제3 단계;A third step of performing excimer laser front exposure; 상기 포토레지스트 패턴의 경도를 증가시키기 위하여 열처리를 실시하는 제4 단계; 및A fourth step of performing heat treatment to increase the hardness of the photoresist pattern; And 상기 포토레지스트 패턴을 식각 마스크로 사용하여 상기 식각 대상층을 선택적으로 식각하는 제5 단계A fifth step of selectively etching the etching target layer using the photoresist pattern as an etching mask 를 포함하여 이루어진 반도체 장치 제조방법.A semiconductor device manufacturing method comprising a. 제 1 항에 있어서,The method of claim 1, 상기 포토레지스트가The photoresist 원자외선 포토레지스트 또는 아르곤 플로라이드 포토레지스트인 반도체 장치 제조방법.A method of manufacturing a semiconductor device, which is an ultraviolet ray photoresist or an argon fluoride photoresist. 제 1 항에 있어서,The method of claim 1, 상기 제3 단계가The third step is 0℃ 내지 100℃의 온도에서 1mJ/㎠ 내지 200mJ/㎠의 노광 에너지를 사용하여 이루어진 반도체 장치 제조방법.A method for manufacturing a semiconductor device using exposure energy of 1 mJ / cm 2 to 200 mJ / cm 2 at a temperature of 0 ° C. to 100 ° C. 제 1 항 또는 제 3 항에 있어서,The method according to claim 1 or 3, 상기 제4 단계가The fourth step is 20℃ 내지 180℃의 온도에서 이루어지는 반도체 장치 제조방법.A method for manufacturing a semiconductor device at a temperature of 20 ° C to 180 ° C. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 제4 단계가The fourth step is 500mmHg 내지 0.1mmHg 압력 하에서 이루어지는 반도체 장치 제조방법.A semiconductor device manufacturing method made under a pressure of 500 mmHg to 0.1 mmHg.
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Publication number Priority date Publication date Assignee Title
KR100855264B1 (en) * 2002-11-28 2008-09-01 주식회사 하이닉스반도체 Method for improving photo process margin

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100855264B1 (en) * 2002-11-28 2008-09-01 주식회사 하이닉스반도체 Method for improving photo process margin

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