KR100262034B1 - Method for manufacturing solid-state image sensor - Google Patents
Method for manufacturing solid-state image sensor Download PDFInfo
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- KR100262034B1 KR100262034B1 KR1019980003018A KR19980003018A KR100262034B1 KR 100262034 B1 KR100262034 B1 KR 100262034B1 KR 1019980003018 A KR1019980003018 A KR 1019980003018A KR 19980003018 A KR19980003018 A KR 19980003018A KR 100262034 B1 KR100262034 B1 KR 100262034B1
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 239000007787 solid Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 abstract description 12
- 230000007547 defect Effects 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 6
- 239000012535 impurity Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 239000004925 Acrylic resin Substances 0.000 description 2
- 229920000178 Acrylic resin Polymers 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910001385 heavy metal Inorganic materials 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/762—Charge transfer devices
- H01L29/765—Charge-coupled devices
- H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
- H01L29/76808—Input structures
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Abstract
Description
본 발명은 고체촬상소자의 제조방법에 관한 것으로, 특히, 식각과정에서 기판의 포토다이오드가 손상되는 것을 최소화하기에 적당한 고체촬상소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a solid state image pickup device, and more particularly, to a method for manufacturing a solid state image pickup device suitable for minimizing damage to a photodiode of a substrate during an etching process.
일반적인 고체촬상소자는 빛에 의해 발생되는 전하신호를 전기적 신호로 바꾸는 광전변환을 이용하는 소자로, 포토다이오드(PD:PhotoDiode)와 VCCD(VCCD:Vertical Charge Coupled Devices)로 구성된 단위 셀들로 배열되어 형성된 PD어레이부와, HCCD(HCCD:Horizontal Charge Coupled Devices), 신호검출부를 포함한다.A general solid state imaging device is a device using photoelectric conversion that converts a charge signal generated by light into an electrical signal, and is formed by arranging unit cells composed of photodiodes (PD) and vertical charge coupled devices (VCCD). The array unit includes an HCCD (Horizontal Charge Coupled Devices) and a signal detection unit.
일반적인 고체촬상소자의 작동을 설명하면 다음과 같다.The operation of a general solid state image pickup device is as follows.
우선, 마이크로렌즈를 통하여 집속된 빛이 수광부인 포토다이오드(PD)에 닿으면 광전효과에 의해 전하가 발생되며, 이 전하가 포토다이오드(PD) 아래의 포텐셜 우물에 축적된다. 이렇게 모아진 전하는 전송 게이트(TG:Transfer Gate)에 걸리는 전압에 의해 야기되는 포텐셜의 변화에 의해 전하 이동로인 수직전하전송영역(VCCD:Vertical Charge Coupled Devices) 및 수평전하전송영역(HCCD:Horizontal CCD)를 통하여 순서대로 전달되어 AMP를 통해 출력된다.First, when the light focused through the microlenses touches the photodiode PD, which is a light receiving unit, charges are generated by the photoelectric effect, and the charge is accumulated in the potential well under the photodiode PD. These charges are collected by the vertical charge transfer region (VCCD) and horizontal charge transfer region (HCCD), which are charge transfer paths, due to the potential change caused by the voltage applied to the transfer gate (TG). Passed in order through and output through AMP.
도 1a 내지 도 1c 는 종래기술에 따른 고체촬상소자의 제조공정도이다.1A to 1C are manufacturing process diagrams of a solid state image pickup device according to the prior art.
도 1a 와 같이, N 형의 반도체기판(100)에 다른 도전형인 P형의 불순물이온을 주입함으로써 P웰(102)을 형성한다. 이 후, 통상적인 공정을 통해, 기판(100)상에 입사되는 빛의 세기에 따라 신호전하를 발생하기 위한 광전환변화부인 포토다이오드(PD)(104)와 포토다이오드(PD)에서 발생된 신호전하를 수직으로 전송하는 전하전송영역인 HCCD(106) 를 교대로 형성한다.As shown in FIG. 1A, the P well 102 is formed by injecting P-type impurity ions of another conductivity type into the N-type semiconductor substrate 100. Subsequently, signals generated by the photodiode PD and the photodiode PD, which are light conversion change units for generating signal charges according to the intensity of light incident on the substrate 100, through a conventional process. The HCCD 106, which is a charge transfer region for vertically transferring charges, is formed alternately.
다음에, 화소간의 격리를 위해 포토다이오드 주변에 채널스톱층(CST:Channel STop layer)(108)을 형성한다. 그리고, 상술한 구조를 갖는 반도체기판(100)에 ONO(Oxide-Nitride-Oxide) 등을 적층하여 제 1절연막(112)을 형성한다.Next, a channel stop layer (CST) 108 is formed around the photodiode for isolation between pixels. An oxide-nitride-oxide (ONO) or the like is stacked on the semiconductor substrate 100 having the above-described structure to form a first insulating film 112.
도 1b 와 같이, 제 1절연막(112)상에 제 1다결정실리콘층 증착 및 식각공정을 거쳐서 제 1게이트전극(116)을 형성한 후, 이 제 1게이트전극(116)을 열산화시키어 표면에 제 1표면산화막(118)을 형성한다.As shown in FIG. 1B, after the first gate electrode 116 is formed on the first insulating layer 112 through the deposition and etching of the first polysilicon layer, the first gate electrode 116 is thermally oxidized to a surface thereof. A first surface oxide film 118 is formed.
다음에, 반도체기판(100) 상에 제 1표면산화막(118)을 덮도록 제 2다결정실리콘층 증착한 후, 식각공정을 거쳐서 제 1게이트전극(116) 상부에 위치하도록 제 2게이트전극(120)을 형성한다. 그리고 제 2게이트전극(120)을 열산화시키어 상술한 제 2게이트전극(120)을 덮는 제 2표면산화막(121)을 형성한다.Next, a second polysilicon layer is deposited on the semiconductor substrate 100 so as to cover the first surface oxide film 118, and then, through the etching process, the second gate electrode 120 is positioned on the first gate electrode 116. ). The second gate electrode 120 is thermally oxidized to form a second surface oxide film 121 covering the second gate electrode 120 described above.
여기에서, 트랜스퍼 게이트인 1게이트전극(116) 및 제 2게이트전극(120)은 포토다이오드(104)에 빛이 입사되어 생성된 전하를 읽어내어 이동시키어 주는 역할을 하고 있다. 그리고, 제 1, 제 2표면산화막(118)(121)은 각각의 제 1 및 제 2다결정실리콘층 간을 완전 격리시킨다.Here, the first gate electrode 116 and the second gate electrode 120, which are transfer gates, serve to read and move charges generated by light incident on the photodiode 104. The first and second surface oxide films 118 and 121 completely isolate between the first and second polysilicon layers, respectively.
그리고, 제 1게이트전극(116) 및 제 2게이트전극(120) 형성 시에 포토다이오드(104)와 대응되는 부위의 제 1절연막(112)이 노출되도록 한다.When the first gate electrode 116 and the second gate electrode 120 are formed, the first insulating layer 112 of the portion corresponding to the photodiode 104 is exposed.
이어서, 포토다이오드(104)와 대응되는 제 1절연막(112)상에 P형 불순물이온을 주입 및 확산시키어 포토다이오드 표면에 P형 불순물층(PDP)(110)을 형성한다.Subsequently, P-type impurity ions are implanted and diffused onto the first insulating layer 112 corresponding to the photodiode 104 to form a P-type impurity layer (PDP) 110 on the surface of the photodiode.
도 1c 와 같이, 상기 구조 전면에 제 2절연막(122)을 형성한다. 그리고 제 2절연막(122)상에 금속층을 증착 및 식각공정을 거쳐서 포토다이오드(104)와 대응된 부위가 노출되고 VCCD(106)와 대응된 부위를 덮는 차광층(124)을 형성한다.As shown in FIG. 1C, a second insulating layer 122 is formed over the entire structure. The metal layer is deposited and etched on the second insulating layer 122 to form a light blocking layer 124 exposing portions corresponding to the photodiodes 104 and covering portions corresponding to the VCCD 106.
다음에, 차광층(124) 및 노출된 제 2절연막(122)을 덮도록 절연물질을 증착하여 보호막(126)을 형성한다.Next, an insulating material is deposited to cover the light blocking layer 124 and the exposed second insulating film 122 to form a protective film 126.
도 1d 와 같이, 상기 구조 전면을 평탄하게 덮는 제 1평탄화층(128)을 형성한 후, 이 제 1평탄화층(128) 상부에 칼라필터층(130)을 형성한다. 이 후에, 제 1평탄화층(128) 상에 칼라필터층(130)을 덮도록 제 2평탄화층(132)을 형성한다. 제 2평탄화층(132) 상에 아크릴 계통의 수지 물질을 도포한 후, 사진식각 공정을 진행시키어 포토다이오드(104) 상부에 형성되도록 패터닝하고, 다시 열에 의한 리플로우 공정을 진행시키어 마이크로렌즈(134)를 형성한다.As shown in FIG. 1D, the first flattening layer 128 is formed to cover the entire surface of the structure. Then, the color filter layer 130 is formed on the first flattening layer 128. Thereafter, the second leveling layer 132 is formed on the first leveling layer 128 to cover the color filter layer 130. After applying an acrylic resin material on the second planarization layer 132, the photolithography process is performed, patterned to be formed on the photodiode 104, and the reflow process by heat is further performed to the microlens 134 ).
상술한 렌즈층(134)를 통해 입사된 빛은 포토다이오드에서 전하를 발생시키고, 발생된 전하는 트랜스퍼 게이트인 제 1게이트전극 및 제 2게이트전극에 의해 낮아진 베리어에 의해서 VCCD 및 HCCD에 전달되어 AMP를 통해 리드아웃된다.Light incident through the lens layer 134 generates charge in the photodiode, and the generated charge is transferred to the VCCD and the HCCD by barriers lowered by the first gate electrode and the second gate electrode, which are transfer gates. Leads out.
그러나, 종래의 기술에서는 트랜스퍼 게이트 형성을 위한 다결정실리콘층 식각 및 차광층 형성을 위한 금속층 식각 등의 공정에서 포토다이오드가 표면에 노출됨으로써 중금속에 오염되었다. 여기에서 중금속 오염이란 건식식각 장비에 기인한 것으로, 이러한 건식식각 장비 내의 반응챔버 등 스텐레스(stainless)로 만든 부분이 많아 오염원으로 작용한다.However, in the prior art, photodiodes are exposed to the surface in the process of polycrystalline silicon layer etching for forming the transfer gate and metal layer etching for forming the light shielding layer. Here, heavy metal contamination is caused by dry etching equipment, and many parts made of stainless steel such as reaction chambers in such dry etching equipment act as a pollution source.
따라서, 상술한 중금속오염 등으로 백점(white effect)이 발생됨으로써 씨씨디의 수율이 저하되는 문제점이 발생되었다.Therefore, a white point is generated due to heavy metal contamination and the like, which causes a problem that the yield of the CD is lowered.
상기의 문제점을 해결하고자, 본 발명의 목적은 식각 등의 공정에서 발생되는 포토다이오드의 손상을 줄일 수 있는 고체촬상소자의 제조방법을 제공하려는 것이다.In order to solve the above problems, an object of the present invention is to provide a method for manufacturing a solid-state image pickup device that can reduce the damage of the photodiode generated in the etching process.
따라서, 본 발명의 고체촬상소자의 제조방법은 포토다이오드와 수직전하전송영역이 교대로 형성된 반도체기판에 제 1절연막을 형성하는 공정과, 제 1절연막 상에 포토다이오드와 대응되는 부위에 잔류되도록 제 2절연막을 형성하는 공정과, 제 2절연막 양측에 트랜스퍼 게이트를 형성하는 공정과, 트랜스퍼 게이트를 덮도록 제 3절연막을 형성하는 공정을 구비한 것을 특징으로 한다.Therefore, the method of manufacturing a solid-state image pickup device of the present invention comprises the steps of forming a first insulating film on a semiconductor substrate on which photodiodes and vertical charge transfer regions are alternately formed, so as to remain at portions corresponding to the photodiodes on the first insulating film. And a step of forming a second insulating film, a step of forming a transfer gate on both sides of the second insulating film, and a step of forming a third insulating film to cover the transfer gate.
도 1a 내지 도 1d 는 종래기술에 따른 고체촬상소자의 제조공정도이고,1A to 1D are manufacturing process diagrams of a solid state image pickup device according to the prior art,
도 2a 내지 도 2e 는 본 발명에 따른 고체촬상소자의 제조공정도이다.2A to 2E are manufacturing process diagrams of the solid state image pickup device according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100, 200. 반도체기판 102, 202. P웰100, 200. Semiconductor substrates 102, 202. P well
104, 204. 포토다이오드 106, 206. 수직전하전송영역104, 204. Photodiodes 106, 206. Vertical charge transfer area
108, 208. 채널스톱층 110, 210. PDP층108, 208. Channel stop layer 110, 210. PDP layer
124, 224. 차광막 126, 226. 보호막124, 224. Light shielding films 126, 226. Protective film
130, 230. 칼라필터층 134, 234. 마이크로렌즈130, 230. Color filter layer 134, 234. Microlens
112, 122, 212, 214, 222. 절연막112, 122, 212, 214, 222. Insulation layer
116, 120, 216, 220. 전송게이트116, 120, 216, 220. Transmission gate
118, 121, 218, 221. 표면산화막118, 121, 218, 221. Surface oxide film
128, 132, 228, 232. 평탄화층128, 132, 228, 232. Flattening layer
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하겠다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2a 내지 도 2e 는 본 발명에 따른 고체촬상소자의 제조공정도이다.2A to 2E are manufacturing process diagrams of the solid state image pickup device according to the present invention.
도 2a 와 같이, N형의 반도체기판(200)에 다른 도전형인 P형의 불순물이온을 주입함으로써 P웰(202)을 형성하고, 통상적인 공정을 통해, 입사되는 빛의 세기에 따라 신호전하를 발생하기 위한 포토다이오드(204)와 포토다이오드(204)에서 발생된 신호전하를 전송하는 전하전송영역인 VCCD(206)를 교대로 형성하며, 포토다이오드(204)와 VCCD(206)은 N형의 불순물이온을 주입하여 확산함으로써 형성된다.As shown in FIG. 2A, the P well 202 is formed by injecting another conductivity type P-type impurity ion into the N-type semiconductor substrate 200, and through the conventional process, the signal charge is changed according to the intensity of the incident light. The photodiode 204 and the VCCD 206, which are charge transfer regions for transferring the signal charges generated by the photodiode 204, are alternately formed, and the photodiode 204 and the VCCD 206 are N-type. It is formed by injecting and diffusing impurity ions.
이 후에, 화소간의 격리를 위해 채널스톱층(CST)(208)을 형성한다.Thereafter, a channel stop layer (CST) 208 is formed for isolation between pixels.
그리고, 상술한 구조를 갖는 반도체기판(200)에 ONO를 다층으로 적층하여 제 1절연막(212)을 형성한다. 이 후에, 제 1절연막(212)상에 질화막 또는 산화막을 이용하여 제 2절연막(214)을 2000 ∼ 5000Å 두께로 형성한다.The first insulating film 212 is formed by stacking ONO in multiple layers on the semiconductor substrate 200 having the above-described structure. Thereafter, the second insulating film 214 is formed to have a thickness of 2000 to 5000 kV on the first insulating film 212 using a nitride film or an oxide film.
다음에, 제 2절연막(214)상에 포토레지스트를 도포한 후, 노광 및 현상하여 포토다이오드(204)와 대응된 부위의 제 1절연막(212) 상에 잔류되도록 패터닝된 마스크패턴(216)을 제조한다.Next, after the photoresist is applied on the second insulating film 214, the mask pattern 216 patterned to be exposed and developed to remain on the first insulating film 212 at a portion corresponding to the photodiode 204 is formed. Manufacture.
도 2b 와 같이, 마스크패턴(216)을 식각마스크로 하여 제 2절연막(214)의 일부를 제거하여 표면보호막(214-1)을 형성한다. 그리고, 마스크패턴(216)을 제거한다.As shown in FIG. 2B, a portion of the second insulating layer 214 is removed using the mask pattern 216 as an etching mask to form the surface protection layer 214-1. Then, the mask pattern 216 is removed.
제 1게이트전극 및 제 2게이트전극 형성을 위한 다결정실리콘층 식각 및 차광층 형성을 위한 금속층 식각 시, 통상적으로 제 1절연막(212) 뿐만 아니라, 제 1절연막 하부의 실리콘기판(200)까지 손상을 입게 되는 데, 본 발명에서의 표면보호막(214-1)은 포토다이오드(204)와 대응된 부위의 제 1절연막(212)을 덮고 있으므로, 상술한 식각 등의 공정으로 부터 제 1절연막(212) 및 실리콘기판(200)을 보호해주는 역할을 한다.When etching the polysilicon layer for forming the first gate electrode and the second gate electrode and etching the metal layer for forming the light shielding layer, not only the first insulating layer 212 but also the silicon substrate 200 under the first insulating layer may be damaged. In the present invention, since the surface protective film 214-1 covers the first insulating film 212 at a portion corresponding to the photodiode 204, the first insulating film 212 is subjected to the above-described etching or the like process. And it serves to protect the silicon substrate 200.
도 2c 와 같이, 제 1절연막(212) 상에 표면보호막(214-1)을 덮도록 제 1다결정실리콘층을 증착하고 사진식각 공정을 거쳐서 포토다이오드(204)와 대응된 부위를 노출시키는 제 1게이트전극(216)을 형성하고, 제 1게이트전극(216)을 열산화시키어 상술한 제 1게이트전극(216)을 덮는 제 1표면산화막(218)을 형성한다.As illustrated in FIG. 2C, a first polysilicon layer is deposited on the first insulating layer 212 so as to cover the surface protection layer 214-1, and then a photoetching process exposes the first diode and the portion corresponding to the photodiode 204. The gate electrode 216 is formed, and the first gate electrode 216 is thermally oxidized to form a first surface oxide film 218 covering the first gate electrode 216 described above.
그리고 상기 구조 전면에 제 2다결정실리콘층을 증착하고 사진식각 공정을 거쳐서 제 1게이트전극(216) 상부에 위치하도록 제 2게이트전극(220)을 형성한다. 이 후, 제 2게이트전극(220)을 열산화시키어 상술한 제 2게이트전극(220)을 덮는 제 2표면산화막(221)을 형성한다.The second polysilicon layer is deposited on the entire surface of the structure, and the second gate electrode 220 is formed to be positioned on the first gate electrode 216 through a photolithography process. Thereafter, the second gate electrode 220 is thermally oxidized to form a second surface oxide film 221 covering the second gate electrode 220 described above.
다음에, 상기 구조를 덮는 제 3절연막(222)을 형성한다.Next, a third insulating film 222 covering the structure is formed.
도 2d 와 같이, 제 3절연막(222)상에 금속층을 적층한 후, 포토다이오드와 대응된 부위의 제 2절연막을 노출시키고, 수직전하전송영역(VCCD)(206)과 대응된 부위를 가리는 차광층(224)을 형성한다. 그리고, 차광층(224) 및 노출된 제 3절연막(222)을 덮도록 보호막(226)을 형성한다.As shown in FIG. 2D, after the metal layer is stacked on the third insulating layer 222, the second insulating layer of the portion corresponding to the photodiode is exposed, and light shielding covers a portion corresponding to the vertical charge transfer region (VCCD) 206. Form layer 224. In addition, the passivation layer 226 is formed to cover the light blocking layer 224 and the exposed third insulating layer 222.
도 2e 와 같이, 상기 구조 전면을 평탄하게 덮는 제 1평탄화층(228)을 형성한 후, 이 제 1평탄화층(228) 상부에 칼라필터층(230)을 형성한다. 이 후에, 제 1평탄화층(228)상에 칼라필터층(230)을 덮도록 제 2평탄화층(232)을 형성한다. 제 2평탄화층(232) 상에 아크릴 계통의 수지 물질을 도포한 후, 사진식각 공정을 진행시키어 포토다이오드(204) 상부에 형성되도록 패터닝하고, 다시 열에 의한 리플로우 공정을 진행시키어 마이크로렌즈(234)를 형성한다.As shown in FIG. 2E, after the first planarization layer 228 is formed to cover the entire structure, the color filter layer 230 is formed on the first planarization layer 228. Thereafter, a second leveling layer 232 is formed on the first leveling layer 228 to cover the color filter layer 230. After the acrylic resin material is coated on the second planarization layer 232, the photolithography process is performed, and then patterned to be formed on the photodiode 204, and the thermal reflow process is performed again. ).
상술한 바와 같이, 본 발명에서는 포토다이오드 상부에 표면보호막을 형성함으로써 고체촬상소자 제조 시 식각 등의 공정으로 부터 포토다이오드가 손상되는 것을 사전에 방지시키어 주고, 백점을 방지할 수 있는 잇점이 있다.As described above, in the present invention, the surface protection film is formed on the photodiode, thereby preventing the photodiode from being damaged from etching during the manufacturing of the solid state imaging device, and preventing the white spot.
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