KR100237682B1 - Method of forming interconnector of semiconductor device - Google Patents

Method of forming interconnector of semiconductor device Download PDF

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KR100237682B1
KR100237682B1 KR1019970001012A KR19970001012A KR100237682B1 KR 100237682 B1 KR100237682 B1 KR 100237682B1 KR 1019970001012 A KR1019970001012 A KR 1019970001012A KR 19970001012 A KR19970001012 A KR 19970001012A KR 100237682 B1 KR100237682 B1 KR 100237682B1
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metal
aluminum
depositing
forming
contact portion
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KR1019970001012A
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KR19980065841A (en
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심상철
김응수
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윤종용
삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로서, 반도체 기판 위에 소자를 형성하고 절연막을 증착하는 단계, 소자 상부의 절연막을 제거하여 접촉부를 형성하고 장벽 금속막을 증착한 후, 열처리하는 단계, 장벽 금속 상부에 제1 금속을 증착하는 단계, 가열 전용 체임버에서 제1 금속을 녹이는 단계, 금속 증착 체임버에서 제2 금속을 증착하는 단계를 포함한다. 이때, 제1 금속과 제2 금속류는 알루미늄이나 알루미늄 합금 등의 동일 재질의 금속을 사용하고, 제1 금속을 녹이는 공정이후 제1 금속이 접촉부 내로 완전히 들어가서 접촉부 외부로 넘치지 않는 두께로 제1 금속을 증착한다. 본 발명에 따른 반도체 소자의 금속 배선 형성 방법에서는 접촉부의 폭이나 종횡비 또는 측벽의 경사도에 관계없이 접촉부 내에 알루미늄을 채워넣을 수 있고, 일렉트로마이그레이션 특성의 열화와 같은 불량을 예방할 수 있으며, 알루미늄을 보다 완벽하게 평탄화시킬 수 있다.The present invention relates to a method for forming a metal wiring of a semiconductor device, comprising: forming a device on a semiconductor substrate and depositing an insulating film, removing the insulating film on the device to form a contact portion, depositing a barrier metal film, and then performing a heat treatment, a barrier Depositing a first metal on top of the metal, melting the first metal in a heating-only chamber, and depositing a second metal in the metal deposition chamber. In this case, the first metal and the second metals are made of the same material as aluminum or an aluminum alloy, and after the process of melting the first metal, the first metal is formed to a thickness such that the first metal does not fully enter the contact portion and overflow beyond the contact portion. Deposit. In the method of forming a metal wiring of a semiconductor device according to the present invention, aluminum can be filled in a contact portion regardless of the width, aspect ratio, or inclination of the sidewall of the contact portion, and it is possible to prevent defects such as deterioration of electromigration characteristics and to make aluminum more perfect. Can be flattened.

Description

반도체 소자의 배선 형성 방법Wiring Formation Method of Semiconductor Device

본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것이다.The present invention relates to a method for forming metal wiring of a semiconductor device.

반도체 소자의 고집적화에 따라 접촉부(contact hole)의 폭이 초미세화되고 접촉부의 종횡비가 커짐에 따라 접촉부 내부에 금속을 채워 넣는 기술이 필수적으로 요구되고 있으며, 이를 위해 금속 고온 증착(hot sputter deposition), 알루미늄 리플로우(Al reflow), 텅스텐 플러그(W-plug) 등 많은 기술이 개발되어 왔다. 가장 널리 적용되고 있는 텅스텐 플러그 방법은 접촉부 상에 텅스텐을 증착하고 씨엠피(chemical mechanical polishing) 방법으로 접촉부 상부의 텅스텐을 갈아낸 후, 배선용 금속을 다시 증착해야 하기 때문에 공정이 복잡해지고 비용이 증가하는 단점이 있다. 또한, 주로 텅스텐과 알루미늄이 이용되는 배선 구조에서는 전류 인가시 계면으로부터 멀어지는 알루미늄 원자들의 드리프팅(drifting)으로 인해 계면에 틈이 형성되고, 일렉트로마이그레이션(electromigration) 가속 현상이 관찰된다. 금속 고온 증착이나 알루미늄 리플로우 방법은 측벽의 경사도나 접촉부의 종횡비에 따라 주입에 제약이 따르며, 접촉부의 폭이 0.5μm 이하로 되면 접촉부에 금속 주입이 어려운 것으로 알려져 있다.As the width of contact holes becomes very small and the aspect ratio of the contacts increases with the high integration of semiconductor devices, a technology for filling metal into the contacts is essential. For this purpose, hot sputter deposition, Many technologies have been developed, such as aluminum reflow and tungsten plugs. The most widely used tungsten plug method is to deposit tungsten on the contacts, grind the tungsten on the contacts by chemical mechanical polishing, and then re-deposit the wiring metal. There are disadvantages. In addition, in a wiring structure in which tungsten and aluminum are mainly used, gaps are formed at the interface due to drift of aluminum atoms away from the interface when an electric current is applied, and an electromigration acceleration phenomenon is observed. In the high temperature metal deposition method or the aluminum reflow method, the injection is restricted depending on the inclination of the side wall and the aspect ratio of the contact portion, and when the width of the contact portion is 0.5 μm or less, it is known that metal injection is difficult.

그러면, 첨부한 도면을 참고로 하여 종래의 기술에 따른 반도체 소자의 금속 배선 형성 방법에 대하여 설명한다.Next, a metal wiring forming method of a semiconductor device according to the related art will be described with reference to the accompanying drawings.

도1a 또는 도1b는 종래의 기술에 따른 반도체 소자의 배선 공정을 나타낸 단면도이다.1A or 1B are cross-sectional views illustrating a wiring process of a semiconductor device according to the related art.

반도체 기판(1) 위에 선별적인 이온 주입의 방법으로 소자(2)를 형성하고, 그 상부에 절연막(3)을 증착한다. 다음 소자(2)의 표면이 노출되도록 사진 공정을 이용하여 절연막(3)에 접촉부(4)를 형성한다. 세정 공정으로 접촉부(4) 내부에서 노출된 소자(2) 표면에 성장한 자연 산화막(도시하지 않음)을 제거한 후, 티타늄(Ti, 5)과 질화물 티타늄(TiN, 6)을 차례로 증착하여 장벽 금속(barrier metal)층을 증착한다. 그 후, 400℃ 이상의 온도에서 장벽 금속을 열처리(annealing)한고, 기판(1) 전면에 배선용 금속으로 알루미늄막(7)을 상온에서 증착한다[도1a 참조].The element 2 is formed on the semiconductor substrate 1 by a selective ion implantation method, and the insulating film 3 is deposited thereon. Next, the contact portion 4 is formed on the insulating film 3 using a photolithography process so that the surface of the element 2 is exposed. After removing the natural oxide film (not shown) grown on the surface of the device 2 exposed inside the contact portion 4 by the cleaning process, titanium (Ti, 5) and titanium nitride (TiN, 6) are sequentially deposited to form a barrier metal ( deposit a barrier metal layer. Thereafter, the barrier metal is annealed at a temperature of 400 ° C. or higher, and the aluminum film 7 is deposited at room temperature on the entire surface of the substrate 1 with the metal for wiring (see FIG. 1A).

다음, 웨이퍼를 히팅(heating) 전용 체임버(chamber)로 이동시킨후 500∼550℃의 온도로 가열하면 접촉부(4) 주위의 알루미늄(7)이 접촉부(4) 내부로 이동하여 접촉부(4)에 채워진다.Next, when the wafer is moved to a heating chamber only and heated to a temperature of 500 to 550 ° C., the aluminum 7 around the contact part 4 moves inside the contact part 4 to the contact part 4. Is filled.

그러나, 이러한 반도체 소자의 금속 배선 형성 방법은 접촉부(4)의 종횡비와 측벽의 경사도에 따라 제약을 받는다. 또한, 알루미늄 리플로우 방법으로는 접촉부 폭이 0.5μm 이하로 감소할 경우 알루미늄의 채워짐 상태가 달라지기 때문에 알루미늄의 두께를 다양하게 분리하여 증착하는 라인에서는 적용하기 어렵다.However, the method of forming the metal wiring of the semiconductor element is limited by the aspect ratio of the contact portion 4 and the inclination of the side wall. In addition, in the aluminum reflow method, when the contact width decreases to 0.5 μm or less, the filling state of aluminum is different, so it is difficult to apply it to a line in which various thicknesses of aluminum are deposited.

본 발명의 과제는 이러한 문제를 해결하는 것으로서, 접촉부의 폭이나 종횡비 또는 측벽의 경사도에 관계없이 접촉부 내에 알루미늄을 채워넣는 데에 있다.An object of the present invention is to solve such a problem and to fill aluminum in a contact regardless of the width or aspect ratio of the contact or the inclination of the side wall.

도1a 또는 도1b는 종래의 기술에 따른 반도체 소자의 배선 공정을 나타낸 단면도이고,1A or 1B are cross-sectional views illustrating a wiring process of a semiconductor device according to the related art.

도2a 내지 도2c는 본 발명에 따른 반도체 소자의 배선 공정을 순서적으로 나타낸 단면도이다.2A to 2C are cross-sectional views sequentially illustrating wiring processes of a semiconductor device according to the present invention.

이러한 과제를 해결하기 위한 본 발명에 따른 반도체 소자의 금속 배선 형성 방법은 반도체 기판 위에 소자를 형성하고 절연막을 증착하는 단계, 소자 상부의 절연막을 제거하여 접촉부를 형성하고 장벽 금속막을 증착한 후, 열처리하는 단계, 장벽 금속 상부에 제1 금속을 증착하는 단계, 가열 전용 체임버에서 제1 금속을 녹이는 단계, 금속 증착 체임버에서 제2 금속을 증착하는 단계를 포함한다. 이때, 제1 금속과 제2 금속류는 알루미늄이나 알루미늄 합금 등의 동일 재질의 금속을 사용하고, 제1 금속을 녹이는 공정이후 제1 금속이 접촉부 내로 완전히 들어가서 접촉부 외부로 넘치지 않는 두께로 제1 금속을 증착한다.In order to solve the above problems, a method of forming a metal wire of a semiconductor device according to the present invention includes forming a device on a semiconductor substrate and depositing an insulating film, removing the insulating film over the device to form a contact portion, and depositing a barrier metal film, followed by heat treatment. And depositing a first metal over the barrier metal, melting the first metal in a heating-only chamber, and depositing a second metal in the metal deposition chamber. In this case, the first metal and the second metals are made of the same material as aluminum or an aluminum alloy, and after the process of melting the first metal, the first metal is formed to a thickness such that the first metal does not fully enter the contact portion and overflow beyond the contact portion. Deposit.

이러한 반도체 소자의 금속 배선 형성 방법에서는 제1 금속을 얇은 두께로 형성한 후 열처리하고 다시 배선을 위한 금속을 증착하기 때문에 접촉부 폭이나 측벽의 경사도에 관계없이 금속이 접촉부 내에 채워진다.In the method of forming a metal wiring of the semiconductor device, since the first metal is formed to a thin thickness, then heat-treated and the metal for wiring is deposited again, the metal is filled in the contact regardless of the contact width or the inclination of the sidewall.

그러면, 첨부한 도면을 참고로 하여 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법에 대하여 본 발명의 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 상세하게 설명한다.Next, a metal wire forming method of a semiconductor device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings so that a person having ordinary skill in the art may easily perform the same.

도2a 내지 도2c는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 나타낸 단면도이다.2A to 2C are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention.

먼저, 반도체 기판(1) 상에 소자(2)를 형성하고, 그 상부에 절연막(3)을 증착한다. 다음, 소자(2)의 표면이 노출되도록 접촉부(4)를 형성하고 세정을 실시하고, 기판(1) 전면에 티타늄(5)과 질화 티타늄(6)을 각각 500Å 이하, 500∼1500Å의 두께로 증착하여 장벽 금속층을 형성한 후, 400℃ ∼500℃의 온도로 열처리를 실시하여 장벽 금속을 안정화시킨다. 1차 알루미늄 또는 알루미늄의 합금(7)을 상온에서 1000Å이하의 얇은 두께로 증착한다[도2a 참조].First, the element 2 is formed on the semiconductor substrate 1, and the insulating film 3 is deposited on it. Next, the contact portion 4 is formed and cleaned so that the surface of the element 2 is exposed, and the titanium 5 and the titanium nitride 6 are respectively 500 Å or less and 500-1500 각각 on the entire surface of the substrate 1. After vapor deposition to form a barrier metal layer, heat treatment is performed at a temperature of 400 ° C to 500 ° C to stabilize the barrier metal. Primary aluminum or an alloy of aluminum 7 is deposited to a thin thickness of 1000 kPa or less at room temperature (see FIG. 2A).

다음, 1차 알루미늄 또는 알루미늄 합금(7)이 증착되어 있는 웨이퍼를 가열 전용 체임버로 이동시킨후, 가열 체임버에서 빠른 열 공정(rapid thermal process : RTP) 기술로 580∼660℃의 온도로 가열하여 1차 알루미늄 또는 알루미늄 합금(7)을 용해시킨다. 이때, 1차 알루미늄(7)이 접촉부(4) 내로 완전히 잠겨야 한다. 즉, 용해 후의 알루미늄 표면(8)의 높이가 접촉부 표면(9)보다 낮아야 한다. 이를 위해서는 제1 알루미늄(7) 증착량이 적절히 조절되어야 한다[도2b 참조].Next, the wafer on which the primary aluminum or aluminum alloy 7 is deposited is moved to a heating chamber, and then heated to a temperature of 580 to 660 ° C. using a rapid thermal process (RTP) technology in the heating chamber. Primary aluminum or aluminum alloy 7 is dissolved. At this time, the primary aluminum 7 should be completely locked into the contact 4. That is, the height of the aluminum surface 8 after melting should be lower than the contact surface 9. For this purpose, the deposition amount of the first aluminum 7 must be appropriately adjusted (see FIG. 2B).

마지막으로, 웨이퍼를 가열 체임버로부터 알루미늄 증착 체임버로 다시 이동시켜서 제2 알루미늄 또는 알루미늄 합금(10)을 1000Å 이상의 두께로 증착하여 원하는 배선 두께를 얻는다. 제2 알루미늄을 증착하기 전에 웨이퍼를 550℃이하의 온도로 냉각시켜야 한다[도2c 참조].Finally, the wafer is moved back from the heating chamber to the aluminum deposition chamber to deposit the second aluminum or aluminum alloy 10 to a thickness of 1000 ns or more to obtain the desired wiring thickness. Before depositing the second aluminum, the wafer must be cooled to a temperature below 550 ° C. (see FIG. 2C).

이처럼, 본 발명에서는 접촉부(4)를 채우기 위한 제1 알루미늄(7) 공정과 배선 형성을 위한 제2 알루미늄(10) 공정을 실시하며, 그 재질이 동일하다.As described above, in the present invention, the first aluminum 7 process for filling the contact portion 4 and the second aluminum 10 process for forming the wiring are performed, and the material is the same.

따라서, 본 발명에 따른 반도체 소자의 금속 배선 형성 방법에서는 접촉부의 폭이나 종횡비 또는 측벽의 경사도에 관계없이 접촉부 내에 알루미늄을 채워넣을 수 있고, 제1 금속과 제2 금속이 재질이 동일하기 때문에 일렉트로마이그레이션 특성의 열화와 같은 불량을 예방할 수 있으며, 알루미늄을 보다 완벽하게 평탄화시킬 수 있다.Therefore, in the method for forming a metal wiring of the semiconductor device according to the present invention, aluminum can be filled into the contact portion regardless of the width, aspect ratio, or inclination of the sidewall of the contact portion, and since the first metal and the second metal have the same material, electromigration is performed. Defects such as deterioration of properties can be prevented, and aluminum can be flattened more perfectly.

Claims (12)

반도체 기판 위에 소자를 형성하고 절연막을 증착하는 단계, 상기 소자 상부의 절연막을 제거하여 접촉부를 형성하고 장벽 금속막을 증착한 후, 400℃에서 500℃사이의 온도로 열처리하는 단계, 상기 장벽 금속 상부에 제 1금속을 1000Å이하의 두께로 증착하는 단계, 가열 전용 체임버에서 상기 제 1금속을 빠른 열공정 기술을 통하여 580℃에서 660℃사이의 온도로 가열하여 녹이는 단계, 금속 증착 체임버에서 상기 제 2금속을 증착하는 단계를 포함하는 반도체 소자의 금속 배선 형성 방법.Forming a device on the semiconductor substrate and depositing an insulating film; removing the insulating film on the device; forming a contact portion; depositing a barrier metal film; and heat-treating at a temperature between 400 ° C. and 500 ° C., on the barrier metal. Depositing a first metal to a thickness of 1000 Å or less, heating the first metal to a temperature between 580 ° C. and 660 ° C. through a rapid thermal process technology in a heating chamber, and melting the second metal in a metal deposition chamber. Metal wire forming method of a semiconductor device comprising the step of depositing. 제1항에서, 상기 제 1금속으로 알루미늄 또는 알루미늄 합금을 사용하는 반도체 소자의 금속 배선 형성 방법.The method of claim 1, wherein aluminum or an aluminum alloy is used as the first metal. 제1항에서, 상기 제 2금속을 1000Å이상의 두께로 증착하는 반도체 소자의 금속 배선 형성 방법.The method of claim 1, wherein the second metal is deposited to a thickness of at least 1000 GPa. 제3항에서, 상기 제 2금속으로 알루미늄 또는 알루미늄의 합금을 사용하며 상기 제 2금속을 증착하기 전에 550℃이하의 온도로 냉각시키는 반도체 소자의 금속 배선 형성 방법.The method of claim 3, wherein aluminum or an alloy of aluminum is used as the second metal and is cooled to a temperature of 550 ° C. or lower before depositing the second metal. 제1항에서, 상기 장벽 금속막은 티타늄과 질화티타늄을 연속으로 증착하여 형성하며, 상기 티타늄은 500Å이하로 증착하는 반도체 소자의 금속 배선 형성 방법.The method of claim 1, wherein the barrier metal film is formed by continuously depositing titanium and titanium nitride, and the titanium is deposited at 500 kW or less. 제5항에서, 상기 질화 티타늄은 500∼1500Å의 두께로 증착하는 반도체 소자의 금속 배선 형성 방법.The method of claim 5, wherein the titanium nitride is deposited to a thickness of 500 to 1500 kW. 제6항에서, 상기 제2 금속으로 알루미늄 또는 알루미늄의 합금을 사용하는 반도체 소자의 금속 배선 형성 방법.The method for forming metal wirings of a semiconductor device according to claim 6, wherein aluminum or an alloy of aluminum is used as the second metal. 제7항에서, 상기 제2 금속을 증착하기 전에 550℃ 이하의 온도로 냉각시키는 반도체 소자의 금속 배선 형성 방법.The method of claim 7, wherein the second metal is cooled to a temperature of about 550 ° C. or less before the second metal is deposited. 제1항에서, 상기 장벽 금속막은 티타늄과 질화 티타늄을 연속적으로 증착하여 형성하는 반도체 소자의 금속 배선 형성 방법.The method of claim 1, wherein the barrier metal film is formed by continuously depositing titanium and titanium nitride. 제9항에서, 상기 티타늄은 500Å 이하로 증착하는 반도체 소자의 금속 배선 형성 방법.The method of claim 9, wherein the titanium is deposited at 500 kW or less. 제9항에서, 상기 질화 티타늄은 500∼1500Å의 두께로 증착하는 반도체 소자의 금속 배선 형성 방법.The method of claim 9, wherein the titanium nitride is deposited to a thickness of 500 to 1500 kW. 제1항에서, 상기 장벽 금속 증착 후 실시하는 열처리는 400∼500℃의 온도에서 실시하는 반도체 소자의 금속 배선 형성 방법.The method of claim 1, wherein the heat treatment performed after the barrier metal deposition is performed at a temperature of 400 to 500 ° C. 7.
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JPH04171940A (en) * 1990-11-06 1992-06-19 Fujitsu Ltd Manufacture of semiconductor device
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JPH04171940A (en) * 1990-11-06 1992-06-19 Fujitsu Ltd Manufacture of semiconductor device
JPH04236450A (en) * 1991-01-21 1992-08-25 Fujitsu Ltd Manufacture of semiconductor device

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