KR100220933B1 - Forming method for metal wiring of semiconductor device - Google Patents
Forming method for metal wiring of semiconductor device Download PDFInfo
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- KR100220933B1 KR100220933B1 KR1019950018889A KR19950018889A KR100220933B1 KR 100220933 B1 KR100220933 B1 KR 100220933B1 KR 1019950018889 A KR1019950018889 A KR 1019950018889A KR 19950018889 A KR19950018889 A KR 19950018889A KR 100220933 B1 KR100220933 B1 KR 100220933B1
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- aluminum alloy
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- alloy layer
- forming
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
Abstract
본 발명은 반도체 소자의 금속배선 형성 방법에 관한 것으로, 반도체기판 상부에 콘택홀을 형성하고, 콘택홀의 표면에 접착층을 형성하고, 그상부에 제1알루미늄 합금층을 저온에서 일정 두께 증착하고, 열처리 공정을 실시한후, 그상부에 제2알루미늄 합금층을 고온에서 증착하여 알루미늄 합금층의 층덮힘을 개선하여 배선의 신뢰성을 향상한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, comprising forming a contact hole on an upper surface of a semiconductor substrate, forming an adhesive layer on a surface of the contact hole, depositing a first aluminum alloy layer at a predetermined thickness thereon at a low temperature, and heat treatment After performing the process, the second aluminum alloy layer is deposited thereon at a high temperature to improve the layer covering of the aluminum alloy layer to improve the reliability of the wiring.
Description
제1(a)도 내지 제1(d)도는 종래의 기술의 실시예들에 따른 금속배선이 형성된 상태의 단면도.1 (a) to 1 (d) is a cross-sectional view of a metal wiring formed in accordance with embodiments of the prior art.
제2(a)도 내지 제2(d)도는 본 발명의 제1실시예에 따라 반도체 소자의 금속배선 형성과정을 도시한 단면도.2 (a) to 2 (d) are cross-sectional views illustrating a process of forming metal wirings in a semiconductor device according to a first embodiment of the present invention.
제3도는 본 발명의 제2실시예에 따라 반도체 소자의 금속배선이 형성된 것을 도시한 단면도.3 is a cross-sectional view showing that metal wirings of a semiconductor device are formed according to a second embodiment of the present invention.
제4도는 본 발명의 제3실시예에 따라 반도체 소자의 금속배선이 형성된 것을 도시한 단면도.4 is a cross-sectional view showing that metal wiring of a semiconductor device is formed in accordance with a third embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1,11,21,31,41 : 도전층 2,12,22,32,42 : 절연층1,11,21,31,41: conductive layer 2,12,22,32,42: insulating layer
3,13,23,33 : 접착층 4,34,44 : 제1알루미늄 합금층3,13,23,33: adhesive layer 4,34,44: first aluminum alloy layer
5,35,45 : 제2알루미늄 합금층 6,16,26,36,46 : 반사 방지층5,35,45: Second aluminum alloy layer 6,16,26,36,46: Antireflection layer
7 : 콘택홀 39 : 텅스텐 매립층7: contact hole 39: tungsten buried layer
본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로 특히, 일정두께의 알루미늄 합금층을 저온에서 증착하고, 일정두께의 알루미늄 합금층을 고온 증착하여 알루미늄 합금의 층덮힘을 개선하여 배선의 신뢰성을 향상하는 반도체 소자의 금속배선 형성방법에 관한 것이다.The present invention relates to a method for forming a metal wiring of a semiconductor device, in particular, by depositing a certain thickness aluminum alloy layer at a low temperature, by depositing a certain thickness aluminum alloy layer at high temperature to improve the layer covering of the aluminum alloy to improve the reliability of the wiring A metal wiring forming method of a semiconductor device.
최근에 반도체 소자가 고집적화되어감에 따라서 콘택홀도 미세화되어, 알루미늄 합금의 층덮힘은 악화되고 배선단절 현상이 일어나 배선의 신뢰성이 나빠진다.In recent years, as semiconductor devices have been highly integrated, contact holes have also been miniaturized, so that the layer covering of the aluminum alloy is deteriorated and wiring breakage occurs, resulting in poor wiring reliability.
종래에는 이를 방지하기 위하여 저온에서 알루미늄 합금증착을 시도하였으나 배선의 스트레스-마이그레이션(stress-migration) 현상을 심화시켜 실제로 적용하기가 힘들었고, 고온에서 알루미늄 합금층을 증착하는 경우 알루미늄 합금층이 단선되는 현상이 일어났다.Conventionally, in order to prevent this, aluminum alloy deposition was attempted at a low temperature, but it was difficult to actually apply the stress-migration phenomenon of the wiring, and when the aluminum alloy layer was deposited at a high temperature, the aluminum alloy layer was disconnected. This happened.
또한, 저온과 고온의 중간의 온도인 약 300근처의 온도에서 알루미늄 합금을 증착하여도 층덮힘이 좋지않아 배선의 신뢰성에 악영향을 미치고 있다.Moreover, about 300 which is the temperature between the low temperature and high temperature Deposition of aluminum alloy at a nearby temperature also has a poor layer covering, which adversely affects the reliability of the wiring.
종래의 반도체 소자의 금속배선 형성방법을 설명하면 다음과 같다.The metal wiring forming method of the conventional semiconductor device will be described below.
제1(a)도는 종래 기술의 제1실시예로서, 알루미늄 합금층을 저온에서 증착한 경우의 단면도이며, 도전층(11)의 상부에 절연층(12)을 증착하고, 콘택홀용 마스크로 상기 절연층(12)을 도전층(11)이 노출될 때까지 식각하여 콘택홀을 형성하고, 전체구조의 상부에 Ti/TiN 등으로 접착층(13)을 증착하고, 전체 구조의 상부에 저온으로 알루미늄 합금층(14)을 증착하고, 상기 알루미늄 합금층(14)의 표면에 반사방지층(16)을 형성한 것이다.FIG. 1 (a) is a cross-sectional view when the aluminum alloy layer is deposited at a low temperature as a first embodiment of the prior art, and the insulating layer 12 is deposited on the conductive layer 11, and the contact hole mask is used. The insulating layer 12 is etched until the conductive layer 11 is exposed to form contact holes, and the adhesive layer 13 is deposited on the upper part of the entire structure by Ti / TiN or the like, and the aluminum is lowered on the upper part of the entire structure. The alloy layer 14 is deposited, and the antireflection layer 16 is formed on the surface of the aluminum alloy layer 14.
그러나, 상기와 같이 알루미늄 합금층을 저온에서 증착하는 경우는 알루미늄 합금층의 스텝 커버리지가 콘택홀의 저부와 상부에 심한 차이가 발생하고, 그 상부에 증착되는 반사방지층이 콘택홀의 저부면에서는 거의 증착되지 않는 문제점이 있다.However, when the aluminum alloy layer is deposited at a low temperature as described above, the step coverage of the aluminum alloy layer is greatly different between the bottom and the top of the contact hole, and the anti-reflection layer deposited on the upper part is hardly deposited on the bottom surface of the contact hole. There is a problem.
제1(b)도는 종래 기술의 제2실시예로서, 알루미늄 합금층을 고온에서 증착한 경우의 단면도이며, 도전층(21)의 상부에 절연층(22)을 증착하고, 콘택홀용 마스크로 상기 절연층(22)을 식각하여 콘택홀을 형성한 다음, 전체 구조의 상부에 접착층(23)을 형성하고, 전체 구조의 상부에 고온으로 알루미늄 합금층(24)을 증착하고, 그 상부에 반사 방지층(26)을 형성한 것으로, 알루미늄 합금층이 콘택홀의 측벽에서 끊어져서 증착됨을 도시한다. 그로인하여 알루미늄 합금층이 콘택 저부의 도전층에 전기적으로 접속되어 있지 않고, 반사방지층도 제대로 증착되지 않는 문제점이 있다.FIG. 1 (b) is a cross-sectional view when the aluminum alloy layer is deposited at a high temperature as a second embodiment of the prior art, and the insulating layer 22 is deposited on the conductive layer 21, and the contact hole mask is used. The insulating layer 22 is etched to form a contact hole, and then an adhesive layer 23 is formed on the upper portion of the entire structure, and an aluminum alloy layer 24 is deposited at a high temperature on the upper portion of the entire structure, and an antireflection layer is formed thereon. (26) is formed, which shows that the aluminum alloy layer is broken and deposited on the sidewall of the contact hole. Therefore, there is a problem that the aluminum alloy layer is not electrically connected to the conductive layer of the contact bottom portion, and the antireflection layer is also not deposited properly.
제1(c)도는 종래 기술의 제3실시예로서, 콘택홀에 텅스텐 매립층을 형성한 다음, 그상부에 알루미늄 합금층을 증착한 단면도이며, 도전층(31)의 상부에 절연층(32)을 형성하고, 상기 절연층(32)의 일정부분이 제거되어 콘택홀을 형성하고, 콘택홀의 표면과 절연층(32)의 상부면에 접차층(33)을 형성하고, 상기 콘택홀에 매립되는 텅스텐 매립층(39)을 형성하고, 그 상부에 알루미늄 합금층(34)을 물리기상 증착(Physical Vapor Deposition; 이하 PVD라 칭함) 방법 또는 화학기상증착(Chemical Vapor Deposition;이하 CVD라 칭함) 방법에 의해 증착한 다음, 그 상부에 반사 방지층(26)을 증착하게 되는데, 층덮힘이 좋지 않고, 콘택홀의 상부에서 알루미늄 합금층에 요부가 발생되어 후속 공정이 어려워지는 문제점이 있다.FIG. 1 (c) is a cross-sectional view of a third embodiment of the prior art, in which a tungsten buried layer is formed in a contact hole and an aluminum alloy layer is deposited thereon, and the insulating layer 32 is formed on the conductive layer 31. And a predetermined portion of the insulating layer 32 is removed to form a contact hole, and a contact layer 33 is formed on a surface of the contact hole and an upper surface of the insulating layer 32 and embedded in the contact hole. The tungsten buried layer 39 is formed, and the aluminum alloy layer 34 is formed thereon by a physical vapor deposition (PVD) method or a chemical vapor deposition (hereinafter, CVD) method. After the deposition, the anti-reflection layer 26 is deposited on the upper layer, but the layer covering is not good, and recesses are formed in the aluminum alloy layer on the upper portion of the contact hole, thereby making it difficult to perform the subsequent process.
제1(d)도는 종래 기술의 제4실시예로서,단차비가 낮은 콘택홀에서 직접 알루미늄 합금층을 증착한 단면도로서, 도전층(41)에 절연층(42)을 증착하고, 절연층(42)의 일정부분을 식각하여 콘택홀을 형성하고, 저온으로 알루미늄 합금층(44)을 물리기상증착법에 의해 증착하고, 그상부에 반사방지층(46)을 증착하게 되는데, 알루미늄 합금층의 층덮힘이 좋지 않은 문제점이 있다.FIG. 1 (d) is a fourth embodiment of the prior art, which is a cross-sectional view of directly depositing an aluminum alloy layer in a contact hole having a low step ratio. The insulating layer 42 is deposited on the conductive layer 41, and the insulating layer 42 is deposited. A portion of the etch is etched to form a contact hole, and the aluminum alloy layer 44 is deposited by physical vapor deposition at a low temperature, and an antireflection layer 46 is deposited thereon. There is a bad problem.
따라서, 본 발명의 목적은 상기 문제점을 해결하기 위하여 알루미늄 합금층을 2차에 걸쳐 증착하되 제1알루미늄 합금층을 저온에서 증착하고, 그 상부에 고온에서 제2알루미늄층을 증착하여 금속배선의 층 덮힘을 향상시키고 신뢰성을 향상하는 반도체 소자의 금속배선 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to deposit the aluminum alloy layer over a second time in order to solve the above problems, the first aluminum alloy layer is deposited at a low temperature, the second aluminum layer is deposited at a high temperature on top of the metal wiring layer It is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device to improve the covering and improve the reliability.
상기 목적을 달성하기 위하여 본 발명의 반도체 소자의 금속배선 형성방법은, 도전층의 상부에 절연층을 증착하고 콘택홀을 형성하는 단계와,In order to achieve the above object, the method for forming a metal wiring of the semiconductor device of the present invention comprises the steps of: depositing an insulating layer on top of the conductive layer and forming contact holes;
전체 구조에 얇은 두께의 접착층을 형성하는 단계와,Forming a thin adhesive layer on the overall structure;
상기 접착층의 표면에 저온에서 제1알루미늄 합금층을 형성하는 단계와, 상기 제1알루미늄 합금층을 열처리하는 단계와, 상기 제1알루미늄 합금층 표면에 고온에서 제2알루미늄 합금층을 증착하는 단계를 포함하는 것을 특징으로 한다.Forming a first aluminum alloy layer on the surface of the adhesive layer at a low temperature, heat treating the first aluminum alloy layer, and depositing a second aluminum alloy layer on the surface of the first aluminum alloy layer at a high temperature. It is characterized by including.
이하, 첨부된 도면을 참조하여 본 발명의 적합한 실시예에 대한 상세한 설명을 하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
제2(a)도 내지 제2(d)도는 본 발명의 제1실시예에 따라 반도체 소자의 금속배선을 제조하는 공정도이다.2 (a) to 2 (d) are process diagrams for manufacturing the metal wiring of the semiconductor device according to the first embodiment of the present invention.
제2(a)도는 도전층(1)의 상부에 절연층(2)을 증착하고, 콘택홀용 마스크를 이용하여 상기 도전층(1)이 들어날 때까지 상기 절연층(2)을 식각하여 콘택홀(7)을 형성하고, 전체 구조의 상부에 접착층(3), 예를들어 Ti 또는 TiN 층을 형성한 상태를 도시한 단면도이다.In FIG. 2 (a), the insulating layer 2 is deposited on the conductive layer 1, and the insulating layer 2 is etched by using a contact hole mask until the conductive layer 1 enters the contact. It is sectional drawing which shows the state in which the hole 7 was formed and the adhesive layer 3, for example, Ti or TiN layer was formed in the upper part of the whole structure.
이때, 접착층(3)은 PVD 또는 CVD 법을 이용하여 1000이하의 두께로 증착한 다음, 300600사이의 온도에서 열처리한다.At this time, the adhesive layer 3 is 1000 by PVD or CVD method. Deposited to a thickness of less than 300 600 Heat treatment at temperature between.
제2(b)도는 25150사이의 비교적 저온이고 510KW의 전력과 0.54.0mTorr의 압력에서 전체 구조의 상부에 제1알루미늄 합금층(4)을 증착한 상태를 나타낸 단면도이다. 이때 제1알루미늄 합금(4)의 증착 두께는 알루미늄 합금층의 전체 두께의 1/21/3정도로 한다.Figure 2 (b) is 25 150 Relatively low temperature between 5 10KW power and 0.5 It is sectional drawing which shows the state which deposited the 1st aluminum alloy layer 4 on the upper part of the whole structure at the pressure of 4.0 mTorr. At this time, the deposition thickness of the first aluminum alloy 4 is 1/2 of the total thickness of the aluminum alloy layer. It is about 1/3.
상기 제1알루미늄 합금층(4)은 비교적 열 에너지를 적게 가지고 있어 콘택내부에서 이동하지 못하고, 고착된 상태이고, 아주 작은 결정입자를 가지고 있다.The first aluminum alloy layer 4 has relatively low thermal energy and cannot move inside the contact, is in a fixed state, and has very small crystal grains.
제2(c)도는 상기 저온 증착된 제1알루미늄 합금층(4)을 가열하기 위하여 다른 알루미늄 합금 증착 챔버로 이동하여 가열하거나 동일한 챔버에서 200400의 온도에서 웨이퍼를 60180초 동안 열처리를 실시하여 결정입자가 커지고 모서리부에서 완만한 곡선으로 된 제1알루미늄 합금층(4)을 형성한 상태를 나타낸 단면도이다.FIG. 2 (c) moves to another aluminum alloy deposition chamber to heat the low temperature deposited first aluminum alloy layer 4 or 200 in the same chamber. 400 Wafer at a temperature of 60 It is sectional drawing which showed the state which formed the 1st aluminum alloy layer 4 which became large crystal | crystallization and made a gentle curve in a corner part by heat processing for 180 second.
제2(d)도는 진공파괴가 없이 상기 제1알루미늄 합금층(4)의 표면에 동일한 재료의 제2알루미늄 합금층(5)을 200450의 온도와 10KW 이하의 전력과 4.0mTorr이하의 압력에서 증착한후, 그상부면에 반사방지막(6)을 증착한 단면도로서, 상기 제2알루미늄 합금층(5)은 고온에서 증착하기 때문에 증착되는 알루미늄층의 플로우 현상이 잘 일어나서 콘택홀의 상부면에서 알루미늄 합금의 쇼트되는 현상이 발생하지 않는다.2 (d) or 200, the second aluminum alloy layer 5 of the same material is formed on the surface of the first aluminum alloy layer 4 without vacuum breaking. 450 After the deposition at a temperature of 10KW or less and a pressure of 4.0mTorr or less, the anti-reflection film 6 is deposited on the upper surface thereof. The second aluminum alloy layer 5 is deposited because it is deposited at a high temperature. The flow phenomenon of the aluminum layer occurs well, so that the phenomenon of shortening of the aluminum alloy does not occur at the upper surface of the contact hole.
참조로, 제2알루미늄 합금층을 증착하는 온도와 전력은 콘택홀의 크기와 단차에 따라 변할수도 있다.For reference, the temperature and power for depositing the second aluminum alloy layer may vary depending on the size and step of the contact hole.
상기 반사방지층(6)은 예를들어 TiN, Si 또는 SiON으로 형성한다.The antireflection layer 6 is formed of TiN, Si or SiON, for example.
따라서, 콘택 내부에 고착된 제1알루미늄 합금층(4)은 핵생성층이 되고, 고온의 제2알루미늄 합금층(5)을 증착하게 됨으로 인하여 알루미늄 합금층이 끊어지는 문제는 해결할 수 있다.Accordingly, the first aluminum alloy layer 4 fixed inside the contact becomes a nucleation layer, and the problem of breaking the aluminum alloy layer due to the deposition of the high temperature second aluminum alloy layer 5 can be solved.
제3도는 본 발명의 제2실시예에 따라 콘택홀에 텅스텐 매립층을 형성한 다음, 그상부에 알루미늄 합금층을 증착한 단면도로서, 도전층(31)의 상부에 절연층(32)을 형성하고, 상기 절연층(32)의 일정부분이 제거되어 콘택홀을 형성하고,콘택홀의 표면과 절연층(32)의 상부면에 접착층(33)을 형성하고, 상기 콘택홀에 매립되는 텅스텐 매립층(39)을 형성한다. 그리고, 그상부에 25150의 온도와, 510KW 사이의 전력과, 0.54.0m Torr의 압력에서 제1알루미늄 합금층(34')을 형성하고, 동일한 챔버에서 200400의 온도에서 웨이퍼를 60180초 동안 열처리를 실시하여 결정입자가 커지고 모서리부에서 완만한 곡선으로 된 제1알루미늄 합금층(34')을 형성한 다음, 200400의 온도와 10KW 이하의 전력과 4.0m Torr이하의 압력에서 제2알루미늄 합금층(35)을 증착하고, 그상부에 반사방지막(36)을 형성한 단면도이다.FIG. 3 is a cross-sectional view of forming a tungsten buried layer in a contact hole and then depositing an aluminum alloy layer on the contact hole according to the second embodiment of the present invention, and forming an insulating layer 32 on the conductive layer 31. A portion of the insulating layer 32 is removed to form a contact hole, an adhesive layer 33 is formed on the surface of the contact hole and the upper surface of the insulating layer 32, and the tungsten buried layer 39 buried in the contact hole is formed. ). And 25 on top of it 150 With the temperature of 5 Power between 10KW, 0.5 A first aluminum alloy layer 34 'was formed at a pressure of 4.0 m Torr and 200 in the same chamber. 400 Wafer at a temperature of 60 Heat treatment for 180 seconds to form a first aluminum alloy layer 34 'having large crystal grains and a smooth curve at the corners, and then 200 400 The second aluminum alloy layer 35 is deposited at a temperature of 10 kW or less and a power of 4.0 m Torr or less, and an antireflection film 36 is formed thereon.
그로인하여 제1 및 제2알루미늄 합금(34',35)으로 이루어진 알루미늄 합금의 층덮힘을 향상 시킬수가 있다.As a result, it is possible to improve the layer covering of the aluminum alloy composed of the first and second aluminum alloys 34 ′ and 35.
제4도는 본 발명의 제3실시예에 따라 단차비가 낮은 콘택홀에서 알루미늄 합금층을 증착한 단면도로서, 도전층(41)에 절연층(42)을 증착하고, 절연층(42)의 일정부분을 식각하여 콘택홀을 형성하고, 25150의 온도와, 510KW사이의 전력과, 0.54.0m Torr의 압력에서 제1알루미늄 합금층(44')을 형성하고, 동일한 챔버에서 200400의 온도에서 웨이퍼를 60180초 동안 열처리를 실시하여 결정입자가 커지고 모서리부에서 완만한 곡선으로 된 제1알루미늄 합금층(44')을 형성한다음, 200400의 온도와 10KW 이하의 전력과 4.0m Torr이하의 압력에서 제2알루미늄 합금층(45')을 증착하고, 그 상부에 반사방지막(46) 예를들어 TiN,Si 또는 SiON을 형성한 단면도이다.4 is a cross-sectional view of depositing an aluminum alloy layer in a contact hole having a low step ratio according to a third embodiment of the present invention. The insulating layer 42 is deposited on the conductive layer 41, and a predetermined portion of the insulating layer 42 is formed. Etching to form a contact hole, 25 150 With the temperature of 5 Power between 10 kW, 0.5 A first aluminum alloy layer 44 'was formed at a pressure of 4.0 m Torr and 200 in the same chamber. 400 Wafer at a temperature of 60 Heat treatment for 180 seconds to form a first aluminum alloy layer 44 'having large crystal grains and a gentle curve at the corners, and then 200 400 The second aluminum alloy layer 45 'is deposited at a temperature of 10 kW or less and a power of 4.0 m Torr or less, and an antireflection film 46, for example, TiN, Si or SiON is formed thereon.
상술한 바와 같이 본 발명에 의해 알루미늄 합금층을 형성하는 방법은 일정두께의 알루미늄 합금층을 저온에서 형성하여 콘택 내부에 고착시키고, 나머지 일정두께를 고온에서 증착하여 층덮힘을 개선하여 배선의 신뢰성을 향상하는 이점이 있다.As described above, in the method of forming an aluminum alloy layer according to the present invention, an aluminum alloy layer having a predetermined thickness is formed at a low temperature to be fixed to the inside of a contact, and the remaining constant thickness is deposited at a high temperature to improve layer covering to improve wiring reliability. There is an advantage to improve.
Claims (9)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950018889A KR100220933B1 (en) | 1995-06-30 | 1995-06-30 | Forming method for metal wiring of semiconductor device |
| TW085107810A TW302512B (en) | 1995-06-30 | 1996-06-28 | Method for forming metal wiring of semiconductor device |
| CN96106744A CN1076122C (en) | 1995-06-30 | 1996-07-01 | Method for forming metal wiring of semi-conductor device |
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| KR1019950018889A KR100220933B1 (en) | 1995-06-30 | 1995-06-30 | Forming method for metal wiring of semiconductor device |
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| KR970003513A KR970003513A (en) | 1997-01-28 |
| KR100220933B1 true KR100220933B1 (en) | 1999-09-15 |
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| KR (1) | KR100220933B1 (en) |
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| JP4387654B2 (en) * | 2002-10-10 | 2009-12-16 | パナソニック株式会社 | Semiconductor device and manufacturing method thereof |
| CN101673678B (en) * | 2008-09-09 | 2011-03-16 | 中芯国际集成电路制造(北京)有限公司 | Growing method of aluminum layer and metal-insulator-metal board |
| GB201102673D0 (en) * | 2011-02-16 | 2011-03-30 | Spp Process Technology Systems Uk Ltd | Methods of depositing aluminium layers |
| US9670574B2 (en) | 2011-02-16 | 2017-06-06 | Spts Technologies Limited | Methods of depositing aluminium layers |
| CN105304510B (en) * | 2014-07-22 | 2018-05-08 | 北京北方华创微电子装备有限公司 | Aluminium film preparation method |
| KR102500941B1 (en) * | 2020-12-14 | 2023-02-16 | 주식회사 포스코 | Impeller wire drum stopper device |
| CN115547926B (en) * | 2022-12-02 | 2023-02-14 | 合肥晶合集成电路股份有限公司 | Manufacturing method of semiconductor structure and semiconductor structure |
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| EP0199030A3 (en) * | 1985-04-11 | 1987-08-26 | Siemens Aktiengesellschaft | Method for manufacturing a multilayer wiring for integrated semiconductor circuits having at least one aluminium alloy layer with a contact hole filling |
| DE69225082T2 (en) * | 1991-02-12 | 1998-08-20 | Matsushita Electronics Corp | Semiconductor device with improved reliability wiring and method of manufacture |
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| CN1076122C (en) | 2001-12-12 |
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