KR100209261B1 - Loc package - Google Patents

Loc package Download PDF

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Publication number
KR100209261B1
KR100209261B1 KR1019960022244A KR19960022244A KR100209261B1 KR 100209261 B1 KR100209261 B1 KR 100209261B1 KR 1019960022244 A KR1019960022244 A KR 1019960022244A KR 19960022244 A KR19960022244 A KR 19960022244A KR 100209261 B1 KR100209261 B1 KR 100209261B1
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South Korea
Prior art keywords
layer
tape
lead
semiconductor chip
tape member
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KR1019960022244A
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Korean (ko)
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KR980006156A (en
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최병선
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이해규
삼성항공산업주식회사
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Priority to KR1019960022244A priority Critical patent/KR100209261B1/en
Publication of KR980006156A publication Critical patent/KR980006156A/en
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Publication of KR100209261B1 publication Critical patent/KR100209261B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 도금층을 포함하는 리이드부; 상기 리이드부의 하부면 단부의 소정 영역에 걸쳐 형성되어 있으며, 접착증, 테이프층 및 접착층이 순차적으로 적층된 3층 구조의 테이프 부재; 상기 테이프 부재 하부에 접착된 반도체 칩; 및 상기 반도체 칩 하부에 형성된 방열층을 포함하는 LOC 패키지에 있어서, 상기 테이프층이 스틸인 것을 특징으로 하는 LOC(Lead On Chip) 패키지에 관한 것이다. 본 발명의 LOC 패키지는 테이프층으로서 스틸을 사용하기 때문에 테이프 버어 현상으로 인한 반도체 패키지의 불량 현상 및 크랙 발생이 일어나지 않으며, 리이드부와 테이프층 간의 공극 발생, 박리 현상 등이 일어나지 않는다. 따라서, 제품의 품질 향상 및 수율 증대를 기대할 수 있다.The present invention provides a semiconductor device comprising: a lead section including a plating layer; A tape member having a three-layer structure formed over a predetermined region of an end portion of a lower surface of the lead section and having an adhesive layer, a tape layer and an adhesive layer sequentially laminated; A semiconductor chip bonded to a lower portion of the tape member; And a heat dissipation layer formed below the semiconductor chip, wherein the tape layer is made of steel. Since the LOC package of the present invention uses steel as a tape layer, defects and cracks of the semiconductor package due to the tape burr phenomenon do not occur, and gap generation and peeling phenomena between the lead portion and the tape layer do not occur. Therefore, the quality of the product and the yield can be expected to increase.

Description

엘오씨(LOC) 패키지LOC package

제1도는 테이프 부재가 형성된 LOC(Lead On Chip)용 리이드 프레임의 정면도이다.1 is a front view of a lead frame for a lead on chip (LOC) in which a tape member is formed;

제2도는 반도체 칩이 고정된 LOC 패키지를 도시한 것으로서,FIG. 2 shows a LOC package in which a semiconductor chip is fixed,

제2(a)도는 리이드부가 은도금된 경우이고,The second portion (a) or the lead portion is silver-plated,

제2(b)도는 리이드부가 PPF (Pre-Plated Frame) 도금된 경우이다.FIG. 2 (b) shows a case where the lead portion is plated with PPF (Pre-Plated Frame).

* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS

11, 21 : 리이드부 13 : 테이프 부재11, 21: lid portion 13: tape member

22 : 은도금층 23 : PPF 도금층22: silver plated layer 23: PPF plated layer

24 : 몰드 25 : 골드 와이어24: mold 25: gold wire

26, 28 : 접착층 27 : 테이프층26, 28: adhesive layer 27: tape layer

29 : 테이프 부재 30 : 반도체 칩29: tape member 30: semiconductor chip

31 : 방열층31: Heat dissipation layer

본 발명은 LOC(Lead On Chip)용 리이드 프레임과 반도체 칩을 포함하는 LOC 패키지 및 그 제조방법에 관한 것으로서, 보다 상세하게는 테이프층으로서 스틸을 사용하여 테이핑 공정시 발생하는 테이프 버어현상 및 테이프층의 수분 흡수 현상을 방지함으로써 제품의 품질 및 수율을 향상시킨 LOC 패키지에 관한 것이다.The present invention relates to a LOC package including a lead frame for LOC (Lead On Chip) and a semiconductor chip and a method of manufacturing the LOC package. More particularly, The present invention relates to an LOC package that improves product quality and yield by preventing moisture absorption phenomenon of the LOC package.

리이드 프레임은 웨이퍼와 함께 반도체 패키지를 이루는 핵심요소로서, 반도체 패키지의 내부와 외부를 연결해 주는 도선(lead)역할과 반도체 칩을 지지해 주는 지지체 역할을 한다.The lead frame serves as a lead for connecting the inside and the outside of the semiconductor package and a support for supporting the semiconductor chip.

리이드 프레임은 통상적으로는 기억소자인 칩을 탑재하여 정적인 상태로 유지하여 주는 패드(Pad)와 , 칩을 외부회로에 연결해 주는 내부 리이드(Internal lead) 및 외부 리이드(External lead)를 포함하는 구조로 이루어진다.The lead frame generally includes a pad for holding a memory element and holding it in a static state and an internal lead and an external lead for connecting the chip to an external circuit. .

이와 같은 구조를 가지는 리이드 프레임은 통상 스탬핑(Stamping) 공정 또는 에칭(Etching) 공정에 의해 만들어진다.The lead frame having such a structure is usually formed by a stamping process or an etching process.

이중, 스탬핑 공정은 순차적으로 이송되는 프레스 금형장치를 이용하여 박판의 소재를 소정 형상으로 타발함으로써 리이드 프레임을 제조하는 방법으로서 대량 생산에 적합한 반면에 에칭 공정은 화학약품을 이용하여 국소 부위를 부식시킴으로써 제품을 형성하는 화학적 식각방법으로서, 소량생산에 주로 적용되고 있는 방법이다.The stamping process is suitable for mass production as a method of manufacturing a lead frame by punching a thin plate material into a predetermined shape by using a press die device which is sequentially transferred, while the etching process is a process of etching a local portion using a chemical agent This is a chemical etching method for forming a product, which is mainly applied to small-scale production.

전술한 스탬핑 공정 또는 에칭 공정에 따라 리이드 프레임을 제조한 다음에는 표면에 도포되어 있는 윤활유 또는 유기물질을 제거하고 와이어 본딩부를 은도금한다. 이때 은도금 대신에 팔라듐을 이용하여 PPF(Pre-Plated Frame)도금을 실시할 수도 있다.After manufacturing the lead frame according to the stamping process or the etching process, the lubricant or organic material applied on the surface is removed and the wire bonding portion is silver plated. At this time, PPF (Pre-Plated Frame) plating may be performed using palladium instead of silver plating.

이렇게 만들어진 리이드 프레임은 다른 부품, 예를 들면 기억소자인 반도체 칩 등과의 조립과정을 거쳐 패키지화 된다. 그런데, 칩과 패드이 접착시, 칩과 패드 사이에 내부 기공 및 기포가 형성되는 문제점이 있다. 이러한 문제점을 극복하기 위하여 칩과 패드 사이의 접착 면적을 최소화하기 위한 연구가 지속적으로 이루어졌고, 마침내는 패드를 완전히 제거한 LOC(Lead on Chip) 패키지 , COL(Chip on Lead) 패키지가 개발되었다.The lead frame thus formed is packaged through an assembly process with other components, for example, a semiconductor chip, which is a memory element. However, when the chip and the pad are bonded, there is a problem that internal pores and bubbles are formed between the chip and the pad. In order to overcome these problems, research was continuously carried out to minimize the area of adhesion between the chip and the pad. Finally, a lead on chip package (LOC) and a chip on lead (COL) package were developed.

이중, LOC 패키지를 제조함에 있어서는, 먼저 와이어 본딩시 리이드 프레임과 반도체 칩간의 도전성을 높이기 위하여 리이드부의 상부면 단부에 소정 길이만큼의 은도금층을 형성하거나 리이드부 전체를 팔라듐으로 도금하여 PPF 도금층을 형성한다. 이어서, 테이핑 공정을 실시한 다음 리아드부의 도금층고 반도체 칩 사이를 와이어 본딩한다. 계속해서 몰딩 공정을 실시한다.In order to increase the conductivity between the lead frame and the semiconductor chip during wire bonding, a silver plating layer of a predetermined length is formed on the upper end of the lead portion, or the entire lead portion is plated with palladium to form a PPF plating layer do. Then, the taping step is performed, and wire bonding is performed between the plating layer and the semiconductor chips of the lead portion. Subsequently, the molding process is carried out.

진술한 통상의 LOC 패키지 공정에서 상기 테이핑 공정은 리이드부의 변형을 방지하고 반도체 칩과 리이드부 사이를 절연시키면서 상기 반도체 칩을 리이드부에 고정하기 위하여 실시되는 매우 중요한 공정중의 하나이다. 테이핑 고정을 실시하기 위해서는 먼저 폴리이미드와 같은 수지 필름을 절단하여 테이프층을 만든다. 이어서, 아크릴계 또는 에폭시계 수지 등의 열경화성 수지로 이루어진 두 개의 접착층 사이에 상기 테이프층을 끼워넣은 3층 구조의 테이프 부재를 형성한 다음, 리이드부의 하부면 단부에 상기 테이프 부재를 접착시킨다. 이때, 테이프 부재가 다수의 리이드부에 걸쳐 형성될 경우, 보다 많은 양의 열이 방출되어 후속의 업셋(up-set) 공정에서 리이드부와 테이프 부재간에 박리가 일어나는 문제점이 있다. 따라서 상기 테이프 부재를 각각의 리이드부의 단부의 소정 영역에만 형성한다. 이어서, 상기 테이프 부재에 반도체 칩을 부착한다. 다음으로, 반도체 칩의 하부면에 상기 반도체 칩으로부터 발생하는 열을 방출시키기 위한 방열층을 형성한다.In the above-described conventional LOC packaging process, the taping process is one of the most important processes to prevent deformation of the lead portion and to fix the semiconductor chip to the lead portion while insulating the semiconductor chip from the lead portion. In order to fix taping, first a resin film such as polyimide is cut to make a tape layer. Next, a tape member having a three-layer structure in which the tape layer is sandwiched between two adhesive layers made of a thermosetting resin such as acrylic or epoxy resin is formed, and then the tape member is bonded to the lower surface end portion of the lead portion. At this time, when the tape member is formed over the plurality of the lid portions, a larger amount of heat is discharged, causing peeling between the lead portion and the tape member in a subsequent up-set process. Therefore, the tape member is formed only in a predetermined region of the end portion of each of the lead portions. Then, a semiconductor chip is attached to the tape member. Next, a heat dissipation layer for emitting heat generated from the semiconductor chip is formed on the lower surface of the semiconductor chip.

전술한 바와 같은 통상의 LOC 패키지 제조 방법에 있어서, 테이프층으로서 사용되는 폴리이미드와 같은 수지는 소재의 특성상 절단시 테이프 버어가 발생된다. 이러한 테이프 버어는 후속의 공정에서 문제점을 일으키는데, 즉 테이프 버어가 반도체 칩의 전극 상에 부착되어 있으면 와이어 본딩시 불량을 초래하게 되고, 몰딩 공정시 몰드 수지와 리드 프레임 간의 밀착성을 저하시켜 반도체 패키지에 크랙(crack)을 형성한다. 또한, 수지는 수분 흡수성을 가지기 때문에 테이프 부재와 리이드부 사이에 공극이 형성되거나 박리 현상이 발생할 수도 있다.In the conventional LOC package manufacturing method as described above, a resin such as polyimide used as a tape layer causes tape burrs when cutting due to the nature of the material. Such a tape burr causes a problem in the subsequent process. That is, if the tape burr is attached on the electrode of the semiconductor chip, it causes a defect in wire bonding, and the adhesion between the mold resin and the lead frame during the molding process is lowered, Thereby forming a crack. Further, since the resin has water absorbency, voids may be formed or peeling may occur between the tape member and the lid portion.

따라서, 본 발명자는 이러한 문제점을 극복하기 위하여 연구한 결과, 본 발명을 완성하게 되었다.Accordingly, the present inventors have conducted studies to overcome this problem, and as a result, the present invention has been completed.

즉, 본 발명의 목적의 테이프층으로서 수지 필름 대신 스틸을 사용함으로써 후속의 공정을 안정화시키고, 공극 발생, 박리 현상등이 일어나지 않는 LOC 패키지를 제공하는 것이다.That is, by using steel instead of a resin film as a tape layer for the purpose of the present invention, a subsequent process is stabilized and a LOC package in which void generation and peeling phenomenon do not occur does not occur.

본 발명의 목적을 달성하기 위하여, 본 발명에서는 도금층을 포함하는 리이드부; 상기 리이드부의 하부면 단부의 소정 영역에 걸쳐 형성되어 있으며, 접착층, 테이프층 및 접착층이 순차적으로 적층된 3층 구조의 테이프부재; 상기 테이프 부재의 하부에 접착된 반도체 칩 ; 및 상기 반도체 칩 하부에 형성된 방열층을 포함하는 LOC 패키지에 있어서, 상기 테이프층이 스틸인 것을 특징으로 하는 LOC 패키지가 제공된다.In order to accomplish the object of the present invention, the present invention provides a semiconductor device comprising: a lead section including a plating layer; A tape member having a three-layer structure formed over a predetermined region of an end portion of a lower surface of the lead section and having an adhesive layer, a tape layer, and an adhesive layer sequentially laminated; A semiconductor chip bonded to a lower portion of the tape member; And a heat dissipation layer formed under the semiconductor chip, wherein the tape layer is made of steel.

상기 본 발명의 LOC 패키지에 있어서, 상기 도금층을 은도금층 또는 PPF 도금층일 수 있다. 이때, 은도금층은 리이드부의 상부면 단부의 소정영역에 형성되며, PPF도금층은 리이드부 전면에 걸쳐 형성된다.In the LOC package of the present invention, the plating layer may be a silver plating layer or a PPF plating layer. At this time, the silver plating layer is formed in a predetermined region of the upper end of the lead portion, and the PPF plating layer is formed over the entire surface of the lead portion.

또한, 상기 방열층으로는 스틸이 주로 사용된다.In addition, steel is mainly used as the heat dissipation layer.

상기 본 발명의 LOC 패키지에 있어서, 테이프층으로서 사용되는 스틸은 절단시에 테이프 버어 현상을 수반하지 않기 때문에 후속의 와이어 본딩 공정이나 몰딩 공정에서 반도체 패키지의 불량이 초래되거나 크랙이 형성되지 않는다. 또한, 스틸은 수지와는 달리 수분 흡습성이 낮기 때문에 리이드부와 테이프 부재 간에 공극이 발생하거나 박리 현상이 일어나지도 않는다.In the LOC package of the present invention, the steel used as the tape layer does not involve a tape burr phenomenon at the time of cutting, so that defects or cracks are not formed in the semiconductor package in the subsequent wire bonding process or molding process. Also, unlike a resin, steel has low water hygroscopicity, so that voids are not generated or peeling occurs between the lead portion and the tape member.

이하, 도면을 들어 본 발명을 보다 상세히 설명하고자 한다.Hereinafter, the present invention will be described in more detail with reference to the drawings.

제1도는 테이프 부재가 형성된 LOC용 리이드 프레임의 정면도로서, 참조번호 11은 리이드부이고, 참조번호 13은 테이프 부재이다. 제1도를 참조하여 보면, 테이프 부재가 리이드부의 단부에 형성되어 있음을 알 수 있다. 이처럼 테이프 부재가 리이드 팁 형태로 형성되어 있기 때문에 테이프 부재로부터의 발열양이 적고, 리이드부와 테이프 부재 간에 공극이 발생하거나 박리가 일어나는 일이 현저하게 줄어든다.1 is a front view of a lead frame for a LOC in which a tape member is formed, in which reference numeral 11 is a lead portion and reference numeral 13 is a tape member. Referring to FIG. 1, it can be seen that the tape member is formed at the end of the lead portion. Since the tape member is formed in the shape of a lead tip, the amount of heat generated from the tape member is small, and the occurrence of voids or peeling between the lead portion and the tape member is remarkably reduced.

또한, 제2도는 반도체 칩이 고정된 LOC 패키지를 도시한 것으로서, (a)는 리이드부가 은도금된 경우이고, (b)는 리이드부가 PPF 도금된 경우이다. 제2도에 있어서, 참조번호 21은 리이드부를 참조번호 22는 은도금층을 , 참조번호 23은 PPF 도금층을 참조번호 24는 몰드를, 참조번호 25는 와이어를, 참조번호 26 및 28은 접착층을 참조번호 27은 테이프층을 참조번호 29는 테이프 부재를 참조번호 30은 반도체 칩을, 참조번호 31은 방열층을 각각 나타낸다.Fig. 2 (a) shows a case where the lead portion is silver-plated, and Fig. 2 (b) shows a case where the lead portion is plated with PPF. In FIG. 2, reference numeral 21 denotes a lead portion, 22 denotes a silver plating layer, 23 denotes a PPF plating layer, 24 denotes a mold, 25 denotes a wire, and 26 and 28 denote adhesive layers Reference numeral 27 denotes a tape layer, reference numeral 29 denotes a tape member, 30 denotes a semiconductor chip, and 31 denotes a heat dissipation layer.

상기와 같은 구조를 갖는 본 발명의 LOC 패키지는 테이프층으로서 스틸을 사용하기 때문에 테이프 버어로 인하여 발생될 수 있는 반도체 패키지의 불량, 크랙형성 등이 발생하지 않는다. 또한, 리이드부와 테이프 부재 간에 공극이 발생하거나 박리가 일어나지도 않는다. 즉, 테이프층으로서 스틸을 사용하면 제품의 품질 향상 및 수율 증대를 도모할 수 있다.Since the LOC package of the present invention having the above structure uses steel as a tape layer, defects and cracks in the semiconductor package, which may be caused by tape burrs, do not occur. Further, voids are not generated or peeled between the lead portion and the tape member. That is, if steel is used as the tape layer, the quality of the product and the yield can be increased.

Claims (3)

도금층을 포함하는 리이브부; 상기 리이드부의 하부면 단부의 소정 영역에 걸쳐 형성되어 있으며, 접착층, 테이프층 및 접착층이 순차적으로 적층된 3층 구조의 테이프 부재; 상기 테이프 부재 하부에 접착된 반도체 칩; 및 상기 반도체 칩 하부에 형성된 방열층을 포함하는 LOC 패키지에 있어서, 상기 테이프층이 스틸인 것을 특징으로 하는 LOC(Lead on Chip) 패키지.A rib portion including a plating layer; A tape member having a three-layer structure formed over a predetermined region of an end portion of a lower surface of the lead section and having an adhesive layer, a tape layer, and an adhesive layer sequentially laminated; A semiconductor chip bonded to a lower portion of the tape member; And a heat dissipation layer formed below the semiconductor chip, wherein the tape layer is made of steel. 제1항에 있어서, 상기 도금층이 은도금층 또는 PPF(Pre-Plated Frame)도금층인 것을 특징으로 하는 LOC 패키지.The LOC package according to claim 1, wherein the plating layer is a silver plating layer or a PPF (Pre-Plated Frame) plating layer. 제1항에 있어서, 상기 방열층이 스틸인 것을 특징으로 하는 LOC 패키지.The LOC package according to claim 1, wherein the heat-radiating layer is made of steel.
KR1019960022244A 1996-06-19 1996-06-19 Loc package KR100209261B1 (en)

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KR1019960022244A KR100209261B1 (en) 1996-06-19 1996-06-19 Loc package

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KR100209261B1 true KR100209261B1 (en) 1999-07-15

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