KR0175414B1 - Method for forming contact hole in semiconductor device - Google Patents
Method for forming contact hole in semiconductor device Download PDFInfo
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- KR0175414B1 KR0175414B1 KR1019950023876A KR19950023876A KR0175414B1 KR 0175414 B1 KR0175414 B1 KR 0175414B1 KR 1019950023876 A KR1019950023876 A KR 1019950023876A KR 19950023876 A KR19950023876 A KR 19950023876A KR 0175414 B1 KR0175414 B1 KR 0175414B1
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- contact hole
- insulating film
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- semiconductor device
- rtp
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 claims abstract description 5
- 238000000206 photolithography Methods 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 13
- 238000001312 dry etching Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims 1
- 239000002184 metal Substances 0.000 abstract description 18
- 238000000151 deposition Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 3
- 238000009826 distribution Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 21
- 239000012535 impurity Substances 0.000 description 6
- 239000005380 borophosphosilicate glass Substances 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000009413 insulation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Abstract
본 발명은 반도체 제조 방법에 관한 것으로서, 반도체 기판에 다층의 절연막을 형성하고, 제1, 제2사진식각의 공정을 통하여 콘택홀을 형성하고, 금속을 증착하기 이전에 RTP를 이용한 리플로우를 시킴으로써 완만한 경사면의 콘택홀 프로파일을 형성함으로써 향당된 스텝 커버리지를 획득하게되어 금속배선의 신뢰성을 향상시키고, 각 콘택 홀의 스텝 커버리지 산포가 감소하는 효과를 가지는 반도체 장치의 콘택 홀 형성 방법이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor, comprising forming a multilayer insulating film on a semiconductor substrate, forming a contact hole through a first and second photolithography process, and reflowing using RTP before depositing a metal. A method for forming a contact hole in a semiconductor device having an effect of obtaining enhanced step coverage by forming a contact hole profile of a gentle inclined surface, improving reliability of metal wiring, and reducing step coverage distribution of each contact hole.
Description
제1도의 (a) 내지 (c)는 종래의 반도체 장치의 콘택 홀 형성 방법을 그 공정 순서에 따라 도시한 단면도이고,(A)-(c) of FIG. 1 is sectional drawing which shows the contact hole formation method of the conventional semiconductor device according to the process sequence,
제2도의 (a) 내지 (c)는 본 발명에 의한 반도체 장치의 콘택 홀 형성 방법을 그 공정 순서에 따라 도시한 단면도이다.2A to 2C are cross-sectional views showing a method for forming a contact hole in a semiconductor device according to the present invention in accordance with the order of the steps thereof.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10, 110 : 반도체 기판 12, 112 : 불순물 확산 영역10, 110: semiconductor substrate 12, 112: impurity diffusion region
14,114 : 콘택 홀 20, 120:도핑하지 않은 저온 산화막14,114: contact holes 20, 120: undoped low temperature oxide film
30,130 : 도핑된 절연막 40,140 : 식각 속도가 빠른 제1 절연막30,130: doped insulating film 40,140: first insulating film with high etching speed
50,150 : 식각 속도가 도핑된 절연막과 같은 제2절연막50,150: second insulating film such as an insulating film doped with an etching rate
60,160 : 감광막 패턴 70,170 : 금속막60,160 photosensitive film pattern 70,170 metal film
본 발명은 반도체 장치의 제조 방법에 관한 것으로서, 더욱 상세하게는, 반도체 장치의 콘택 홀의 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device.
소자가 미소화됨에 따라 2차원적으로 배치한 소자가 칩 위에 차지하는 비율은 저하되고 배선 영역은 증대된다.As the element becomes smaller, the proportion of two-dimensionally disposed elements on the chip decreases and the wiring area increases.
미세 가공이 가능해도 배선 저항이나 콘택트 저항의 영향이 커져 배선의 미세화를 대폭 발전시킬 수는 없다. 그러므로 초고집적의 칩 기능은 실질적으로 배선수에 따라서 제한되고 이것을 해결하기 위해서는 배선의 다층화가 효과적이다. 또한 배선이 다층화됨에따라, 금속 배선을 절연시키기 위한 절연 물질이 다층으로 형성된다.Even if the microfabrication is possible, the influence of the wiring resistance and the contact resistance becomes large, and the refinement of the wiring cannot be greatly developed. Therefore, the ultra-high integration chip function is substantially limited according to the number of wirings, and in order to solve this problem, multilayering of wirings is effective. In addition, as the wiring is multilayered, an insulating material for insulating the metal wiring is formed in multiple layers.
반도체 장치가 고집적화에 따라 콘택 홀의 크기가 0.5㎛ 이하로 감소하게 되고, 이에 따라 콘택 홀의 애스팩트(aspect) 비가 증가하여, 후속 공정시 콘택 홀 내부에서의 금속과 유전체 막의 접촉을 어렵게 하고 금속 스텝 커버리지(step coverage)를 감소시켜 금속 배선의 불량이 발생한다.As the semiconductor device is highly integrated, the size of the contact hole is reduced to 0.5 μm or less, thereby increasing the aspect ratio of the contact hole, which makes it difficult to contact the metal and the dielectric film inside the contact hole during subsequent processing, and the metal step coverage. (step coverage) is reduced, so that defective metal wiring occurs.
이를 해결하기 위해 일반적으로 PMD(Poly-Metal Dielectric) 물질로써 단층의 BPSG(Borophosphsilicate glass)또는 서로 다른 농도 프로파일을 갖는 다층의 BPSG 를 연속증착한 후 리틀로우하여 평탄화하고, 이후에 습식 식각과 건식 식각을 통하여 원하는 콘택 프로파일을 형성한다.In order to solve this problem, a single layer of BPSG (Borophosphsilicate glass) or a multi-layer BPSG having different concentration profiles is continuously deposited and then low-lowed to be flattened by a poly-metal dielectric (PMD) material, followed by wet etching and dry etching. To form the desired contact profile.
콘택 홀의 프로파일을 개선하기 위한 기술로는 미국 특허 제 5041397호에 의한 방법으로 기판 상에 층간 절연막으로써 하부로부터 상부로 갈수록 인의 농도가 증가하도록 다층의 PSG 를 형성한 후 습식 식각과 건식 식각을 수행하여 패터닝하는 방법과, 대한민국 특허 출원된 출원번호 제 94-13840호에 의한 방법으로 농도가 다른 BPSG 상하 막질 사이에 형성하여 리플로우시킨 후 식각 속도 차이를 이용하여 농도가 다른 영역에서 보다 양호한 콘택 프로파일을 얻는 방법이 있다.As a technique for improving the contact hole profile, a method according to US Pat. BPSG phases with different concentrations by patterning and by the method according to Korean Patent Application No. 94-13840 There is a method of obtaining a better contact profile in regions having different concentrations by using etching rate differences after forming and reflowing between lower layers.
그러면, 첨부한 도면을 참고로 하여 반도체 장치의 콘택 홀 형성 방법에 대하여 더욱 상세하게 설명한다.Next, a method of forming a contact hole in a semiconductor device will be described in more detail with reference to the accompanying drawings.
제1a도 ∼ 제1c 도는 종대의 반도체 장치의 콘택 홀 형성 방법을 그 공정 순서에 따라 도시한 단면도이다.1A to 1C are cross-sectional views showing a method for forming contact holes in vertical semiconductor devices in the order of their processes.
제1a도에 도시한 바와, 불순물 확산 영역(12)이 형성되어있는 반도체 기판(10) 위에 도핑하지 않은 저온 산화막(20)과 도핑된 절연막(30)을 차례로 형성한다. 그리고, 도핑된 절연막(30) 위에 같은 절연 물질로서 식각속도가 빠른 제1절연막(40)을 형성하고, 그 위에는 도핑된 절연막(30)과 동일한 식각 속도를 갖는 제2절연막(50)을 증착한다. 이때 제1절연막(40)과 제2절연막(50)의 두께는 2000∼2500Å으로 형성한다.As shown in FIG. 1A, the undoped low temperature oxide film 20 and the doped insulating film 30 are sequentially formed on the semiconductor substrate 10 on which the impurity diffusion region 12 is formed. Then, the first insulating layer 40 having the same etching rate as the same insulating material is formed on the doped insulating layer 30, and the second insulating layer 50 having the same etching rate as the doped insulating layer 30 is deposited thereon. . At this time, the thickness of the first insulating film 40 and the second insulating film 50 is 2000 to 2500∼.
다음, 평탄화 및 불순물의 재분포를 위해 850℃∼900℃에서 열처리한다.Next, heat treatment is performed at 850 ° C to 900 ° C for planarization and redistribution of impurities.
제1b도에서, 상기 제2절연막(50)의 전면에 소정 영역이 노출되도록 감광막 패턴(60)을 형성한 후, 불순물 확산 영역(12)을 노출시키기 위해 제2절연막(50)과 제1(절연막(40)의 일부까지를 등방성 습식 식각법으로 1차 식각한다. 이어서, 잔존하는 제1절연막(40)과 도핑된 절연막(30), 도핑하지 않은 저온 산화막(20)을 이방성 건식 식각법으로 2차 식각하여 불순물 확산 영역(12)이 드러나도록 콘택 홀(14)을 형성한다.In FIG. 1B, after the photoresist pattern 60 is formed on the entire surface of the second insulating layer 50 to expose a predetermined region, the second insulating layer 50 and the first ( A portion of the insulating film 40 is first etched by an isotropic wet etching method, and then the remaining first insulating film 40, the doped insulating film 30, and the undoped low temperature oxide film 20 are subjected to an anisotropic dry etching method. The second hole is etched to form the contact hole 14 to expose the impurity diffusion region 12.
제1c도에서 남아있는 감광막(600)을 제거한 후 콘택 홀(14)이 형성되어있는 반도체 기판(10) 전면에 도전체 금속 물질을 증착하여 콘택 홀(14) 내면 및 불순물 확산 영역(12)에 접촉되는 금속막(70)을 형성한다.After removing the remaining photoresist film 600 in FIG. 1C, a conductive metal material is deposited on the entire surface of the semiconductor substrate 10 on which the contact hole 14 is formed, and then deposited on the inner surface of the contact hole 14 and the impurity diffusion region 12. The metal film 70 in contact is formed.
이러한 종래의 반도체 장치의 콘택 홀 형성 방법에서는 층간 절연막을 플로우 공정이 가능한 BPSG, PSG, BSG막을 이용하여 다층으로 형성시킴으로써 표면 스텝 커버리지가 개선된다.In such a conventional method of forming a contact hole in a semiconductor device, the surface step coverage is improved by forming an interlayer insulating film in a multilayer using BPSG, PSG, and BSG films capable of a flow process.
또한, 층간 절연막으로서 식각 속도가 빠른 절연막과 식각 속도가 느린 절연막을 다층으로 형성하여 콘택 홀 형성을 위한 사진식각 공정시 습식 식각과 건식 식각의 경계면이 빠른 식각 속도를 갖는 절연막 내에 형성되도록함으로써, 콘택 홀의 프로파일이 개선된다. 따라서 이후에 증착되는 금속의 콘택 홀 내부에서의 스텝 커버리지가 개선되어금속 배선의 신뢰성이 향상되며 각 콘택 홀의 금속막 스텝 커버리지 산포 감소 효과를 얻을 수 있게 된다.In addition, as the interlayer insulating film, an insulating film having a high etching rate and an insulating layer having a low etching rate are formed in a multilayer, so that the interface between wet etching and dry etching is formed in the insulating film having a fast etching rate during the photolithography process for forming the contact hole. The profile of the hole is improved. Therefore, the step coverage in the contact hole of the metal to be subsequently deposited is improved, so that the reliability of the metal wiring is improved and the metal film step coverage dispersion reduction effect of each contact hole can be obtained.
그러나, 이러한 종래의 반도체 장치의 콘택 홀 형성 방법은 콘택 홀의 프로파일을 개선시키는 효과는 있으나, 습식 식각과 건식 식각의 경계면부분에서 항상 날카로운 모서리가 남아 있게 되고, 다층의 BPSG를 이용하는 공정에서는 다층막의 침적 후 리플로우시에 붕소와 인이 막질 내에서의 상호 확산되므로 막질 내의 농도 조절이 어렵다는 문제점을 가지고 있다.However, the contact hole formation method of the conventional semiconductor device has an effect of improving the contact hole profile, but sharp edges always remain at the interface between the wet etching and the dry etching, and the deposition of the multilayer film in the process using the multilayer BPSG. Since boron and phosphorus are mutually diffused in the membrane during post-reflow, it is difficult to control the concentration in the membrane.
본 발명의 목적은 이러한 문제점을 해결하기 위한 것으로서, RTP(Rapid Thermal Process)를 이용하고 공정단계의 변경을 통하여 막질의 평탄화 및 농도 조절을 용이하게 하며 콘택 프로파일을 양호하게 하는 데에 있다.SUMMARY OF THE INVENTION An object of the present invention is to solve the problem, and to facilitate the planarization and concentration control of the film quality and the contact profile by using a rapid thermal process (RTP) and changing the process steps.
이러한 목적을 달성하기 위한 본 발명에 따른 반도체 장치의 콘텍 홀 형성 방법은, 반도체 기판에 다층의 절연막을 형성하는 제1공정, 상기 다층의 절연막을 사진식각하여 콘택 홀을 형성하는 제2공정, 상기 콘택 홀이 형성되어 있는 반도체 기판을 RTP를 이용하여 리플로우 하는 제3공정을 포함하고 있다.According to an aspect of the present invention, there is provided a method of forming a contact hole in a semiconductor device, the method comprising: forming a contact hole by photolithography of the multilayer insulating film; The third step of reflowing the semiconductor substrate in which the contact hole is formed using RTP is included.
본 발명에 따른 이러한 반도체 장치의 콘택 홀 형성 방법에서는 사진식각하여 콘택 홀을 형성한 다음 평탄화 및 농도 조절이 용이한 RTP를 이용하여 리플로우 함으로써, 완만한 경사면을 갖는 콘택 홀 프로파일을 형성하게 된다.In the method for forming a contact hole of the semiconductor device according to the present invention, the contact hole is formed by photolithography and then reflowed using RTP, which is easy to planarize and adjust the concentration, thereby forming a contact hole profile having a gentle slope.
그러면, 첨부한 도면을 참고로 하여 본 발명에 따른 반도체 장치의 콘택 홀 형성 방법의 실시예를 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있을 정도도 상세히 설명한다.Next, an embodiment of a method for forming a contact hole in a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
제2a도 ∼ 제2c도는 본 발명에 의한 반도체 장치의 콘택 홀 형성 방법을 그 공정 순서에 따라 도시한 단면도이다.2A to 2C are cross-sectional views showing a method for forming a contact hole in a semiconductor device according to the present invention in accordance with the process procedure.
제2a도에 도시한 바와 같이, 불순물 확산 영역(112)이 형성 되어있는 반도체 기판(110)위에 도핑하지 않은 저온 산화막(120), 도핑된 절연막(130)을 차례로 형성한다. 다음, 도핑된 절연막(130) 위에 식각 속도가 빠른 제1절연막(140), 식각 속도가 도핑된 절연막(130)과 같은 제2절연막(150)을 연속하여 증착한다.As shown in FIG. 2A, an undoped low temperature oxide film 120 and a doped insulating film 130 are sequentially formed on the semiconductor substrate 110 on which the impurity diffusion region 112 is formed. Next, a second insulating layer 150 such as a first etching layer 140 having a high etching rate and an insulating layer 130 doped with an etching rate is sequentially deposited on the doped insulating layer 130.
제2b도 와 같이, 상기 제2절연막(150)의 전면에 소정 영역이 노출되도록 감광막을 패터닝하여 감광막 패턴(160)을 형성한 후, 제2절연막(150) 전체와 제1절연막(140)의 일부까지를 습식 식각법으로 1차 시각한다. 다음, 남아 있는 제1절연막(140)과 도핑된 절연막(130), 도핑되지 않은 저온 산화막(120)을 건식 식각법으로 2차 식각한다.As shown in FIG. 2B, the photoresist layer is patterned to expose a predetermined region on the entire surface of the second insulation layer 150 to form the photoresist pattern 160, and then the entirety of the second insulation layer 150 and the first insulation layer 140 are formed. Part of the first view is by wet etching. Next, the remaining first insulating layer 140, the doped insulating layer 130, and the undoped low temperature oxide layer 120 are secondly etched by a dry etching method.
이후, 금속을 증착하기 이전에, 남아 있는 감광막(160)을 제거하고 RTP(Rapid Thermal Process)를 이용하여 리플로우를 시킴으로써 완만한 경사면의 콘택홀(114) 프로파일을 형성한다. 이때 RTP의 온도 범위는 850∼1000℃이고, 시간은 10초∼1분정도이다.Subsequently, before depositing the metal, the remaining photoresist layer 160 is removed and reflowed using a rapid thermal process (RTP) to form a contact hole 114 profile having a gentle slope. At this time, the temperature range of RTP is 850-1000 degreeC, and time is about 10 second-about 1 minute.
제2c도와 같이, 완만한 경사면이 형성되어 있는 콘택 홀(114)에 금속막(170)을 형성한다. 그리하여 스텝 커버리지가 향상된다. 따라서 금속의 콘택 홀(114) 내부의 스텝 커버리지가 개선되어 금속 배선의 신뢰성을 향상시킬 수 있고, 각 콘택 홀(114)의 스텝 커버리지 산포가 감소된다.As shown in FIG. 2C, the metal film 170 is formed in the contact hole 114 in which a gentle inclined surface is formed. Thus, step coverage is improved. Therefore, the step coverage inside the metal contact hole 114 can be improved to improve the reliability of the metal wiring, and the step coverage distribution of each contact hole 114 is reduced.
따라서, 본 발에 따른 반도체 장치의 콘택 홀 형성 방법은 금속을 증착하기 이전에 RTP를 이용한 리플로우를 시킴으로써 완만한 경사면의 콘택홀 프로파일을 형성한다. 그럼으로써 향상된 스텝 커버리지를 획득하게되어 금속 배선의 신뢰성을 향상시키고, 각 콘택 홀의 스텝 커버리지 산포가 감소하는 효과가 있다.Accordingly, the method for forming a contact hole in a semiconductor device according to the present invention forms a smooth inclined contact hole profile by reflowing with RTP before depositing a metal. As a result, improved step coverage can be obtained, thereby improving the reliability of the metal wiring and reducing the step coverage spread of each contact hole.
Claims (6)
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| KR1019950023876A KR0175414B1 (en) | 1995-08-02 | 1995-08-02 | Method for forming contact hole in semiconductor device |
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| KR100671607B1 (en) * | 2002-07-09 | 2007-01-18 | 주식회사 하이닉스반도체 | Method for manufacturing flash memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100671607B1 (en) * | 2002-07-09 | 2007-01-18 | 주식회사 하이닉스반도체 | Method for manufacturing flash memory |
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