KR0171936B1 - Method of manufacturing transistor in semiconductor device - Google Patents
Method of manufacturing transistor in semiconductor device Download PDFInfo
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- KR0171936B1 KR0171936B1 KR1019940036288A KR19940036288A KR0171936B1 KR 0171936 B1 KR0171936 B1 KR 0171936B1 KR 1019940036288 A KR1019940036288 A KR 1019940036288A KR 19940036288 A KR19940036288 A KR 19940036288A KR 0171936 B1 KR0171936 B1 KR 0171936B1
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- South Korea
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- oxide film
- heat treatment
- semiconductor device
- gate electrode
- tungsten silicide
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 26
- 238000010438 heat treatment Methods 0.000 claims abstract description 17
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 16
- 239000007789 gas Substances 0.000 claims abstract description 14
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 10
- 239000011737 fluorine Substances 0.000 claims abstract description 10
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 8
- 230000008021 deposition Effects 0.000 claims abstract description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 5
- 229910021529 ammonia Inorganic materials 0.000 claims abstract description 4
- 239000001257 hydrogen Substances 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 5
- 125000006850 spacer group Chemical group 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 230000006866 deterioration Effects 0.000 abstract description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 abstract description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 abstract 2
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- CTQNGGLPUBDAKN-UHFFFAOYSA-N O-Xylene Chemical compound CC1=CC=CC=C1C CTQNGGLPUBDAKN-UHFFFAOYSA-N 0.000 description 1
- 229910018557 Si O Inorganic materials 0.000 description 1
- 229910008284 Si—F Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000006722 reduction reaction Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 1
- 239000008096 xylene Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 반도체 소자의 트랜지스터 제조방법에 관한 것으로, 폴리사이드구조의 게이트전극을 형성함에 있어, 텅스텐 실리사이드 증착시 개입된 불소(F) 에 의한 게이트산화막의 특성열화를 방지하기 위하여 텅스텐 실리사이드를 증착한후 암모니아(NH3) 또는 수소(H2)와 같은 환원성 분위기가스 상태와 600 내지 900℃의 온도 조건에서 열처리하므로써, 후속 열처리 공정시 게이트산화막으로의 불소의 확산이 최소화되어 게이트산화막의 특성이 향상되고 따라서 소자의 전기적 특성이 향상될수 있는 반도체 소자의 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor manufacturing method of a semiconductor device. In forming a gate electrode having a polyside structure, tungsten silicide is deposited in order to prevent deterioration of a gate oxide film due to fluorine (F) involved in the deposition of tungsten silicide. After heat treatment in a reducing atmosphere gas such as ammonia (NH 3 ) or hydrogen (H 2 ) and a temperature condition of 600 to 900 ℃, the diffusion of fluorine into the gate oxide film during the subsequent heat treatment process is minimized to improve the characteristics of the gate oxide film The present invention relates to a transistor manufacturing method of a semiconductor device in which the electrical characteristics of the device can be improved.
Description
제1a 및 제1b도는 종래 반도체 소자의 트랜지스터 제조방법을 설명하기 위한 소자의 단면도.1A and 1B are cross-sectional views of a device for explaining a transistor manufacturing method of a conventional semiconductor device.
제2a 및 제2b도는 본 발명에 따른 반도체 소자의 트랜지스터 제조방법을 설명하기 위한 소자의 단면도.2A and 2B are cross-sectional views of a device for explaining a transistor manufacturing method of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘기판 2 : 필드산화막1: silicon substrate 2: field oxide film
3 : 게이트산화막 4 및 4A : 폴리실리콘층3: gate oxide film 4 and 4A: polysilicon layer
5 및 9 : 텅스텐 실리사이드 6 : 감광막패턴5 and 9: tungsten silicide 6: photosensitive film pattern
7 및 7A : 스페이서산화막 8 및 8 : 소오스 및 드래인영역7 and 7A: spacer oxide film 8 and 8: source and drain regions
10 및 11 : 게이트전극10 and 11: gate electrode
본 발명은 반도체 소자의 트랜지스터 제조방법에 관한 것으로, 특히 폴리사이드(Polycide)구조의 게이트전극을 형성함에 있어, 텅스텐 실리사이드를 증착한 후 환원성 분위기가스 상태에서 열처리하므로써 후속 열처리공정시 게이트산화막으로의 불소의 확산이 최소화되어 게이트산화막의 특성이 향상될수 있도록 한 반도체 소자의 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor of a semiconductor device. In particular, in forming a gate electrode having a polycide structure, tungsten silicide is deposited and then heat-treated in a reducing atmosphere gas, thereby fluorine as a gate oxide film in a subsequent heat treatment process. The present invention relates to a method for fabricating a transistor of a semiconductor device in which diffusion of the oxide can be minimized to improve characteristics of the gate oxide film.
일반적으로 반도체 소자의 제조공정에서 소자의 동작속도를 증가시키는 하나의 방법으로서 전극 즉, 도전층의 저항을 감소시키는 방법이 이용된다. 이는 도전층으로 사용되는 폴리실리콘층 상부에 텅스텐 실리사이드(WSix)를 증착하여 폴리사이드구조의 도전층을 형성한후 열처리하므로써 이루어지는데, 이를 이용한 종래반도체 소자의 트랜지스터 재조방법을 제1a 및 제1b도를 통해 설명하면 다음과 같다.In general, a method of reducing the resistance of an electrode, that is, a conductive layer, is used as one method of increasing the operation speed of a device in a manufacturing process of a semiconductor device. This is achieved by depositing tungsten silicide (WSi x ) on the polysilicon layer used as the conductive layer to form a conductive layer having a polyside structure and then heat treating it. When described with reference to the following.
제1a 및 제1b도는 종래 반도체 소자의 트랜지스터 제조방법을 설명하기 위한 소자의 단면도이다.1A and 1B are cross-sectional views of a device for explaining a transistor manufacturing method of a conventional semiconductor device.
제1a도에 도시된 바와같이, 필드산화막(2)이 형성된 실리콘기판(1)상에 게이트산화막(3) 및 폴리실리콘층(4)을 순차적으로 형성한후 폴리실리콘층(4)에 불순물이온을 주입하고 그 상부에 텅스텐 실리사이드(5)를 증착한다. 이후 게이트전극이 형성될 부분에 감광막패턴(6)을 형성시킨다.As shown in FIG. 1A, after the gate oxide film 3 and the polysilicon layer 4 are sequentially formed on the silicon substrate 1 on which the field oxide film 2 is formed, impurity ions are formed in the polysilicon layer 4. Is injected and the tungsten silicide 5 is deposited thereon. Thereafter, the photoresist pattern 6 is formed on the portion where the gate electrode is to be formed.
제1b도에 도시된 바와 같이 감광막패턴(6)을 이용한 식각공정을 통해 게이트전극(10)을 패터닝하고 열처리 공정을 실시한 다음 게이트전극(10)의 양측벽에 산화막스페이서(7)를 형성시키고 전체면에 불순물이온을 주입하여 게이트전극(10) 양측의 실리콘기판(1) 상부에 소오스 및 드레인영역(8)을 형성시키므로써 트랜지스터가 형성된다. 여기서 텅스텐 실리사이드(5)는 육불화텅스텐(WF6) 과 사일렌(SiH4) 가스를 사용한 저압화학기상증착방법에 의해 증착되며 후속 열처리공정에 의해 하부의 폴리실리콘과 계면의 안정화를 이룬 다음 결정화되는데, 이때의 반응식은 하기의 식1과 같다.As shown in FIG. 1B, the gate electrode 10 is patterned through an etching process using the photoresist pattern 6, a heat treatment process is performed, and an oxide film spacer 7 is formed on both sidewalls of the gate electrode 10. Transistors are formed by implanting impurity ions into the surface to form source and drain regions 8 over the silicon substrate 1 on both sides of the gate electrode 10. Here, tungsten silicide (5) is deposited by low pressure chemical vapor deposition using tungsten hexafluoride (WF 6 ) and xylene (SiH 4 ) gas, and then stabilizes the interface with the polysilicon underneath by subsequent heat treatment. At this time, the reaction scheme is as shown in Equation 1 below.
그런데 식1 에서와 같이 텅스텐 실리사이드(WSi2) 증착과정에서 불소(F)가 함유되며 이는 후속 열처리공정시 게이트산화막까지 확산되어 게이트산화막내의 Si-O 결합본드(Bond)를 파괴시키고 Si-F로 결합하며, 이때 떨어져나온 산소(O)원자는 게이트산화막 및 폴리실리콘의 계면으로 이동하여 폴리실리콘을 산화시킨다. 이에 따라 게이트산화막의 두께가 증가되고 특성이 열화되어 트랜지스터의 전기적 특성을 저하시키는 문제점이 있다.However, as shown in Equation 1, fluorine (F) is contained during the deposition of tungsten silicide (WSi 2 ), which is diffused to the gate oxide layer in the subsequent heat treatment process to destroy the Si-O bond bonds in the gate oxide layer and to Si-F. In this case, the separated oxygen (O) atoms move to the interface between the gate oxide film and the polysilicon to oxidize the polysilicon. Accordingly, there is a problem that the thickness of the gate oxide film is increased and the characteristics are deteriorated, thereby lowering the electrical characteristics of the transistor.
따라서 본 발명은 텅스텐 실리사이드를 증착한 후 암모니아(NH3) 또는 수소(H2)와 같은 환원성 가스분위기 상태에서 열처리하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 트랜지스터 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for fabricating a transistor of a semiconductor device which can solve the above disadvantages by depositing tungsten silicide and heat treatment in a reducing gas atmosphere such as ammonia (NH 3 ) or hydrogen (H 2 ). have.
상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 트랜지스터 제조 방법은 필드산화막이 형성된 실리콘 기판 상에 게이트산화막 및 폴리실리콘층을 형성하고 불순물 이온을 주입시키는 단계와, 전체 구조 상부에 텅스텐 실리사이드를 증착한 후 사진 및 식각공정을 통해 게이트전극을 패터닝하는 단계와, 상기 텅스텐 실리사이드 증착시 함유된 불소를 제거하기 위해 암모니아 또는 수소와 같은 환원성 분위기 가스를 이용하여 열처리 공정을 실시하는 단계와, 상기 게이트전극 양측벽에 산화막스페이서를 형성시키고 불순물이온주입공정을 실시하여 상기 게이트전극양측의 실리콘기판 상부에 소오스 및 드레인영역을 형성시키는 단계로 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a transistor of a semiconductor device, the method including forming a gate oxide film and a polysilicon layer on a silicon substrate on which a field oxide film is formed, and implanting impurity ions into the semiconductor substrate; Patterning the gate electrode through a photolithography and etching process after deposition, and performing a heat treatment process using a reducing atmosphere gas such as ammonia or hydrogen to remove fluorine contained in the tungsten silicide deposition, and the gate Forming an oxide film spacer on both side walls of the electrode and performing an impurity ion implantation process to form source and drain regions on the silicon substrates on both sides of the gate electrode.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2a 및 제2b도는 본 발명에 따른 반도체 소자의 트랜지스터 제조방법을 설명하기 위한 소자의 단면도이다.2A and 2B are cross-sectional views of a device for explaining a transistor manufacturing method of a semiconductor device according to the present invention.
제2a도는 필드산화막(2)이 형성된 실린콘기판(1)상에 열산화공정에 의해 게이트산화막(3)을 형성한 후 그 상부에 폴리실리콘층(4A)을 형성하고 불순물이온을 주입한 다음 저압화학기상증착방법에 의해 텅스텐 실리사이드(9)를 증착한 상태의 단면도이다.2a shows a gate oxide film 3 formed on the silicon substrate 1 on which the field oxide film 2 is formed by a thermal oxidation process, and then a polysilicon layer 4A is formed thereon and impurity ions are implanted. It is sectional drawing of the state which deposited the tungsten silicide 9 by the low pressure chemical vapor deposition method.
제2b도에 도시된 바와 같이, 게이트전극이 형성될 부분에 감광막패턴(도시하지 않음)을 형성한후 식각공정을 통해 게이트전극(11)을 패터닝하고 환원성 분위기가스 상태에서 열처리공정을 실시하여 텅스텐 실리사이드(9)를 결정화시킨다.As shown in FIG. 2B, after forming a photoresist pattern (not shown) on the portion where the gate electrode is to be formed, the gate electrode 11 is patterned through an etching process and heat treatment is performed in a reducing atmosphere gas. The silicide 9 is crystallized.
이후 게이트전극(11)의 양측벽에 산화막 스페이서(7A)를 형성시키고 불순물 이온주입공정을 실시하여 게이트전극(11) 양측의 실리콘기판(1) 상부에 소오스 및 드레인 영역(8A)을 형성시키므로써 트랜지스터의 제조가 완료된다. 여기에서 열처리 공정을 다음의 표를 참조하여 설명하면 다음과 같다.Afterwards, an oxide spacer 7A is formed on both sidewalls of the gate electrode 11 and an impurity ion implantation process is performed to form source and drain regions 8A on the silicon substrate 1 on both sides of the gate electrode 11. The manufacture of the transistor is completed. Herein, the heat treatment process will be described with reference to the following table.
이러한 열처리공정은 표에서와 같이 텅스텐실리사이드(9)가 증착된 실리콘기판(1)을 대기압상태인 반응로의 튜브(이때의 온도는 300 내지 800℃ 그리고 N또는A가스분위기) 내부로 로딩(Loading)한 후 저압 또는 대기압상태인 튜브내의 온도를 600 내지 900℃까지 상승시킨다. 상승된 온도상태에서 환원성 분위기가스인 NH또는 H2가스를 공급하고(이때의 튜브내부는 저압 또는 대기압상태임) 열처리한 다음 튜브내의 온도를 300 내지 800℃로 하강시키고(N또는 A가스 분위기) 대기압상태에서 실리콘기판(1)을 반응로 외부로 언로딩(Unloading)한다. 이러한 열처리 공정시 텅스텐 실리사이드내에 함유된 불소(F)는 환원성 분위기가스인 NH또는 H가스와 하기의 식2 및 식3과 같은 환원반응을 일으켜 불화수소(HF)가 되어 외부배출(Out gassing)된다. 그러므로 후속 열처리공정시 불소(F)가 게이트산화막까지 확산되는 것을 최소화시켜 게이트산화막의 특성저하가 방지되고 따라서 소자의 전기적 특성이 향상된다.This heat treatment process loads the silicon substrate 1 on which tungsten silicide 9 is deposited into the tube of the reactor (at this time, the temperature is 300 to 800 ° C. and the N or A gas atmosphere) at atmospheric pressure. The temperature in the tube under low or atmospheric pressure is raised to 600 to 900 ° C. At elevated temperature, NH or H2 gas, which is a reducing atmosphere gas, is supplied (in this case, the inside of the tube is at a low pressure or atmospheric pressure), heat-treated, and then the temperature in the tube is lowered to 300 to 800 ° C (N or A gas atmosphere). In this state, the silicon substrate 1 is unloaded to the outside of the reactor. In this heat treatment process, fluorine (F) contained in tungsten silicide undergoes a reduction reaction with NH or H gas, which is a reducing atmosphere gas, to form hydrogen fluoride (HF) and is discharged outward. . Therefore, the diffusion of fluorine (F) to the gate oxide film is minimized during the subsequent heat treatment, thereby preventing the gate oxide film from deteriorating in characteristics and thus improving the electrical characteristics of the device.
상술한 바와같이 본 발명에 의하면 텅스텐 실리사이드 증착시 함유된 불소(F)가 게이트 산화막으로 확산되는 것을 방지하기 위하여 환원성 분위기가스 상태에서 열처리하므로써 후속 열처리공정시 게이트산화막으로의 불소의 확산이 최소화되어 게이트산화막의 특성열화가 방지되고 따라서 소자의 전기적 특성이 향상될수 있는 탁월한 효과가 있다.As described above, according to the present invention, in order to prevent diffusion of fluorine (F) contained in the tungsten silicide deposition into the gate oxide film, heat treatment is performed in a reducing atmosphere gas so that diffusion of fluorine into the gate oxide film during the subsequent heat treatment process is minimized. The deterioration of the characteristics of the oxide film is prevented and thus there is an excellent effect that the electrical properties of the device can be improved.
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