KR0165765B1 - Eject marking method for semiconductor package and its package - Google Patents
Eject marking method for semiconductor package and its package Download PDFInfo
- Publication number
- KR0165765B1 KR0165765B1 KR1019940032145A KR19940032145A KR0165765B1 KR 0165765 B1 KR0165765 B1 KR 0165765B1 KR 1019940032145 A KR1019940032145 A KR 1019940032145A KR 19940032145 A KR19940032145 A KR 19940032145A KR 0165765 B1 KR0165765 B1 KR 0165765B1
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- South Korea
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- eject
- product
- mold
- package
- annular
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 title claims abstract description 10
- 150000001875 compounds Chemical class 0.000 claims abstract description 9
- 239000000463 material Substances 0.000 claims abstract description 9
- 238000000926 separation method Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000000465 moulding Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000011010 flushing procedure Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
본 발명은 반도체패키지용 이젝트마킹 방법 및 패키지제품에 관한 것으로서, 패키지제품(5) 표면으로 환형요홈부(6)를 형성시키는 환형돌출부(7)를 단수개 이상 형성하고, 이 환형돌출부(7) 내부에는 원주형돌출부(2)가 형성되도록 한 요홈(3)을 형성하며, 상승, 하강할 수 있는 이젝트핀(4)을 구비하여 패키지제품(5) 표면에 이젝트마킹부(8)가 형성되도록 하므로서, 하금형상에 환형돌출부를 형성하고, 환형돌출부 내부에 형성된 요홈에는 문자 및 도형이 각인된 이젝트핀을 구비하여 컴파운드재로 성형되는 반도체패키지제품의 이젝트마킹부에 플러쉬 발생을 감소시켜 제품의 품질을 높이고, 패키지제품과 금형과의 접촉면적을 최소화하며 접촉응력을 감쇄시키므로서 제품의 분리가 용이하도록 한 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an eject marking method for a semiconductor package and a packaged product, wherein at least one annular projection (7) forming an annular recess (6) is formed on the surface of the packaged product (5), and the annular projection (7) is formed. A recess 3 is formed inside the columnar protrusion 2, and the eject pin 8 is provided with an eject pin 4 that can be raised and lowered so that the eject marking portion 8 is formed on the surface of the package product 5. Therefore, the annular protrusion is formed on the lower die, and the recess formed in the annular protrusion is provided with eject pins imprinted with letters and figures to reduce the occurrence of flush on the eject marking portion of the semiconductor package product formed of compound material. It is effective to increase the separation, minimize the contact area between the package product and the mold and reduce the contact stress, thereby facilitating the separation of the product.
Description
제1도는 종래 이젝트마킹 방법의 구조도1 is a structural diagram of a conventional eject marking method
제2도는 종래 이젝트마킹된 패키지제품 구조도2 is a structure diagram of a conventional eject marked package product
제3도는 종래 이젝트마킹된 패키지제품 단면도3 is a cross-sectional view of a conventional ejected packaged product
제4도는 본 발명의 이젝트마킹 방법의 금형구조도4 is a mold structure diagram of the eject marking method of the present invention
제5도는 본 발명의 이젝트마킹 패키지제품 구조도5 is a structural diagram of the eject marking package product of the present invention
제6도는 본 발명의 이젝트마킹 패키지제품의 요부 단면도6 is a cross-sectional view of main parts of the eject marking package product of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 금형 2 : 원주형돌출부1: mold 2: cylindrical protrusion
3 : 요홈 4 : 이젝트핀3: groove 4: eject pin
5 : 반도체패키지제품 6 : 환형요홈부5: semiconductor package product 6: annular recess
7 : 환형돌출부 8 : 이젝트마킹부7: annular projection 8: ejection marking
본 발명은 반도체패키지용 이젝트마킹 방법 및 그 패키지제품에 관한 것으로서, 특히 몰드금형에서 이젝트마킹되는 반도체패키지의 분리가 수월하고, 이젝트마킹된 패키지제품의 마킹부에 발생되는 플러쉬의 발생을 감소시킬 수 있도록 하는 반도체패키지용 이젝트마킹 방법 및 그 패키지제품에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an eject marking method for a semiconductor package and a packaged product thereof. In particular, it is easy to separate a semiconductor package ejected from a mold mold and reduce the occurrence of flush generated in the marking portion of the ejected packaged product. The present invention relates to an eject marking method for a semiconductor package and a package product thereof.
일반적으로 반도체패키지는 몰드금형에서 컴파운드재를 이용하여 패키지성형하게 되는데 이때 상,하 금형중 어느 한측의 금형에는 문자 및 도형이 각인된 이젝트핀이 구비되어 패키지성형된 반도체패키지에 문자 및 도형을 마킹하는 동시에 패키지제품을 이젝트시켜 금형틀에서 용이하게 분리되도록 하는 것으로서, 종래에는 도시된 도면 제1도에서와 같이 몰드금형장치의 상,하 금형중 어느 한측의 금형(21)에 구비된 부싱(22) 내부에 이젝트핀(23)을 구비하여 금형(21)상부의 캐비티부(21A)에서 컴파운드재로 성형되는 반도체패키지의 패키지제품(24)이 일측면에 이젝트핀(23)에 의해 다수개의 이젝트마킹부(25)가 형성되도록 한다.In general, a semiconductor package is packaged by using a compound material in a mold mold. At this time, a mold on one side of the upper and lower molds is provided with eject pins imprinted with letters and figures to mark letters and figures on the packaged semiconductor package. At the same time, by ejecting the package product to be easily separated from the mold, conventional bushing 22 provided in the mold 21 on either side of the upper and lower molds of the mold mold apparatus as shown in FIG. ) The package product 24 of the semiconductor package, which is formed of a compound material in the cavity portion 21A on the upper part of the mold 21 by having the eject pin 23 therein, is ejected by a plurality of eject pins 23 on one side thereof. The marking portion 25 is formed.
이렇게 패키지제품(24)이 성형되는 동시에 이젝트핀(23)에 의해 이젝트마킹부(25)가 형성된후 이젝트핀(23)을 상승시켜 패키지제품(24)을 분리시키게 되면, 도시된 도면 제2도와 같이 반도체패키지의 패키지제품(24) 일측면에 다수개의 이젝트마킹부(25)가 형성되어진다.When the package product 24 is molded and the eject marking portion 25 is formed by the eject pin 23, the eject pin 23 is raised to separate the package product 24. Likewise, a plurality of eject marking portions 25 are formed on one side of the package product 24 of the semiconductor package.
그러나 이젝트마킹부(25)가 형성된 패키지제품(24)은 도시된 도면 제3도에서와 같이 문자 및 도형이 소정크기로 성형되어지도록 조건을 갖춘 이젝트핀(23)의 크기가 크므로 인하여 요홈부를 가진 이젝트마킹부(25) 면적이 크게 형성되어 패키지제품(24)이 분리될때 이젝트마킹부(25)와 이젝트핀(23)의 접촉 단면적이 커짐에 따라 접촉응력이 크게 발생하여 이젝트마킹부(25)에 플러쉬(P)가 많이 발생하고, 이젝트핀(23)이 이젝트마킹부(25)에서 수월하게 분리되지 못하는 등의 문제점이 있었다.However, the packaged product 24 having the eject marking portion 25 is formed with a recess pin because the size of the eject pin 23 having a condition that the characters and figures are molded to a predetermined size as shown in FIG. When the ejection marking part 25 has a large area and the package product 24 is separated, as the contact cross-sectional area of the eject marking part 25 and the eject pin 23 increases, the contact stress is largely generated, and thus the eject marking part 25 ), A lot of flushes (P) occurs, and the eject pins 23 are not easily separated from the eject marking part 25.
따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위하여 발명한 것으로서, 금형장치의 상,하금형중 어느 한측 금형상에 환형돌출부를 형성하고, 환형돌출부 내부에 형성된 요홈에는 문자 및 도형이 각인된 이젝트핀을 구비하여 컴파운드재로 성형되는 반도체패키지제품의 이젝트마킹부에 플러쉬 발생을 감소시키고, 금형상에서 패키지제품의 분리가 용이하도록 한 것을 목적으로 한다.Therefore, the present invention is invented to solve the above conventional problems, the annular projection is formed on either side of the upper and lower molds of the mold apparatus, the grooves formed inside the annular projections are stamped with letters and figures The purpose of the present invention is to reduce the occurrence of flush and to facilitate the separation of the packaged product on the mold by providing an eject pin to the eject marking portion of the semiconductor package product formed of a compound material.
이하 첨부된 도면에 의하여 본 발명을 상세하게 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
컴파운드재로 몰드금형장치의 상,하금형에 형성된 캐비티부(1A)에서 컴파운드재로 패키지성형되는 반도체패키지 제품에 이젝트마킹부(8)를 형성시키는 몰드금형장치의 상,하금형중 어느하나의 금형(1)중에 패키지제품(5) 표면으로 환형요홈부(6)를 형성시키는 환형돌출부(7)를 단수개 이상 형성하고, 이 환형돌출부(7) 내부에는 원주형돌출부(2)가 형성되도록 한 요홈(3)을 형성하며, 상승, 하강할 수 있는 이젝트핀(4)을 구비하여 패키지제품(5) 표면에 이젝트마킹부(8)가 형성되도록 한다.Any one of the upper and lower molds of the mold mold apparatus for forming the eject marking portion 8 in the semiconductor package product packaged with the compound material from the cavity portion 1A formed on the upper and lower molds of the mold mold apparatus with the compound material. A plurality of annular projections 7 forming the annular grooves 6 on the surface of the package product 5 are formed in the mold 1, and the cylindrical projections 2 are formed inside the annular projections 7. Forming a groove (3), and having an eject pin (4) that can be raised, lowered so that the eject marking portion (8) is formed on the surface of the package product (5).
이렇게 이젝트마킹부(8)가 형성되는 패키지제품(5)은 캐비티부(1A) 외부로 돌출형성된 금형(1)의 환형돌출부(7)에 의해 패키지제품(5) 표면에 환형요홈부(6)가 형성되고, 이 환형요홈부(6)의 중앙에는 이젝트핀(4)이 상승, 하강되도록 설치된 금형(1)의 요홈(3) 상부와 이젝트핀(4) 상부면 사이의 높이(H) 공간부에서 원주형돌출부(2)가 형성되게 하여 이젝트마킹부(8)를 성형시키는 것이다.The packaged product 5 in which the eject marking portion 8 is formed is annular groove 6 on the surface of the packaged product 5 by the annular protrusion 7 of the mold 1 protruding out of the cavity 1A. And a height (H) space between the upper part of the recess 3 and the upper part of the eject pin 4 of the mold 1 installed so that the eject pin 4 is raised and lowered at the center of the annular recess 6. The columnar projections 2 are formed at the portions to form the eject marking portions 8.
따라서, 패키지제품(5)의 표면에는 금형(1)중에 환형돌출부(7) 및 요홈(3)과 이젝트핀(4)에 구비된 숫자만큼 환형돌출부(7)와 이 환형요홈부(6) 중앙에 원주형돌출부(2)를 가진 이젝트마킹부(8)가 형성된다.Therefore, the surface of the packaged product 5 has an annular protrusion 7 and a center of the annular protrusion 7 and the annular recess 6 by the number provided in the annular protrusion 7 and the recess 3 and the eject pin 4 in the mold 1. An eject marking portion 8 having a columnar protrusion 2 is formed in the groove.
이러한 반도체패키지제품(5)에 형성된 원주형의 이젝트마킹부(8) 표면에는 이젝트핀(4)에 각인된 문자 및 도형을 패키지성형중에 형성시키도록 한다.On the surface of the columnar ejection marking portion 8 formed in the semiconductor package product 5, letters and figures engraved on the eject pin 4 are formed during package molding.
이와같이 몰드금형장치의 상,하금형 캐비티부(1A)에서 이젝트마킹부(8)가 형성되고 패키지성형이 완료되면, 상,하금형이 분리되면서 요홈(3)에서 상승,하강하는 이젝트핀(4)을 상승시켜 패키지제품(5)을 금형상에서 분리시킨다.As such, when the eject marking portion 8 is formed in the upper and lower mold cavity portions 1A of the mold mold apparatus and the package molding is completed, the eject pins 4 which rise and fall in the grooves 3 are separated while the upper and lower molds are separated. ), The packaged product 5 is separated from the mold.
이때 분리되는 패키지제품(5)은 금형에 형성된 환형돌출부(7)의 두께(t)를 최대한 얇게 형성하고, 이 환형돌출부(7)에 의해 패키지제품(5)에 형성되는 환형돌출부(7)에 의해 패키지제품(5)에 형성되는 환형요홈부(6)를 최대한 좁게 형성하므로서, 이젝트핀(4)이 요홈(3)에서 상승할 때 분리되는 패키지제품(5)과 금형(1)과의 접촉면적을 최소화하며 분리가 용이하게 한다.At this time, the package product 5 to be separated forms the thickness t of the annular protrusion 7 formed in the mold as thin as possible, and the annular protrusion 7 formed in the package product 5 by the annular protrusion 7. By forming the annular groove 6 formed in the package product 5 to be as narrow as possible, the contact between the package product 5 and the mold 1 separated when the eject pin 4 is raised from the groove (3) Minimizes area and facilitates separation.
또한 요홈(3)에 삽입된 이젝트핀(4)의 상부면과 요홈(3)의 상부 선단 사이의 소정높이(H)에서 성형되는 이젝트마킹부(8)는 요홈(3)에서 패키지제품(5)이 분리시 이젝트핀(4)의 상승 압력으로 용이하게 분리되는 동시에 이젝트마킹부(8)에 발생하는 플러쉬를 감소시킨 것이다.In addition, the ejection marking part 8 formed at a predetermined height H between the upper surface of the eject pin 4 inserted into the groove 3 and the upper end of the groove 3 has a packaged product 5 in the groove 3. ) Is easily separated by the rising pressure of the eject pin 4 at the time of separation, and at the same time, the flush generated in the eject marking part 8 is reduced.
이상에서 같이 본 발명은 하금형상에 환형돌출부를 형성하고, 환형돌출부 내부에 형성된 요홈에는 문자 및 도형이 각인된 이젝트핀을 구비하여 컴파운드재로 성형되는 반도체패키지제품의 이젝트마킹부에 플러쉬 발생을 감소시켜 제품의 품질을 높이고, 패키지제품과 금형과의 접촉면적을 최소화하며 접촉응력을 감쇄시키므로서 제품의 분리가 용이하도록 한 효과가 있다.As described above, the present invention forms an annular protrusion on the lower die, and the recess formed in the annular protrusion includes an eject pin inscribed with letters and figures to reduce the occurrence of flushing in the eject marking portion of the semiconductor package product formed of a compound material. By improving the product quality, minimizing the contact area between the package product and the mold and reducing the contact stress, there is an effect to facilitate the separation of the product.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940032145A KR0165765B1 (en) | 1994-11-30 | 1994-11-30 | Eject marking method for semiconductor package and its package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940032145A KR0165765B1 (en) | 1994-11-30 | 1994-11-30 | Eject marking method for semiconductor package and its package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960019620A KR960019620A (en) | 1996-06-17 |
| KR0165765B1 true KR0165765B1 (en) | 1999-02-01 |
Family
ID=19399788
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940032145A KR0165765B1 (en) | 1994-11-30 | 1994-11-30 | Eject marking method for semiconductor package and its package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0165765B1 (en) |
-
1994
- 1994-11-30 KR KR1019940032145A patent/KR0165765B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR960019620A (en) | 1996-06-17 |
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