KR0161726B1 - Method of fabricating semiconductor device - Google Patents
Method of fabricating semiconductor device Download PDFInfo
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- KR0161726B1 KR0161726B1 KR1019940032628A KR19940032628A KR0161726B1 KR 0161726 B1 KR0161726 B1 KR 0161726B1 KR 1019940032628 A KR1019940032628 A KR 1019940032628A KR 19940032628 A KR19940032628 A KR 19940032628A KR 0161726 B1 KR0161726 B1 KR 0161726B1
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Abstract
본 발명은 반도체소자 제조방법에 관한 것으로, 반도체기판 상부에 소자 분리절연막, 불순물 접합영역 및 하부절연층을 형성하고 상기 하부절연층을 식각하여 콘택홀을 형성한 다음, 상기 불순물 접합영역의 불순물과 같은 특성을 갖는 불순물이 함유된 절연막을 전체표면상부에 일정두께 형성하고 열공정을 실시하여 상기 절연막에 함유된 불순물을 상기 반도체기판에 확산시켜 상기 불순물 접합영역보다 깊게 형성된 확산 불순물 접합영역을 형성함으로써 절연막 스페이서 형성공정시 발생되는 접합누설전류를 감소시키고 콘택 미스얼라인이 발생하더라도 소자분리절연막 하부로 확산 불순물 접합영역을 형성함으로써 접합누설전류를 감소시켜 반도체소자의 신뢰성을 향상시키고 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for manufacturing a semiconductor device, comprising forming a device isolation insulating film, an impurity junction region and a lower insulation layer on an upper surface of a semiconductor substrate, etching the lower insulation layer to form a contact hole, and then removing impurities from the impurity junction region. An insulating film containing impurities having the same characteristics is formed on the entire surface at a predetermined thickness, and thermal processes are performed to diffuse the impurities contained in the insulating film onto the semiconductor substrate to form a diffusion impurity junction region formed deeper than the impurity junction region. It reduces the junction leakage current generated during the insulating film spacer formation process and forms the diffusion impurity junction region under the device isolation insulating film even if contact misalignment occurs, thereby reducing the junction leakage current to improve the reliability of the semiconductor device and increase the integration of the semiconductor device. It is a technology that makes it possible.
Description
제1도는 종래 기술의 실시예에 따라 형성된 반도체소자를 도시한 단면도.1 is a cross-sectional view showing a semiconductor device formed according to an embodiment of the prior art.
제2a도 및 제2b도는 본 발명의 제1실시예에 따른 반도체소자 제조 공정을 도시한 단면도.2A and 2B are cross-sectional views showing a semiconductor device manufacturing process according to the first embodiment of the present invention.
제3도는 본 발명의 제2실시예에 따라 형성된 반도체소자를 도시한 단면도.3 is a cross-sectional view showing a semiconductor device formed in accordance with a second embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11,31,51 : 반도체기판 13,33,53 : 소자분리산화막11,31,51: semiconductor substrate 13,33,53: device isolation oxide film
15,35,55 : 불순물 접합영역 17,37,57 : 하부절연층15,35,55 Impurity junction region 17,37,57 Lower insulating layer
19,39,59 : 콘택홀 21,41,61 : 산화막19,39,59: contact hole 21,41,61: oxide film
23,43 : 확산 불순물 접합영역23,43: diffusion impurity junction region
본 발명은 반도체소자 제조방법에 관한 것으로, 특히 반도체소자 형성공정 중에서 반도체기판에 접속되는 콘택형성시 발생하는 접합누설전류를 감소시키고, 콘택 미스얼라인(contact misalign) 발생시 불순물접합을 유지하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a technique for reducing a junction leakage current generated during contact formation connected to a semiconductor substrate during a semiconductor device formation process and maintaining impurity junctions when contact misalignment occurs. It is about.
종래에는 저장전극 콘택형성시 식각정도에 따라 불순물 접합영역이 영향을 받아 접합누설전류를 크게 발생시켰다. 더구나, 정렬오차가 발생했을 때 소자 분리절연막을 식각하게 되어, 상기의 식각된 부분으로 다량의 접합누설전류가 발생된다. 그로 인하여, 반도체소자의 신뢰성을 저하시키고 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.Conventionally, the impurity junction region is affected by the degree of etching during the formation of the storage electrode contact to generate a large junction leakage current. In addition, when the alignment error occurs, the element isolation insulating film is etched, and a large amount of junction leakage current is generated in the etched portion. Therefore, there is a problem that the reliability of the semiconductor device is lowered and the integration of the semiconductor device is difficult.
제1도는 종래 기술에 따라 형성된 반도체소자를 도시한 단면도이다.1 is a cross-sectional view showing a semiconductor device formed according to the prior art.
제1도를 참조하면, 반도체기판(51) 상부에 소자분리산화막(53), 불순물 접합영역(55) 및 하부절연층(57)을 순차적으로 형성한다. 여기서, 불순물 접합영역(55)는 활성영역에 형성된 것이다. 그 다음에, 상기 불순물 접합영역(55)이 노출되도록 콘택홀(59)을 형성한다. 그리고, 전체표면상부에 일정두께 산화막(61)을 형성한다. 그리고, 상기 산화막(61)이 두께만큼 이방성식각을 실시하여 상기 콘택홀(59)의 측벽에 산화막(61) 스페이서를 형성한다. 그리고, 상기 노출된 불순물 접합영역(55)에 접속되도록 도전층(63)을 형성한다. 이때, 상기 도전층(63)은 저정전극으로 사용할 수 있다.Referring to FIG. 1, the device isolation oxide film 53, the impurity junction region 55, and the lower insulating layer 57 are sequentially formed on the semiconductor substrate 51. The impurity junction region 55 is formed in the active region. Next, the contact hole 59 is formed to expose the impurity junction region 55. Then, a constant thickness oxide film 61 is formed over the entire surface. In addition, the oxide layer 61 is anisotropically etched by a thickness to form an oxide layer 61 spacer on the sidewall of the contact hole 59. Then, the conductive layer 63 is formed to be connected to the exposed impurity junction region 55. In this case, the conductive layer 63 may be used as a low cathode.
여기서, 상기 콘택홀(59)을 형성하는 식각공정시 상기 불순물 접합영역(55)이 형성된 반도체기판(51)이 손상됨으로써 접합누설전류를 발생시켜 반도체소자의 특성을 저하시킨다.Here, during the etching process of forming the contact hole 59, the semiconductor substrate 51 on which the impurity junction region 55 is formed is damaged, thereby generating a junction leakage current to deteriorate the characteristics of the semiconductor device.
따라서, 본 발명은 종래 기술의 문제점을 해결하기 위하여, 반도체기판의 활성영역에 불순물 접합영역을 형성하고 상기 반도체기판 상부에 하부절연층을 형성한 다음, 상기 불순물 접합영역을 노출시키는 콘택홀을 형성하고 상기 불순물 접합영역의 불순물과 같은 불순물이 함유된 절연막을 전체표면상부에 형성한 다음, 열공정을 실시하여 상기 절연막에 함유된 불순물을 상기 반도체기판에 확산시켜 확산 불순물 접합영역을 형성하고 이방성식각을 실시하여 상기 콘택홀의 측벽에 절연막 스페이서를 형성한 다음, 상기 반도체기판에 접속되도록 도전층을 형성함으로써 접합누설전류의 유출을 최소화하여 반도체소자의 신뢰성을 향상시키는 반도체소자 제조방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the problems of the prior art, an impurity junction region is formed in an active region of a semiconductor substrate, a lower insulating layer is formed on the semiconductor substrate, and then contact holes are formed to expose the impurity junction region. And an insulating film containing impurities such as impurities in the impurity junction region is formed over the entire surface, and then a thermal process is performed to diffuse the impurities contained in the insulating film onto the semiconductor substrate to form a diffusion impurity junction region and anisotropic etching. The present invention provides a method for fabricating a semiconductor device which improves reliability of semiconductor devices by minimizing leakage of junction leakage current by forming insulating film spacers on sidewalls of the contact holes and then forming conductive layers to be connected to the semiconductor substrates. There is this.
이상의 목적을 달성하기 위한 본 발명의 특징은, 반도체기판 상부에 소자 분리절연막, 불순물 접합영역 및 하부절연층을 형성하는 공정과, 상기 반도체기판의 일정부분을 노출시키는 콘택홀을 형성하는 공정과, 상기 전체표면상부에 절연막을 일정두께 형성하는 공정과, 열공정을 실시하여 상기 절연막에 함유된 불순물을 상기 노출된 반도체기판에 확산시켜 확산 불순물 접합영역을 형성하는 공정과, 상기 절연막을 이방성식각하여 절연막 스페이서를 형성하는 공정과, 상기 노출된 반도체기판에 접속되도록 도전층을 콘택시키는 공정을 포함하는 반도체소자 제조방법에 있어서, 상기 절연막은 상기 불순물 접합영역의 불순물과 같은 특성을 갖는 불순물이 함유된 산화막으로 형성된 것이다.Features of the present invention for achieving the above object is a step of forming a device isolation insulating film, an impurity junction region and a lower insulating layer on the semiconductor substrate, forming a contact hole for exposing a portion of the semiconductor substrate; Forming an insulating film a predetermined thickness over the entire surface, performing a thermal process to diffuse impurities contained in the insulating film to the exposed semiconductor substrate to form a diffusion impurity junction region, and anisotropically etching the insulating film. A method of manufacturing a semiconductor device, comprising: forming an insulating film spacer, and contacting a conductive layer to be connected to the exposed semiconductor substrate, wherein the insulating film contains impurities having the same characteristics as those of the impurity junction region. It is formed of an oxide film.
그리고, 상기 콘택공정이 미스얼라인 된 경우에도 본 발명에 따른 반도체소자 제조방법은 사용되는 것이다.The semiconductor device manufacturing method according to the present invention is used even when the contact process is misaligned.
이하, 첨부된 도면을 참고로하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2a도 및 제2b도는 본 발명의 제1실시예에 따른 반도체소자 제조공정을 도시한 단면도이다.2A and 2B are cross-sectional views showing a semiconductor device manufacturing process according to the first embodiment of the present invention.
제2a도를 참조하면, 반도체기판(11) 상부에 소자분리산화막(13), 불순물접합영역(15) 및 하부절연층(17)을 순차적으로 형성한다. 그리고, 콘택마스크(도시안됨)를 이용한 식각공정으로 상기 반도체기판(11)의 예정된 부분을 노출시키는 콘택홀(19)을 형성한다. 그리고, 전체표면상부에 산화막(21)을 형성한다. 이때, 산화막(21)은 상기 불순물 접합영역(15)을 형성하는 부순물과 같은 불순물이 함유된 산화막으로 형성한다.Referring to FIG. 2A, the device isolation oxide film 13, the impurity junction region 15, and the lower insulating layer 17 are sequentially formed on the semiconductor substrate 11. In addition, a contact hole 19 exposing a predetermined portion of the semiconductor substrate 11 is formed by an etching process using a contact mask (not shown). Then, an oxide film 21 is formed over the entire surface. In this case, the oxide film 21 is formed of an oxide film containing impurities such as impurities that form the impurity junction region 15.
제2b도를 참조하면, 열공정을 실시하여 상기 산화막(21)에 함유된 불순물을 상기 반도체기판(11)에 확산시켜 확산 불순물 접합영역(23)을 형성한다. 그리고, 상기 산화막(21)을 이방성식각하여 상기 콘택홀(19)의 측벽에 산화막(21) 스페이서를 형성한다. 그리고, 상기 반도체기판(11)에 형성된 확산 불순물 접합영역(23) 및 불순물 접함영역(15)에 접속되도록 도전층(25)을 형성한다.Referring to FIG. 2B, a thermal process is performed to diffuse the impurities contained in the oxide film 21 to the semiconductor substrate 11 to form a diffusion impurity junction region 23. The oxide film 21 is anisotropically etched to form spacers of the oxide film 21 on the sidewalls of the contact hole 19. The conductive layer 25 is formed to be connected to the diffusion impurity junction region 23 and the impurity contact region 15 formed on the semiconductor substrate 11.
제3도는 본 발명의 제2실시예에 따라 콘택홀 형성시 미스얼라인이 발생된 반도체소자를 도시한 단면도이다.3 is a cross-sectional view illustrating a semiconductor device in which misalignment is generated when forming a contact hole according to a second embodiment of the present invention.
제3도를 참조하면, 반도체기판(31) 상부에 소자분리산화막(33), 불순물 접합영역(35) 및 하부절연층(37)을 순차적으로 형성한다. 그리고, 콘택마스크(도시안됨)를 이용한 식각공정으로 상기 반도체기판(31)이 노출되도록 콘택홀(39)을 형성한다. 이때, 상기 콘택홀(39)은 미스얼라인이 발생하여 상기 소자분리산화막(33)의 일측을 식각하며 형성한 것이다. 그리고, 상기 콘택홀(39)은 활성영역, 즉 상기 불순물 접합영역(35)을 벗어나 형성된 것이다. 그 다음에, 전체표면 상부에 일정두께 산화막(41)을 형성한다. 이때, 상기 산화막(41)은 상기 불순물 접합영역(35)과 같은 불순물이 함유된 산화막으로 형성한다. 그 후에, 열공정을 실시함으로써 상기 산화막(41)에 함유된 불순물이 상기 반도체기판(31)에 확산되어 확산 불순물 접합영역(43)을 형성한다. 그리고, 상기 산화막(41)을 이방성식각하여 산화막(41) 스페이서를 형성한다. 그리고, 상기 확산 불순물 접합영역(43)에 접속되도록 도전층(45)을 형성한다.Referring to FIG. 3, the device isolation oxide layer 33, the impurity junction region 35, and the lower insulating layer 37 are sequentially formed on the semiconductor substrate 31. In addition, a contact hole 39 is formed to expose the semiconductor substrate 31 by an etching process using a contact mask (not shown). In this case, the contact hole 39 is formed by etching one side of the device isolation oxide film 33 due to misalignment. The contact hole 39 is formed outside the active region, that is, the impurity junction region 35. Then, a constant thickness oxide film 41 is formed over the entire surface. In this case, the oxide film 41 is formed of an oxide film containing impurities such as the impurity junction region 35. Thereafter, by performing a thermal process, impurities contained in the oxide film 41 are diffused into the semiconductor substrate 31 to form a diffusion impurity junction region 43. The oxide film 41 is anisotropically etched to form an oxide film 41 spacer. The conductive layer 45 is formed to be connected to the diffusion impurity junction region 43.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자 제조방법은, 반도체기판 상부에 소자분리절연막, 불순물 접합영역 및 하부절연층을 형성하고 상기 반도체기판의 일정부분이 노출되도록 콘택홀을 형성한 다음, 전체표면상부에 상기 불순물 접합영역을 형성하는 불순물과 같은 특성을 갖는 불순물이 함유된 절연막을 일정두께 형성하고 열공정으로 상기 절연막에 함유된 불순물을 상기 반도체기판에 확산시켜 확산 불순물 접합영역을 형성한 다음, 후공정을 실시함으로써 콘택형성시 발생하기 쉬운 소자의 특성저하를 방지하여 반도체소자의 신뢰성을 향상시키는 잇점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, a device isolation insulating film, an impurity junction region, and a lower insulating layer are formed on a semiconductor substrate, and contact holes are formed to expose a portion of the semiconductor substrate. An insulating film containing an impurity having the same characteristics as the impurity forming the impurity junction region is formed on the surface, and a diffusion impurity junction region is formed by diffusing impurities contained in the insulating film on the semiconductor substrate by a thermal process. In addition, by performing the post-process, it is advantageous to improve the reliability of the semiconductor device by preventing the deterioration of characteristics of the device, which are likely to occur during contact formation.
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