KR0155828B1 - Formation method of contact hole in semiconductor device - Google Patents
Formation method of contact hole in semiconductor device Download PDFInfo
- Publication number
- KR0155828B1 KR0155828B1 KR1019950015916A KR19950015916A KR0155828B1 KR 0155828 B1 KR0155828 B1 KR 0155828B1 KR 1019950015916 A KR1019950015916 A KR 1019950015916A KR 19950015916 A KR19950015916 A KR 19950015916A KR 0155828 B1 KR0155828 B1 KR 0155828B1
- Authority
- KR
- South Korea
- Prior art keywords
- contact hole
- substrate
- forming
- etching
- insulating film
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title abstract description 19
- 230000015572 biosynthetic process Effects 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000005530 etching Methods 0.000 claims abstract description 18
- 238000005468 ion implantation Methods 0.000 claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 10
- 238000001039 wet etching Methods 0.000 claims abstract description 10
- 238000001312 dry etching Methods 0.000 claims abstract description 8
- 150000002500 ions Chemical class 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 11
- 229910052710 silicon Inorganic materials 0.000 abstract description 11
- 239000010703 silicon Substances 0.000 abstract description 11
- 229920000642 polymer Polymers 0.000 abstract description 6
- 238000004140 cleaning Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000779 smoke Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
이온 주입을 이용하여 반도체 기판에 손상을 주지 않고 콘택홀을 형성하는 방법에 관하여 개시한다. 본 발명은 기판 상에 절연막을 형성하는 단계화, 상기 절연막 상에 포토레지스트 패턴을 형성하는 단계와, 상기 포토레지스트 패턴을 식각 마스크로 상기 절연막을 건식 식각하여 상기 기판으로부터 소정의 높이를 갖는 제1 콘택홀을 형성하는 단계와, 상기 제1 콘택홀이 형서된 기판의 전면에 이온 주입을 실시하는 단계와, 상기 식각된 절연막을 습식 식각하여 기판이 노출되는 제2 콘택홀을 형서하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 콘택홀 형성 방법을 제공한다. 본 발명에 의하면, 콘택홀 형성시에 과도 식각으로 한한 콘택 저항 증가 및 누설 전류의 증가를 억제하며 실리콘 기판의 노출에 의한 폴리머를 줄일 수 있다.A method of forming a contact hole without damaging a semiconductor substrate using ion implantation is disclosed. The present invention provides a step of forming an insulating film on a substrate, forming a photoresist pattern on the insulating film, and dry etching the insulating film using the photoresist pattern as an etching mask to have a first height having a predetermined height from the substrate. Forming a contact hole, performing ion implantation on the entire surface of the substrate on which the first contact hole is formed, and wet etching the etched insulating layer to form a second contact hole to expose the substrate; A method of forming a contact hole in a semiconductor device is provided. According to the present invention, it is possible to suppress an increase in contact resistance and an increase in leakage current caused by excessive etching during contact hole formation, and to reduce the polymer due to exposure of the silicon substrate.
Description
제1도는 종래 기술에 의한 반도체 장치의 콘택홀 형성 방법을 성명하기 위하여 나타낸 단면도이다.1 is a cross-sectional view showing a conventional method for forming a contact hole in a semiconductor device.
제2도(a) 내지 제2도(d)는 본 발면에 의한 반도체 장치의 콘택홀 형성 방법을 설명하기 위하여 나타낸 단면도이다.2A to 2D are cross-sectional views for explaining the method for forming a contact hole in a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
18 : 절연막 22 : 제1 콘택홀18: insulating film 22: first contact hole
26 : 제2 콘택홀26: second contact hole
본 발명은 반도체 장치의 콘택홀 형성 방법에 관한 것으로, 특히 이온 주입을 이용하여 반도체 기판에 손상을 주지않고 콘택홀을 형성하는 방법에 관한 것이다.The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a method for forming a contact hole without damaging a semiconductor substrate by using ion implantation.
반도체 기판 상에 형성된 게이트 전극이나 소오스 및 그레인 영역을 금속 배선과 접속시켜 주기 위하여 콘택홀을 형성하여야 한다. 일반적으로, 상기 콘택홀은 게이트 전극이나 소오스 및 드레인 영역이 형성된 반도체 기판 상에 평탄화된 산화막을 형성한 후 이방성 식각 특성을 갖는 건식 식각 방법으로 상기 산화막을 식각한 후 세정하여 형성한다. 그러나, 상기 건식 식각 방법은 이방성 식각 특성을 갖는 장점이 있으나, 실리콘 기판과 산화막 간의 선택비가 그다지 크기 않고 콘택홀을 형성시 실리콘기판의 표면에 손상을 주는 단범이 있다. 여기서, 종래의 건식식각방법을 이용한 종래의 반도체 장치의 콘택홀 형성 방법을 제1도를 이용하여 상세히 설명한다.A contact hole must be formed to connect the gate electrode, the source and the grain region formed on the semiconductor substrate with the metal wiring. In general, the contact hole is formed by forming a planarized oxide film on a semiconductor substrate having a gate electrode or a source and drain region, and then etching and cleaning the oxide film by a dry etching method having anisotropic etching characteristics. However, the dry etching method has an anisotropic etching characteristic, but the selectivity between the silicon substrate and the oxide film is not so large, and there is a shortcoming that damages the surface of the silicon substrate when forming the contact hole. Here, a method of forming a contact hole in a conventional semiconductor device using a conventional dry etching method will be described in detail with reference to FIG. 1.
제1도를 참조하면, 반도체 기판(1) 상에 게이트 절연막(3), 게이트 전극(5) 및 스페이서(7)가 형성되어 있으며, 상기 게이트 전극(5)을 절연하는 절연막(9)이 형성되어 있고, 상기 절연막(9)을 일부 식각하여 소오스 또는 드레인 영역(11)을 오픈하는 콘택홀(13)이 형성되어 있다. 그런데, 상기 콘택홀(13)을 형성할 때 상기 절연막(9)을 과도 식각하게되어 실리콘 기판(1)의 표면은 참조 부호 A로 표시한 바와 같이 하부로 더 식각된다.Referring to FIG. 1, a gate insulating film 3, a gate electrode 5, and a spacer 7 are formed on a semiconductor substrate 1, and an insulating film 9 that insulates the gate electrode 5 is formed. A contact hole 13 is formed in which the insulating layer 9 is partially etched to open the source or drain region 11. However, when the contact hole 13 is formed, the insulating layer 9 is excessively etched so that the surface of the silicon substrate 1 is further etched downward as indicated by the reference numeral A.
따라서, 1G DRAM 이상의 반도체 소자와 같은 얕은 접합 구조를 갖는 소자의 콘택홀 형성시에 셀프얼라인실리시데이션과 같은 공정을 도입하지 않고서는 실리콘 기판 표면의 과도 식각에 의한 접합 부위 (소오스 또는 드레인 부위)의 손상으로 콘택 저항 증가 및 누설 전류의 증가되는 문제점이 있다.Therefore, a junction part (source or drain region) by excessive etching of the silicon substrate surface without introducing a process such as self-aligned silidication in forming a contact hole in a device having a shallow junction structure such as a semiconductor device of 1G DRAM or more. There is a problem in that contact resistance increases and leakage current increases due to the damage.
또한, 실리콘 기판의 표면이 건식 식각에 의하여 노출되었을 때, 시릴콘 기판의 표면에 하드폴리머가 형성된다. 이러한 하드폴리머는 콘택홀의 크기가 작을 경우 후속의 세정 공정시도 하드폴리머가 제거되지 않는 단점이 있다.In addition, when the surface of the silicon substrate is exposed by dry etching, a hard polymer is formed on the surface of the silylcon substrate. Such a hard polymer has a disadvantage in that when the size of the contact hole is small, the hard polymer is not removed even in a subsequent cleaning process.
따라서, 본 발명의 목적은 실리콘 기판의 과도 식각에 의한 콘택 저항의 증가를 억제하고, 실리콘 기판의 표면에 하드폴리머가 형성되지 않는 반도체 장치의 콘택홀 형성 방법을 제공하는데 있다.Accordingly, an object of the present invention is to provide a method for forming a contact hole in a semiconductor device in which an increase in contact resistance due to excessive etching of a silicon substrate is suppressed and a hard polymer is not formed on the surface of the silicon substrate.
상기 목적을 달성하기 위하여, 본 발명은 기판 상에 절연막을 형성하는 단계와, 상기 절연막 상에 포토레지스트 패턴을 형성하는 단계와, 상기 포토레지스트 패턴을 식각 마스크로 상기 절연막을 건식 식각하여 상기 기판으로부터 소정의 높이를 갖는 제1 콘택홀을 형성하는 단계와, 상기 제1 콘택홀이 형성된 기판의 전면에 이온 주입을 실시하는 단계와, 상기 식각된 절연막을 습식 식각하여 기판이 노출되는 제2 콘택홀을 형성하는 단계를 포함하는 것을 특징으로하는 반도체 장치의 콘택홀 형성 방법을 제공한다.In order to achieve the above object, the present invention provides a method of forming an insulating film on a substrate, forming a photoresist pattern on the insulating film, and dry etching the insulating film using the photoresist pattern as an etching mask from the substrate. Forming a first contact hole having a predetermined height, performing ion implantation on the entire surface of the substrate on which the first contact hole is formed, and wet etching the etched insulating layer to expose the second contact hole It provides a method for forming a contact hole of a semiconductor device comprising the step of forming a.
상기 제1 콘택홀을 형성하는 단계 전에 상기 절연막을 등방성 식각하는 단계를 더 포함할 수 있으며, 상기 제1 콘택홀으리 형성시 기판으로부터 소정 높이는 200 ~ 1000Å로 조절한다. 상기 이온 주입은 비소 또는 붕소를 이용하여 1.0E15 ~ 5.0E15 ions/㎠ 범위의 도우즈와 20KeV~50KeV 범위의 에너지로 실시한다.The method may further include isotropically etching the insulating film before the forming of the first contact hole, wherein a predetermined height from the substrate is adjusted to 200 to 1000 kW when the first contact hole is formed. The ion implantation is performed using arsenic or boron with a dose ranging from 1.0E15 to 5.0E15 ions / cm 2 and energy ranging from 20KeV to 50KeV.
본 발명에 의하면, 콘택홀 형성시에 과도 식각으로 한한 콘택저항 증가 및 누설 전류의 증가를 억제하며 실리콘 기판의 노출에 의한 폴리며를 줄일 수 있다.According to the present invention, it is possible to suppress an increase in contact resistance and an increase in leakage current caused by excessive etching at the time of forming a contact hole, and to reduce a polygon due to exposure of a silicon substrate.
이하, 본 발명의 실시예를 첨부 도면을 참조하여 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제2도(a) 내지 제2도(d)는 본 발명에 따른 반도체 장치의 콘택홀 형성 방법을 설명하기 위하여 도시한 단면도들이다.2A to 2D are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to the present invention.
제2도(a)는 반도체 기판 상에 게이트 전극, 절연박 및 포토레지스트 패턴을 형성하는 단계를 나타낸다.2A illustrates a step of forming a gate electrode, an insulating foil, and a photoresist pattern on a semiconductor substrate.
구체적으로, 반도체 기판(10) 상에 기이트 절연막(12), 게이트 전극(14) 및 스페이서(16)를 형성한다. ㅅ아기 게이트 전극(14)의 형성은 폴리실리콘막이나 폴리사이드막으로 형성할 수 있다. 이어서, 상기 게이트 전극(14)이 형성된 기판의 전면에 절연막(18)을, 예컨대 산화막으로 형성한다. 상기 절연막(18)은 열처리를 통하여 평탄화시킬 수도 있다. 다음에, 상기 절연막(18) 상에 사진 식각 공정을 이용하여 포토레지스트 패턴(20)을 형성한다.Specifically, the substrate insulating film 12, the gate electrode 14, and the spacer 16 are formed on the semiconductor substrate 10. The gate gate electrode 14 can be formed of a polysilicon film or a polyside film. Subsequently, an insulating film 18 is formed of, for example, an oxide film on the entire surface of the substrate on which the gate electrode 14 is formed. The insulating film 18 may be planarized by heat treatment. Next, the photoresist pattern 20 is formed on the insulating layer 18 by using a photolithography process.
제2도(b)는 상기 저연막(18)을 1차로 식각하여 제1 콘택홀(22)을 형성하는 단계를 나타낸다.FIG. 2B illustrates a step of first etching the low smoke film 18 to form the first contact hole 22.
구체적으로, 상기 포토레지스트 패턴(20)을 식각 마스크로 상기 절연막을 식각하여 제1 콘택홀(22)을 형성한다. 이때 식각 시간을 조절하여 제1도(b)에 도시한 바와 같이 실리콘 기판으로부터 200~1000Å 정도의 높이에 제1 콘택홀의 하부가 오도록 조절하며, 상기 제1 콘택홀의 폭은 제조되는 반도체 장치의 디자인 룰보다 다소 작게한다. 또한, 상기 제1 콘택홀(22) 형성시 후공정에서 제1 콘택홀에 침적되는 도전막의 스텝커버리지를 개선하기 위하여 상기 절연막(18)을 1차로 습식 식각한 후 2차로 건식 식각을 실시하여도 되며 상기 1차 습식 식각 없이 바로 이방식 식각 특성을 갖는 건식 식각을 실시할 수도 있다.Specifically, the insulating layer is etched using the photoresist pattern 20 as an etch mask to form a first contact hole 22. In this case, as shown in FIG. 1 (b), the etching time is adjusted so that the lower portion of the first contact hole is provided at a height of about 200 to 1000 microseconds from the silicon substrate, and the width of the first contact hole is designed to be manufactured. Slightly smaller than the rule. In addition, in order to improve step coverage of the conductive film deposited in the first contact hole in a later step in forming the first contact hole 22, the wet etching of the insulating film 18 may be performed after the primary wet etching. It is also possible to perform a dry etching having a straight etching method without the first wet etching.
제2도(c)는 상기 식각된 절연막(18)이 형성된 기판(10)의 전면에 이온 주입(24)을 실시하는 단계를 나타낸다.FIG. 2C illustrates a step of performing ion implantation 24 on the entire surface of the substrate 10 on which the etched insulating layer 18 is formed.
구체적으로, 상기 식각된 절연막(18)이 형성된 기판의 전면에 이온 주입(24)을 실시한다. 상기 이온 주입(24)은 비소, 붕소를 사용하여 1.0E15~5.0E15 ions/㎠의 도즈와 20KeV~50KeV의 에너지로 실시한다. 상기 이온 주입은 후공정에서 반도체 기판의 표면을 오픈하는 콘택홀을 동방성 식각 특성을 갖는 습식 식각 방법으로 형성하기 위하여 실시한다. 이렇게 이온 주입된 절연막 부분(B)은 화학적 및 물리적 성질이 변화되어 이온 주입되지 않는 절연막(18)보다 습식 식각 속도가 10~20배 정도 빠르게 된다.Specifically, the ion implantation 24 is performed on the entire surface of the substrate on which the etched insulating layer 18 is formed. The ion implantation 24 is carried out with a dose of 1.0E15 to 5.0E15 ions / cm 2 and energy of 20KeV to 50KeV using arsenic and boron. The ion implantation is performed to form a contact hole for opening the surface of the semiconductor substrate by a wet etching method having an isotropic etching characteristic in a later step. The ion implanted insulating layer portion B is changed in chemical and physical properties such that the wet etching rate is 10 to 20 times faster than the insulating layer 18 which is not ion implanted.
제2도(d)는 절연막(18)을 2차로 식각하여 기판의 표면을 노출하는 제2 콘택홀(26)을 형성하는 단계를 나타낸다.FIG. 2D illustrates a step of forming the second contact hole 26 exposing the surface of the substrate by second etching the insulating film 18.
구체적으로, 먼저, 포토레지스트 패턴(20)을 제거한다. 이어서, 이온 주입으로 인하여 습식 식각 속도가 빠른 절연막 부분(제2도(c)의 B부분)을 습식 식각하여 기판(10)의 표면을 노출하는 제2 콘택홀(26)을 형성한다. 다음에, 제2 콘택홀이 형성된 기판을 세정하여 반도체 장치의 콘택홀을 완성한다.Specifically, first, the photoresist pattern 20 is removed. Subsequently, a second contact hole 26 exposing the surface of the substrate 10 is formed by wet etching the insulating portion (B portion of FIG. 2C) having a high wet etching rate due to ion implantation. Next, the substrate on which the second contact hole is formed is cleaned to complete the contact hole of the semiconductor device.
상술한 바와 같이 본 발명에 의항면 콘택홀 형성시에 과도한 식각을 하지 않아 콘택 저항 증가 및 누설 전류의 증가를 억제하며, 실리콘 기파느이 노출에 의한 폴리머를 줄일 수 있다.As described above, excessive etching is not performed at the time of forming the surface contact hole according to the present invention, thereby suppressing an increase in contact resistance and an increase in leakage current, and reducing the polymer due to exposure to silicon waves.
이상, 본 발명을 구체적으로 설명하였지만, 본 발명은 이에 한정되는 것이 아니고, 당없자의 통상적인 지식의 범위에서 그 변형이나 개량이 가능하다.As mentioned above, although this invention was demonstrated concretely, this invention is not limited to this, A deformation | transformation and improvement are possible in the range of ordinary knowledge of a sugar free person.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950015916A KR0155828B1 (en) | 1995-06-15 | 1995-06-15 | Formation method of contact hole in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950015916A KR0155828B1 (en) | 1995-06-15 | 1995-06-15 | Formation method of contact hole in semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970003463A KR970003463A (en) | 1997-01-28 |
| KR0155828B1 true KR0155828B1 (en) | 1998-12-01 |
Family
ID=19417237
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950015916A KR0155828B1 (en) | 1995-06-15 | 1995-06-15 | Formation method of contact hole in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0155828B1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100526573B1 (en) * | 1998-06-30 | 2006-01-12 | 주식회사 하이닉스반도체 | Metal wiring formation method of semiconductor device |
| KR102207373B1 (en) | 2020-07-13 | 2021-01-26 | 주식회사 파세코 | Frame assembly structure for installing window type air-conditioner on window sill |
-
1995
- 1995-06-15 KR KR1019950015916A patent/KR0155828B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR970003463A (en) | 1997-01-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6218251B1 (en) | Asymmetrical IGFET devices with spacers formed by HDP techniques | |
| JPH0951033A (en) | Preparation of integrated circuit chip | |
| US6281131B1 (en) | Methods of forming electrical contacts | |
| KR0155828B1 (en) | Formation method of contact hole in semiconductor device | |
| US6200887B1 (en) | Method to form a smooth gate polysilicon sidewall in the fabrication of integrated circuits | |
| KR100209280B1 (en) | Method for forming a contact of semiconductor device | |
| US5770464A (en) | Method for fabricating semiconductor devices having lightly doped drain | |
| JPH0982949A (en) | Semiconductor device and the manufacture | |
| KR100324933B1 (en) | method for forming self-align contact hole in semiconductor device | |
| KR100226733B1 (en) | Manufacture of semiconductor device | |
| KR100272264B1 (en) | Manufacturing method of semiconductor device | |
| KR100273685B1 (en) | Method for forming semiconductor device | |
| US7517755B2 (en) | Method for fabricating semiconductor device | |
| KR100215871B1 (en) | Method for fabricating semiconductor device | |
| KR100298463B1 (en) | Method for manufacturing semiconductor device the same | |
| US6936517B2 (en) | Method for fabricating transistor of semiconductor device | |
| KR100489588B1 (en) | Manufacturing Method of Top Gate Thin Film Transistor | |
| KR0147466B1 (en) | Semiconductor device manufacturing method | |
| KR0172513B1 (en) | Method for forming contact of semiconductor device | |
| KR100324325B1 (en) | Manufacturing method for mostransistor for electro static discharge | |
| KR100358174B1 (en) | Method for forming source and drain of semiconductor device | |
| KR100364794B1 (en) | Method for fabricating of semiconductor device | |
| KR100567047B1 (en) | Menufacturing method for mos transistor | |
| KR100342394B1 (en) | manufacturing method of semiconductor devices | |
| KR0162141B1 (en) | Method of manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20090714 Year of fee payment: 12 |
|
| LAPS | Lapse due to unpaid annual fee |