KR0152954B1 - Method of forming insulating film for semiconductor - Google Patents
Method of forming insulating film for semiconductor Download PDFInfo
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- KR0152954B1 KR0152954B1 KR1019950011268A KR19950011268A KR0152954B1 KR 0152954 B1 KR0152954 B1 KR 0152954B1 KR 1019950011268 A KR1019950011268 A KR 1019950011268A KR 19950011268 A KR19950011268 A KR 19950011268A KR 0152954 B1 KR0152954 B1 KR 0152954B1
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- film
- antioxidant
- forming
- buffer
- isolation
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000002955 isolation Methods 0.000 claims abstract description 31
- 239000003963 antioxidant agent Substances 0.000 claims abstract description 27
- 230000003078 antioxidant effect Effects 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 8
- 230000003647 oxidation Effects 0.000 claims abstract description 8
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 8
- 150000004767 nitrides Chemical class 0.000 claims description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 230000003064 anti-oxidating effect Effects 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 240000006829 Ficus sundaica Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
본 발명은 반도체 소자의 격리막 형성방법에 관한 것으로, 반도체 기판 위에 제1완충막과 제1산화방지막, 제2완충막 및, 제2산화방지막을 순차적으로 형성하는 공정과; 상기 반도체 기판의 격리영역 상의 제1산화방지막과 제2완충막 및 제2산화방지막을 식각하여 능동영역패턴을 형성하는 공정과; 상기 능동영역 패턴의 양 측면에 제3산화방지막을 형성하는 공정 및; 열산화공정에 의해 격리영역에 격리막을 형성하는 공정을 거쳐 소자 제조를 완료하므로서, 격리막 성장시 능동영역의 기판 상에 발생하는 스트레스를 줄일 수 있을 뿐 아니라 동시에 능동영역으로 확장되는 격리영역의 확장길이를 효과적으로 감소시킬 수 있고, 또한 공정단순화를 기할 수 있는 고신뢰성의 반도체 소자 제조기술을 구현할 수 있게 된다.The present invention relates to a method for forming an isolation film of a semiconductor device, comprising: sequentially forming a first buffer film, a first antioxidant film, a second buffer film, and a second antioxidant film on a semiconductor substrate; Etching the first antioxidant film, the second buffer film, and the second antioxidant film on the isolation region of the semiconductor substrate to form an active region pattern; Forming third antioxidant films on both side surfaces of the active region pattern; By completing the process of forming the isolation layer in the isolation region by the thermal oxidation process, it is possible to reduce the stress generated on the substrate of the active region during the growth of the isolation layer and at the same time to extend the isolation region to the active region. Can be effectively reduced, and it is possible to implement a highly reliable semiconductor device manufacturing technology that can simplify the process.
Description
제1(a)도 내지 제1(c)도는 종래 기술에 따른 반도체 소자의 PBR(poly-buffer-recessed) 국부산화 제조공정을 도시한 공정수순도.1 (a) to (c) is a process flow diagram showing a poly-buffer-recessed local oxidation manufacturing process of a semiconductor device according to the prior art.
제2(a)도 내지 제2(c)도는 종래 기술에 따른 반도체 소자의 RLS(reverse L-shape sealed) PBL(poly-buffer LOCOS) 제조공정을 도시한 공정수순도.2 (a) to 2 (c) is a process flowchart showing a reverse L-shape sealed (RLS) poly-buffer LOCOS (PBL) manufacturing process of a semiconductor device according to the prior art.
제3(a)도 내지 제3(c)도는 종래 기술에 따른 반도체 소자의 NCL(nitride-clad LOCOS) 제조공정을 도시한 공정수순도.3 (a) to 3 (c) are process flowcharts showing a nitride-clad LOCOS (NCL) manufacturing process of a semiconductor device according to the prior art.
제4(a)도 내지 제4(e)도는 본 발명에 따른 반도체 소자의 격리막 형성방법을 도시한 공정수순도.4 (a) to 4 (e) are process steps showing a method of forming an isolation film for a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
S : 기판 100 : 제1완충막S: Substrate 100: First buffer film
102 : 제1산화방지막 104 : 제2완충막102: first antioxidant film 104: second buffer film
106 : 제2산화방지막 108 : 제3산화방지막106: second antioxidant film 108: third antioxidant film
110 : 격리막110: separator
본 발명은 반도체 소자의 격리막 형성방법에 관한 것으로, 특히 산화방지막으로 밀폐된 완충막을 갖는 반도체 소자의 격리막 형성방법에 관한 것이다.The present invention relates to a method for forming a separator of a semiconductor device, and more particularly, to a method for forming a separator of a semiconductor device having a buffer film sealed with an antioxidant film.
반도체 소자의 집적도가 증가함에 따라 기존의 산화막 격리 공정인 국부산화(local oxidation of silicon:이하, LOCOS라 한다) 공정을 복잡하게 개선한 공정 예컨대, PBR LOCOS 공정, RLS PBL 공정, NCL 공정 등을 사용하여 감소된 능동영역 및 격리영역의 길이 등을 새로이 정의하여 사용되고 있다.As the degree of integration of semiconductor devices increases, the process of complex improvement of the existing oxidation isolation process, which is a local oxidation of silicon (hereinafter referred to as LOCOS) process, for example, PBR LOCOS process, RLS PBL process, NCL process, etc. are used. Therefore, the length of reduced active area and isolation area is newly defined and used.
이중 제1(a)도 내지 제1(c)도에 도시된 상기 PBR(poly-buffer-recessed) LOCOS 공정은 기판(S)에 가해지는 스트레스를 줄이기 위하여 기판(S) 위에 완충산화막(1)을 성장한 후 다결정 실리콘(3)과 질화막인 Si3N4(5)을 순차적으로 화학기상증착(CVD)하고, 격리영역이 형성될 부위의 질화막(5)과 다결정 실리콘(3) 및 완충산화막(1)을 식각한뒤 격리영역의 확장을 줄이기 위하여 상기 기판(S)을 250-2000Å의 깊이까지 식각하여 제1(a)도에 도시된 바와 같은 패턴을 형성하고, 이어서 상기 능동영역의 양 측벽 및 기판의 격리영역에 다시 완충산화막(1')을 성장시킨 후 질화막(5')을 증착하여 식각된 기판의 측벽에 질화막이 남도록 에칭하여 제1(b)도에 도시된 바와 같은 패턴을 형성한다. 이 상태에서 열처리하여 격리막(7)을 성장시키면 제1(c)도에 도시된 바와 같은 패턴을 얻게 된다.The poly-buffer-recessed (PBR) LOCOS process shown in FIGS. 1 (a) to 1 (c) is a buffer oxide film (1) on the substrate (S) to reduce the stress applied to the substrate (S). After the growth, polycrystalline silicon (3) and Si 3 N 4 (5), which is a nitride film, are sequentially subjected to chemical vapor deposition (CVD). After etching 1), the substrate S is etched to a depth of 250-2000 Å to reduce the expansion of the isolation region to form a pattern as shown in FIG. 1 (a), and then both sidewalls of the active region. After growing the buffer oxide film 1 'in the isolation region of the substrate, the nitride film 5' is deposited to etch the nitride film to remain on the sidewall of the etched substrate, thereby forming a pattern as shown in FIG. 1 (b). do. When the isolation film 7 is grown by heat treatment in this state, a pattern as shown in FIG. 1 (c) is obtained.
다음으로 제2(a)도 내지 제2(c)도에 도시된 RLS(reverse L-shape sealed) PBL(poly-buffer LOCOS) 공정은 기판(S)에 가해지는 스트레스를 줄이기 위하여 완충산화막(1) 위에 다결정 실리콘(3)을 증착한 후 질화막(5)을 증착하고 있으며, 이 경우에는 격리영역의 확장을 방지하기 위하여 다결정 실리콘(3) 밑의 완충산화막(1) 양측 에지 부분을 상기 완충산화막이 상기 다결정 실리콘보다 좁은 폭을 가지도록 식각한 후 질화막으로 이러한 부분을 채우고, 반응성이온식각(RIE)법으로 상기 질화막을 식각하여 제2(c)도에 도시된 바와 같은 패턴을 형성한다.Next, the reverse L-shape sealed (RLS) poly-buffer LOCOS (PLL) process shown in FIGS. 2A to 2C is used to reduce the stress applied to the substrate S. ) And then the nitride film 5 is deposited. In this case, in order to prevent the expansion of the isolation region, the edge portions of both sides of the buffer oxide film 1 under the polycrystalline silicon 3 are deposited. After etching to have a narrower width than the polycrystalline silicon, this portion is filled with a nitride film, and the nitride film is etched by reactive ion etching (RIE) to form a pattern as shown in FIG. 2 (c).
반면, 제3(a)도 내지 제3(c)도에 도시된 NCL(nitride-clad LOCOS) 공정은 기판(S) 상의 완충산화막(1) 위에 다결정 실리콘을 증착하지 않고 직접 질화막(5)을 증착한 경우를 나타낸 것으로, 이 경우에도 격리 영역의 확장을 줄이기 위하여 질화막(5) 밑의 완충산화막(1) 양측 에지 부분을 식각한 후, 다시 질화막(5')으로 상기 산화막(1)의 식각된 부분을 채우고, 격리영역이 형성될 부위의 질화막(5')을 식각한뒤 열처리하여 제3(c)도에 도시된 바와 같은 패턴을 형성한다.On the other hand, in the nitride-clad LOCOS (NCL) process shown in FIGS. 3A to 3C, the nitride film 5 is directly deposited without depositing polycrystalline silicon on the buffer oxide film 1 on the substrate S. FIG. In this case, in order to reduce the expansion of the isolation region, the edge portions of both sides of the buffer oxide film 1 under the nitride film 5 are etched, and then the oxide film 1 is etched with the nitride film 5 '. And then heat-treat the nitride film 5 'of the portion where the isolation region is to be formed to form a pattern as shown in FIG. 3 (c).
그러나 이러한 공정을 이용하여 격리막을 형성할 경우, PBR LOCOS 공정에서는 기판을 식각하고 측벽 질화막을 형성한 것으로 격리영역의 확장은 줄어드나 기판에 스트레스가 야기되는 문제점이 발생되며, RLS PBL 공정에서는 다결정 실리콘 밑의 완충산화막 양측 에지 부분을 식각한 후 다시 완충산화막을 형성하고 CVD 질화막을 증착하는 등의 복잡한 공정이 요구되는 단점을 가지게 되고, NCL 공정에서는 완충산화막 위에 바로 질화막이 증착되므로 기판에 스트레스가 가해지지 않도록 하기 위하여 완충산화막과 질화막의 두께비를 적절히 조절해야 하는 어려움이 따라 기판에 스트레스가 야기될 가능성이 크며, 또한 이 경우 역시 RLS PBL 공정에서와 같이 완충산화막을 질화막의 밑 부분까지 식각해야 하므로 공정이 복잡하고 까다롭다는 문제점을 안게 된다.However, when the isolation layer is formed using this process, the substrate is etched and the sidewall nitride layer is formed in the PBR LOCOS process, so that the expansion of the isolation region is reduced, causing stress on the substrate. In the RLS PBL process, polycrystalline silicon is formed. After etching the edges of both sides of the buffer oxide layer below, a complicated process such as forming a buffer oxide film and depositing a CVD nitride film is required.In the NCL process, a nitride film is deposited directly on the buffer oxide film, so that stress is applied to the substrate. In order to prevent this from happening, there is a high possibility of causing stress on the substrate due to difficulty in properly adjusting the thickness ratio between the buffer oxide film and the nitride film. You get this complicated and tricky problem .
이에 본 발명은 상기와 같은 문제점을 해결하기 위하여 이루어진 것으로, 산화방지막으로 밀폐된 완충막을 갖도록 소자를 형성하므로서 반도체 기판에 인가되는 스트레스를 감소시킴과 동시에 격리영역의 확장을 줄일 수 있도록 한 반도체 소자의 격리막 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, and by forming the device to have a buffer film sealed with an anti-oxidation film to reduce the stress applied to the semiconductor substrate and at the same time reduce the expansion of the isolation region of the semiconductor device The purpose is to provide a method of forming a separator.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 격리막 제조방법은 반도체 기판 위에 제1완충막과 제1산화방지막, 제2완충막 및, 제2산화방지막을 순차적으로 형성하는 공정과; 상기 반도체 기판의 격리영역 상의 제1산화방지막과 제2완충막 및 제2산화방지막을 식각하여 능동영역 패턴을 형성하는 공정과; 상기 능동영역 패턴의 양 측면에 제3산화방지막을 형성하는 공정 및; 열산화공정에 의해 격리영역에 격리막을 형성하는 공정을 포함하여 이루어짐을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a separator of a semiconductor device, the method including sequentially forming a first buffer film, a first antioxidant film, a second buffer film, and a second antioxidant film on a semiconductor substrate; Etching the first antioxidant layer, the second buffer layer, and the second antioxidant layer on the isolation region of the semiconductor substrate to form an active region pattern; Forming third antioxidant films on both side surfaces of the active region pattern; And forming a separator in the isolation region by a thermal oxidation process.
상기 공정 결과, 능동영역으로 확장되는 격리막의 확장길이를 효과적으로 줄일 수 있게 된다.As a result of this process, it is possible to effectively reduce the extension length of the separator extending into the active region.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
제4(a)도 내지 제4(e)도는 본 발명에 따른 반도체 소자의 격리막 형성방법을 도시한 공정수순도를 나타낸 것으로, 상기 도면을 참조하여 그 제조공정을 살펴보면 아래와 같다.4 (a) to 4 (e) show a process flow diagram illustrating a method of forming an isolation film of a semiconductor device according to the present invention. The manufacturing process will be described below with reference to the drawings.
먼저, 제4(a)도에 도시된 바와 같이 반도체 기판(S) 위에 제1완충막(100)으로 산화막을 50-500Å의 두께로 증착하고, 상기 산화막(100) 위에 제1산화방지막으로서 50-500Å의 두께를 갖는 얇은 질화막(102)과 제2완충막으로서 100-1000Å의 두께를 갖는 다결정 실리콘막(104)을 증착한 후, 상기 다결정 실리콘막(104) 위에 제2산화방지막으로서 500-5000Å의 두께를 갖는 두꺼운 질화막(106)을 증착한다.First, as shown in FIG. 4 (a), an oxide film is deposited on the semiconductor substrate S with the first buffer film 100 to a thickness of 50 to 500 GPa, and 50 as the first antioxidant film on the oxide film 100. After depositing a thin nitride film 102 having a thickness of -500 GPa and a polycrystalline silicon film 104 having a thickness of 100-1000 GPa as the second buffer film, 500-as a second antioxidant film on the polycrystalline silicon film 104. A thick nitride film 106 having a thickness of 5000 kPa is deposited.
이때 상기 산화막(100)과 제1산화방지막(102)의 두께비는 1:1 이하의 비를 갖도록 형성될 수도 있으므로 본 발명의 경우, 일반적인 LOCOS 방법에 의해 격리막을 형성했을때 보다 능동영역에서 발생하는 스트레스가 줄어 들게 된다.At this time, since the thickness ratio of the oxide film 100 and the first antioxidant film 102 may be formed to have a ratio of 1: 1 or less, in the case of the present invention, when the isolation film is formed by a general LOCOS method, The stress is reduced.
그후 제4(a)도에 도시된 바와 같이 반도체 기판(S)의 격리영역 상의 제2산화방지막(106)과 제2완충막(104)인 다결정 실리콘막 및 제1산화방지막(102)을 식각하여 능동영역의 패턴을 형성하고, 제4(c)도에 도시된 바와 같이 상기 능동영역 패턴의 양 측벽과 상부 및 제1완충막(100) 위에 제3산화방지막으로서 50-700Å의 두께를 갖는 질화막(108)을 증착한다.Thereafter, as shown in FIG. 4 (a), the polycrystalline silicon film and the first antioxidant film 102, which are the second antioxidant film 106 and the second buffer film 104, on the isolation region of the semiconductor substrate S are etched. To form a pattern of the active region, and as shown in FIG. 4 (c), a thickness of 50-700 kPa as a third anti-oxidation layer on both sidewalls of the active region pattern, the upper portion, and the first buffer layer 100 is shown. The nitride film 108 is deposited.
그 다음 제4(d)도에 도시된 바와 같이 상기 질화막(108)을 식각하여 상기 능동영역 패턴의 양 측면에만 질화막(108)이 남도록 하고, 반도체 기판(S)의 격리영역 상의 산화막(100)을 제거한다.Next, as shown in FIG. 4 (d), the nitride film 108 is etched so that the nitride film 108 remains on both sides of the active region pattern, and the oxide film 100 on the isolation region of the semiconductor substrate S is formed. Remove it.
그후 제4(e)도에 도시된 바와 같이 열산화공정에 의해 상기 격리영역에 격리막(110)을 형성하므로서 본 공정을 완료한다.Thereafter, as shown in FIG. 4 (e), the isolation layer 110 is formed in the isolation region by a thermal oxidation process, thereby completing this process.
이와 같이 측면 질화막(108)을 형성하면, 결과적으로 다결정 실리콘(104)이 제1 내지 제3산화방지막인 질화막(102),(106),(108)에 의해 완전히 밀폐된 구조를 가지게 되므로 기판에 발생하는 스트레스를 작게할 수 있을 뿐 아니라 열산화공정에 의해 형성되는 격리막의 능동영역으로의 침투를 작게 할 수 있으며, 이로 인해 격리막 성장시 격리영역의 확장길이 또한 줄일 수 있게 된다.As such, when the side nitride film 108 is formed, the polycrystalline silicon 104 has a structure completely sealed by the nitride films 102, 106, and 108, which are the first to third antioxidant films. In addition to reducing the stress generated, it is possible to reduce the penetration of the separator formed by the thermal oxidation process into the active region, thereby reducing the extension length of the separator during growth of the separator.
또한 본 발명의 경우에는 PBR LOCOS에서 요구되는 기판 식각 공정이나 RLS PBL 및 NCL에서 요구되는 완충산화막의 등방성 식각 등과 같은 공정이 요구되지 않으므로 공정이 단순하다는 이점을 가진다.In addition, in the case of the present invention, since a process such as a substrate etching process required in PBR LOCOS or an isotropic etching of buffer oxide film required in RLS PBL and NCL is not required, the process is simple.
상술한 바와 같이 본 발명에 의하면, 1) 격리막 성장시 능동영역의 기판 상에 발생하는 스트레스를 줄일 수 있고, 2) 동시에 능동영역으로 확장되는 격리영역의 확장길이를 효과적으로 감소시킬 수 있으며, 3) 공정단순화를 기할 수 있는 고신뢰성의 반도체 소자 제조기술을 구현할 수 있게 된다.As described above, according to the present invention, 1) it is possible to reduce the stress generated on the substrate of the active region during the growth of the separator, 2) at the same time can effectively reduce the extension length of the isolation region extending to the active region, 3) It is possible to implement a highly reliable semiconductor device manufacturing technology that can simplify the process.
Claims (8)
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