KR100303438B1 - Device isolation method of semiconductor device - Google Patents
Device isolation method of semiconductor device Download PDFInfo
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- KR100303438B1 KR100303438B1 KR1019940012841A KR19940012841A KR100303438B1 KR 100303438 B1 KR100303438 B1 KR 100303438B1 KR 1019940012841 A KR1019940012841 A KR 1019940012841A KR 19940012841 A KR19940012841 A KR 19940012841A KR 100303438 B1 KR100303438 B1 KR 100303438B1
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- 238000002955 isolation Methods 0.000 title claims description 22
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000000034 method Methods 0.000 claims abstract description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 35
- 150000004767 nitrides Chemical class 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 238000000206 photolithography Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract description 6
- 241000293849 Cordylanthus Species 0.000 abstract description 3
- 238000001259 photo etching Methods 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 210000003323 beak Anatomy 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02595—Microstructure polycrystalline
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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Abstract
Description
제1(a) 내지 제1(g)도는 종래기술에 따른 반도체 장치의 소자 분리방법을 보여주는 공정수순의 단면도.1 (a) to 1 (g) are cross-sectional views of a process procedure showing a device isolation method of a semiconductor device according to the prior art.
제2도는 반도체 소자의 활성영역과 비활성영역의 패턴을 보여주는 평면도.2 is a plan view showing a pattern of an active region and an inactive region of a semiconductor device.
제3(a) 내지 제3(h)도는 본 발명에 따른 반도체 장치의 소자 분리방법을 보여주는 공정수순의 단면도.3 (a) to 3 (h) are cross-sectional views of a process procedure showing a device separation method of a semiconductor device according to the present invention.
제4도는 소자분리공정이 완료된 직후의 샘(SEM; scanning electron microscope) 사진으로 찍은 단면도로서, 4(a)도는 본 발명에 따른 소자 분리 프로파일을 보여주는 단면도;4 is a cross-sectional view taken with a scanning electron microscope (SEM) picture immediately after the device isolation process is completed, and FIG. 4 (a) is a cross-sectional view showing a device isolation profile according to the present invention;
제4(b)도는 본 발명에서 다결정 실리콘 측벽이 오우버 에치되지 않을 경우에 생기는 산화막 돌기를 보여주는 단면도;Figure 4 (b) is a cross-sectional view showing the oxide film projections generated when the polycrystalline silicon sidewall is not over-etched in the present invention;
제4(c)도는 제3(d)도에서 생긴 공동에 다결정이 매립되어 필드 산화막이 성장될 때의 프로파일을 보여주는 단면도.4 (c) is a cross-sectional view showing a profile when a polycrystalline is buried in a cavity formed in FIG. 3 (d) to grow a field oxide film.
제5도는 제2도 패턴에 따른 실제 형상을 보여주는 샘 사진의 평면도이다.5 is a plan view of a spring photograph showing the actual shape according to the second FIG. Pattern.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 실리콘 기판 22 : 패드 산화막21 silicon substrate 22 pad oxide film
23 : 질화막 24 : 공동(cavity)23 nitride film 24 cavity
25 : 얇은 산화막 26 : 다결정 실리콘막25 thin oxide film 26 polycrystalline silicon film
27 : 다결정 실리콘 측벽 38 : 필드 산화막27 polycrystalline silicon sidewall 38 field oxide film
29 : 산화막 돌기29: oxide film projection
본 발명은 반도체 장치의 소자 분리방법에 관한 것으로서, 더욱 상세하게는 소자 분리 공정중 발생하는 산화막 돌출 부위를 평탄화하기 위하여 별도의 평탄화막을 침적하여 에치백(etch back)하는 공정을 사용하지 않고 측벽 형성시 적절하게 오우버 에치(over etch)하여 양호한 필드(field) 산화막을 형성할 수 있도록 한 반도체 장치의 소자 분리방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device, and more particularly, to form a sidewall without using a process of depositing and etching back a planarization film in order to planarize an oxide projecting portion generated during the device isolation process. The present invention relates to a method of isolating elements of a semiconductor device in which over-etching is performed in a timely manner to form a good field oxide film.
지금까지 집적회로에 있어 소자를 분리시키기 위한 다양한 기술이 개발되어 왔다. 그 한가지 이유는 다른 IC 종류들 (예를들면 NMOS, CMOS, 그리고 bipolar)이 다소 다른 분리 기법을 요구하고 있기 때문이다. 더욱이, 다양한 분리 기술들이 최소 분 폭, 표면 평탄화, 공정 복합성, 그리고 분리구조의 공정중에 발생하는 결함의 밀도에 관하여 다른 모습을 보여준다. 특별한 회로 적용을 위하여 분리 기술을 선택할 때 이들 특징들 중에서 유리한 것이 이용되어질 수 있다. 특히 MOS 구조에서 개발된 가장 중요한 기법은 LOCOS isolation(LOCal Oxidation of Silicon)으로서 이것은 기판의 비활성화(또는 필드) 영역에서 반쯤 우묵한 산화막의 형성을 포함한다.To date, various techniques have been developed for isolating devices in integrated circuits. One reason is that different IC types (eg NMOS, CMOS, and bipolar) require somewhat different isolation techniques. Moreover, various separation techniques show different aspects in terms of minimum width, surface planarization, process complexity, and the density of defects occurring during the processing of the isolation structure. Advantageous of these features can be used when selecting a separation technique for a particular circuit application. In particular, the most important technique developed in the MOS structure is LOCOS isolation (LOCal Oxidation of Silicon), which includes the formation of an oxide film that is half hollow in the inactive (or field) region of the substrate.
그런데, 이러한 LOCOS 구조에서는 실리콘 기판위에 패드 산화막을 얇게 형성시키고 그 위에 질화막을 형성한 다음 활성영역을 패터닝하고 필드산화를 수행하게 된다. 이 때 질화막 위에서는 산화막이 거의 자라지 않기 때문에 활성 영역과 비활성 영역 사이에서 산화막이 새부리 모양을 갖는 소위 버즈 빅 (Bird′s beak)현상이 생기게 된다. 이 버즈 빅은 차후의 공정이 진행됨에 따라 계년에서 스트레스를 가하게 되어 누설전류를 발생시킬 뿐만 아니라 소자의 신뢰성에 심각한 영향을 야기시킨다.However, in such a LOCOS structure, a thin pad oxide film is formed on a silicon substrate, a nitride film is formed on the silicon substrate, the active region is patterned, and field oxidation is performed. At this time, since the oxide film hardly grows on the nitride film, a so-called Bird's beak phenomenon occurs in which the oxide film has a beak shape between the active region and the inactive region. The Buzz Big is stressed in later years as the process progresses, causing leakage currents and seriously affecting device reliability.
이러한 단점을 개선하기 위하여 여러 가지 소자분리방법들이 제안되었는데 그중에 대표적인 것이 일본특허공개 공보 평 1-282839호에 실린 “소자분리의 제조방법”이다. 제1도는 그중의 일실시예를 보인 것으로 그 제조방법은 다음과 같다. 먼저 제1(a)도에서 보는 바와 같이 실리콘 기판(1) 위에 얇은 산화막(2)과 질화막(3)을 형성시킨다. 그 다음 사진식각공정을 거쳐 소자분리 영역(4)을 패터닝한다. (제1(b)도) 그리고 제1(c), (d)도와 같이 다결정 실리콘(5)을 침적하고 이방성 식각법으로 질화막(3)의 측면에 다결정 실리콘 측벽(6)을 형성시킨다. 그 다음에 실리콘 기판(1)을 열산화시킨다.(필드 산화) 열산화는 다결정 실리콘 측벽(6)이 완전히 산화될 정도로 행한다. 버즈 빅은 다결정 실리콘 측벽이 산화됨에 따라 질화막(3)과 기판(1) 사이에는 발생하지 않는다. 이때 산화막(7)에는 다결정 실리콘 측벽(6)이 산화됨에 따라 돌기(9)가 생긴다.(제1(e)도) 그 다음 제1(f), (g)도에서는 상기 공정에서 발생한 돌기를 제거하기 위하여 평탄화막(8)을 웨이퍼 전면에 침적시키고 에치 백함으로써 평탄화된 산화막(10)을 형성시킨다.Various device isolation methods have been proposed to remedy these shortcomings, a representative of which is a "manufacturing method of device isolation" published in Japanese Patent Application Laid-open No. 1-282839. Figure 1 shows one embodiment of the manufacturing method is as follows. First, as shown in FIG. 1A, a thin oxide film 2 and a nitride film 3 are formed on the silicon substrate 1. The device isolation region 4 is then patterned through a photolithography process. (Fig. 1 (b)) Then, as shown in Figs. 1 (c) and (d), the polycrystalline silicon 5 is deposited and the polycrystalline silicon sidewall 6 is formed on the side of the nitride film 3 by the anisotropic etching method. Then, the silicon substrate 1 is thermally oxidized. (Field oxidation) Thermal oxidation is performed so that the polycrystalline silicon sidewall 6 is completely oxidized. Buzz big does not occur between the nitride film 3 and the substrate 1 as the polycrystalline silicon sidewalls are oxidized. At this time, as the polycrystalline silicon sidewall 6 is oxidized in the oxide film 7, protrusions 9 are formed. (FIG. 1 (e)) Next, in FIG. 1 (f) and (g), the protrusions generated in the process are shown. The planarized oxide film 10 is formed by depositing and etching back the planarization film 8 to the entire surface of the wafer for removal.
그러나, 상기한 바와 같은 종래기술은 공정 수행상 몇 가지 문제점을 갖고 있어 실제 제품의 생산에 적용하기 어려운 단점이 있다.However, the prior art as described above has some problems in the performance of the process, which is difficult to apply to the production of the actual product.
첫째, 버즈 빅의 성장은 마스킹 레이어(masking layer) 아래의 패드 산화막 두께에 의존하는데, 종래기술은 다결정 실리콘 측벽에 의해서만 버즈 빅을 제어한다. 즉, 두께 하향에 한계가 있는 패드 산화막을 그대로 사용하기 때문에 버즈 빅 제어에 한계가 있고, 측벽 아래의 패드 산화막 두께가 균일하지 않기 때문에 버즈 빅의 길이가 일정하지 않게 된다.First, the growth of the buzz big depends on the thickness of the pad oxide layer under the masking layer, which prior art controls the buzz big only by the polycrystalline silicon sidewalls. That is, since the pad oxide film having a limit in thickness downward is used as it is, there is a limitation in the buzz big control, and the length of the buzz big is not constant because the thickness of the pad oxide film under the side wall is not uniform.
둘째, 돌출된 산화막 돌기를 제거하기 위하여 평탄화막을 웨이퍼 전면에 침적시키고 에치 백을 하고 있는데 에치 백 공정 자체의 균일성이 없을 뿐만 아니라, 평탄하게 식각하기 위하여는 평탄화막과 열산화막의 식각률이 같도록 조절해야 하는데 이것은 실제 어렵고 공정 마진이 없기 때문에 제품 생산에 적용하는 것이 곤란하다.Second, in order to remove the protruding oxide projections, the planarization film is deposited on the entire surface of the wafer and etched back. In addition, there is no uniformity of the etch back process itself, and the etching rate of the planarization film and the thermal oxide film is the same so as to etch it flat. This is difficult to apply to product production because it is practically difficult and there is no process margin.
마지막으로, 평탄화후 최종 필드 산화막 프로파일의 단차가 심하여 후속 게이트를 형성시킬 때 게이트 폴리실리콘이 모두 식각되지 않고 잔류하게 되어 싱글 비트 불량(single bit fail)을 일으키는 주원인이 된다.Finally, when the level of the final field oxide profile after the planarization is severe, all of the gate polysilicon remains unetched when the subsequent gate is formed, which is a main cause of a single bit failure.
본 발명은 상기한 바와 같은 종래기술의 문제점을 해결하기 위하여 안출된 것으로서, 본 발명의 목적은 활성영역 정의시 질화막 측벽 아래의 산화막을 오우버 에치하여 양호한 필드 산화막을 형성함으로써 버즈 빅에 의한 스트레스를 최소화할 수 있는 반도체 장치의 소자분리 방법을 제공하는데 있다. 본 발명의 또다른 목적은 측벽 산화에 의하여 발생되는 돌기를 평탄화하기 위하여 별도의 평탄화막을 침적하고 에치 백 공정을 수행하는 복잡한 과정을 생략함으로써 공정 단순화를 꾀할 수 있어 물리적, 전기적 특성이 우수한 반도체 장치의 소자분리 방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and an object of the present invention is to over-etch an oxide film under a nitride film sidewall when defining an active region to form a good field oxide film, thereby reducing stress caused by buzz big. An object isolation method of a semiconductor device can be minimized. Another object of the present invention is to simplify the process by eliminating the complicated process of depositing a separate planarization film and performing an etch back process to planarize the protrusions caused by sidewall oxidation. It is to provide a device isolation method.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명은 실리콘 기판 상에 패드 산화막과 질화막을 차례로 적층시킨 후, 사진식각공정을 거쳐 질화막을 패터닝하고 선택 산화를 하여 소자분리 영역을 형성하는 반도체 장치의 소자분리 방법에 있어서, 상기 질화막 아래 공동을 형성하고 얇은 산화막을 성장시킨 다음 다결정 실리콘막을 적층시키고 이방성 식각법으로 상기 질화막 측면을 둘러싸는 다결정 실리콘 측벽을 형성하여 실리콘 기판을 선택적으로 산화시키는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 소자분리 방법을 제공한다.In order to achieve the object described above, the present invention is a device of a semiconductor device in which a pad oxide film and a nitride film are sequentially stacked on a silicon substrate, followed by a photolithography process, patterning the nitride film and performing selective oxidation to form device isolation regions. A separation method, comprising: forming a cavity under the nitride film, growing a thin oxide film, stacking a polycrystalline silicon film, and forming a polycrystalline silicon sidewall surrounding the nitride film side by anisotropic etching to selectively oxidize the silicon substrate. An element isolation method of a semiconductor device is provided.
이하 본 발명의 바람직한 실시예를 첨부한 도면에 따라 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제2도는 반도체 소자의 활성영역(11)과 비활성영역(12)을 도시한 것으로서 활성영역(11)은 질화막 패턴 아래에 놓이고 비활성 영역(12)은 필드 산화막이 형성되어 서로 소자분리가 된다.FIG. 2 shows the active region 11 and the inactive region 12 of the semiconductor device. The active region 11 is disposed under the nitride film pattern, and the inactive region 12 forms a field oxide film to separate the devices from each other.
제3도는 본 발명에 따른 반도체 장치의 소자분리 방법을 보여주는 것으로서 제2도의 X-X′선을 따라 단면을 도시한 것이다. 제3(a)도에서 보는 바와 같이 실리콘 기판(21) 위에 얇은 패드 산화막(22)을 성장시키고 그 위에 1000~2000Å 정도의 질화막을 적층시킨다. 그 다음 사진, 식각공정으로 제3(b)도와 같이 활성영역과 비활성영역을 정의한다. 이제 제3(c)도와 같이 등방성식각(wet etch)으로 비활성 영역의 패드 산화막을 제거하는데, 이 경우 등방성 식각의 특성상 활성영역 아래의 패드 산화막도 일정량 식각되어 활성영역을 따라 공동(cavity)(24)이 생긴다. 이어서 제3(d)도와 같이 패드산화막보다 얇은 산화막(25)을 성장시키는데, 이 얇은 산화막(25)은 비활성 영역 전면에 걸쳐 균일한 두께로 형성되고 그 두께의 조절이 자유로와 버즈 빅 조절이 매우 용이하게 된다.FIG. 3 is a cross-sectional view taken along line X-X 'of FIG. 2, which shows a device isolation method of a semiconductor device according to the present invention. As shown in FIG. 3A, a thin pad oxide film 22 is grown on the silicon substrate 21, and a nitride film of about 1000 to 2000 microseconds is deposited thereon. Next, the active region and the inactive region are defined by the photo-etching process as shown in FIG. 3 (b). Now, as shown in FIG. 3 (c), the pad oxide layer of the inactive region is removed by a wet etch. In this case, a certain amount of the pad oxide layer under the active region is also etched due to the property of isotropic etching, thereby forming a cavity (24) along the active region. ) Subsequently, as shown in FIG. 3 (d), an oxide film 25 thinner than the pad oxide film is grown. The thin oxide film 25 is formed to have a uniform thickness over the entire inactive region, and the thickness is freely controlled and the buzz big control is very high. It becomes easy.
일반적으로 질화막 아래의 패드 산화막은 질화막 두께의 ⅓이하의 두께가 되면 하부의 실리콘에 전위(轉位)(dislocation)를 유발하여 소자의 전기적 특성에 악영향을 미치기 때문에 그 두께의 하향에 근본적인 한계를 가지고 있다. 따라서, 본 발명에서는 이러한 한계를 극복할 수 있는 방법으로 공동을 형성한 다음 얇은 산화막을 성장시키고 그 위에 마스킹 레이어로서 스트레스의 영향이 없는 다결정 실리콘 측벽을 형성하도록 한 것이다.In general, the pad oxide film under the nitride film has a fundamental limitation in decreasing its thickness because it causes dislocations in the lower silicon when the thickness is less than or equal to the thickness of the nitride film. have. Therefore, in the present invention, a cavity is formed in such a way as to overcome this limitation, and then a thin oxide film is grown and a polycrystalline silicon sidewall free of stress influence as a masking layer is formed thereon.
그 다음 제3(e)도와 같이 다결정 실리콘막(26)을 적층시킨다. 그리고 이방성식각법으로 질화막의 측벽에 다결정 실리콘 측벽(27)을 형성시킨다. (제2(f)도) 이때 산화막과 다결정 실리콘과는 선택비가 매우 좋아(보통 poly Si:oxide=20:1) 측벽 형성이 잘 되며 하부 실리콘에 대한 침식작용도 없다. 본 발명에서는 500~1500Å 정도의 다결정 실리콘을 증착하고 이방성식각으로 측벽을 형성하는데 이때 침적한 두께만큼을 식각한 후 20~30% 정도 오우버 에치하여 질화막의 두께보다 낮게 측벽을 형성한다. 만약 적당량의 오우버 에치를 하지 않을 경우, 제4(b)도와 같이 다결정 실리콘 측벽에 산화된 돌출부위가 식각되지 않고 남아 후속 공정 진행이 불가능하게 되며 돌출부위를 제거하기 위하여 과다한 식각을 하게 되면 필드 산화막이 얇아지고 필드 모서리(edge)에 단차가 생겨 소자의 전기적 특성을 저하시키는 원인이 된다. 본 발명에서는 돌출부위를 평탄화하기 위하여 별도의 평탄화막을 침적하여 에치 백을 실시하는 복잡한 공정을 거치지 않고 다결정 실리콘 측벽 형성시 적당량 오우버 에치하여 양호한 필드 산화막을 형성할 수 있도록 하였다.Then, the polycrystalline silicon film 26 is laminated as shown in FIG. 3 (e). The polycrystalline silicon sidewall 27 is formed on the sidewall of the nitride film by anisotropic etching. At this time, the selectivity between the oxide film and the polycrystalline silicon is very good (usually poly Si: oxide = 20: 1), and the sidewalls are formed well and there is no erosion effect on the lower silicon. In the present invention, the deposition of polycrystalline silicon of about 500 ~ 1500Å and to form a sidewall by anisotropic etching, the sidewall is formed lower than the thickness of the nitride film by etching over 20 ~ 30% after etching the deposited thickness. If an appropriate amount of over-etching is not performed, the oxidized protrusions on the sidewall of the polycrystalline silicon are not etched as shown in FIG. 4 (b), and subsequent processes cannot be performed, and the excessive etching is performed to remove the protrusions. The oxide film becomes thin and a step is generated in the field edge, which causes the device to degrade the electrical characteristics. In the present invention, a planar oxide film can be formed by appropriately over-etching the polysilicon sidewalls without the complicated process of depositing a separate planarization film to etch back to planarize the protrusions.
또한, 형성된 다결정 실리콘 측벽은 제3(d)도에서 형성된 공동을 매립하게 되는데 매립된 다결정 실리콘은 필드 산화막 성장시 산화되지 않고 제4(c)도에서 보는 바와 같이 남게 된다. 이러한 현상은 다결정 실리콘의 볼록한(convex) 부분과 오목한(concave) 부분에서 산화가 잘 되지 않는 것으로 설명될 수 있다. 이 고립된 다결정 실리콘은 재성장시킨 얇은 산화막과 함께 버즈 빅을 제어하는 주요소로 작용한다.In addition, the formed polycrystalline silicon sidewall fills the cavity formed in FIG. 3 (d), and the embedded polycrystalline silicon is not oxidized during field oxide film growth and remains as shown in FIG. 4 (c). This phenomenon can be explained by poor oxidation in the convex and concave portions of the polycrystalline silicon. This isolated polycrystalline silicon, along with the regrown thin oxide film, acts as a key element in controlling Buzz Big.
제3(f)도 다음 공정으로 필드 산화막(28)을 성장시키면 제3(g)도와 같은 모양이 형성되는데 다결정 실리콘이 산화되는 동안 기판 레벨 이하로의 산화가 줄어 스트레스가 감소하므로 소자의 누설전류도 매우 적게 될 뿐 아니라 질화막 측벽에 생기는 산화막의 돌기(29)도 종래기술보다 현저히 낮아 단차에서 오는 어려움을 극복할 수 있다.When the field oxide film 28 is grown in the following process, the third (f) also has a shape similar to that of the third (g). During the oxidation of the polycrystalline silicon, the oxidation to the substrate level or less decreases the stress, thereby reducing the leakage current of the device. In addition, the projections 29 of the oxide film formed on the nitride film sidewalls are also significantly lower than those of the prior art, thereby overcoming the difficulty of the step difference.
이후, 캡(cap) 산화막, 질화막, 패드 산화막을 차례로 제거하면 제3(h)도와 같은 최종 산화막 프로파일을 얻을 수 있다. 실제로 위의 공정 수순에 의하여 구현된 소자분리 프로파일이 제4(a)도 및 제5도에 잘 나타나 있다. 상기 도면에서 보여주는 바와 같이 후속 게이트 공정에 문제가 없는 양호한 수직구조를 나타내고 있으며 버즈 빅 조절이 매우 용이하여 활성영역과 비활성 영역이 양호하게 정의된 셀 구조를 구현할 수 있다.Thereafter, the cap oxide film, the nitride film, and the pad oxide film are sequentially removed to obtain a final oxide film profile as shown in FIG. 3 (h). In fact, the device isolation profile implemented by the above process procedure is well illustrated in FIGS. 4 (a) and 5. As shown in the figure, it shows a good vertical structure having no problem in the subsequent gate process, and it is very easy to adjust the buzz big to realize a cell structure in which the active region and the inactive region are well defined.
이상과 같은 본발명의 소자분리 방법으로 버즈 빅으로 인한 스트레스를 최소화할 수 있어 소자의 전기적 특성 등 신뢰성을 향상시킬 수 있고 공정을 단순화하므로써 경비 절감 및 쓰루풋(thruput) 향상을 기대할 수 있는 잇점이 있다.The device isolation method of the present invention can minimize the stress caused by the buzz big to improve the reliability, such as the electrical characteristics of the device, and the advantages can be expected to reduce the cost and improve the throughput by simplifying the process .
Claims (5)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019940012841A KR100303438B1 (en) | 1994-06-08 | 1994-06-08 | Device isolation method of semiconductor device |
| DE69524992T DE69524992T2 (en) | 1994-06-08 | 1995-06-06 | Method of isolating parts of a semiconductor device |
| US08/470,914 US5641705A (en) | 1994-06-08 | 1995-06-06 | Device isolation method of semiconductor device |
| EP95303890A EP0687001B1 (en) | 1994-06-08 | 1995-06-06 | Device isolation method for a semiconductor device |
| CN95107354A CN1059517C (en) | 1994-06-08 | 1995-06-08 | Device isolation method of semiconductor device |
| JP16830195A JP3468920B2 (en) | 1994-06-08 | 1995-06-08 | Element isolation method for semiconductor device |
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| KR1019940012841A KR100303438B1 (en) | 1994-06-08 | 1994-06-08 | Device isolation method of semiconductor device |
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