KR0146525B1 - Method for manufacturing thin film transistor - Google Patents

Method for manufacturing thin film transistor

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Publication number
KR0146525B1
KR0146525B1 KR1019950011225A KR19950011225A KR0146525B1 KR 0146525 B1 KR0146525 B1 KR 0146525B1 KR 1019950011225 A KR1019950011225 A KR 1019950011225A KR 19950011225 A KR19950011225 A KR 19950011225A KR 0146525 B1 KR0146525 B1 KR 0146525B1
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South Korea
Prior art keywords
impurity ions
source
transistor
forming
ldd
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KR1019950011225A
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Korean (ko)
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KR960043050A (en
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박영택
오영균
김의식
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김주용
현대전자산업주식회사
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Priority to KR1019950011225A priority Critical patent/KR0146525B1/en
Priority to TW085105472A priority patent/TW371783B/en
Priority to JP8113675A priority patent/JPH08306923A/en
Priority to CN96110002A priority patent/CN1050691C/en
Publication of KR960043050A publication Critical patent/KR960043050A/en
Application granted granted Critical
Publication of KR0146525B1 publication Critical patent/KR0146525B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체 소자의 트랜지스터 제조방법에 관하여 개시된다.The present invention relates to a method for manufacturing a transistor of a semiconductor device.

본 발명은 4가의 불순물이온을 주입하여 실리콘기판의 소오스/드레인영역이 형성될 부위에 비정질실리콘층을 형성시키므로써 채널링 현상을 억제하고, 얕은 접합영역(Shallow Junction)을 형성하며, 소자의 신뢰성을 향상시킬 수 있도록 한 반도체 소자의 트랜지스터 제조방법에 관한 것이다.According to the present invention, an amorphous silicon layer is formed at a portion where a source / drain region of a silicon substrate is to be formed by implanting tetravalent impurity ions, thereby suppressing channeling phenomenon, forming a shallow junction region, and improving device reliability. The present invention relates to a method for manufacturing a transistor of a semiconductor device that can be improved.

Description

반도체 소자의 트랜지스터 제조방법Transistor manufacturing method of semiconductor device

제1a 내지 1c도는 종래의 반도체 소자의 트랜지스터 제조방법을 설명하기 위해 도시한 소자의 단면도.1A to 1C are cross-sectional views of a device shown for explaining a transistor manufacturing method of a conventional semiconductor device.

제2a 내지 제2e도는 본 발명에 따른 반도체 소자의 트랜지스터 제조방법을 설명하기 위해 도시한 소자의 단면도.2A through 2E are cross-sectional views of a device for explaining the method of manufacturing a transistor of a semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘기판 2 : 게이트산화막1 silicon substrate 2 gate oxide film

3 : 게이트전극 4 : 산화막스페이서3: gate electrode 4: oxide spacer

5 : 희생산화막 6 : LDD 영역5: sacrificial oxide film 6: LDD region

7 : 소오스/드레인영역 8 : 비정질실리콘층7 source / drain region 8 amorphous silicon layer

9 : 접합부9: junction

본 발명은 반도체 소자의 트랜지스터 제조방법에 관한 것으로, 특히 4가의 불순물이온을 주입하여 실리콘기판의 소오스/드레인영역이 형성될 부위의 실리콘을 비정질화 한 다음 LDD구조의 소오스/드레인영역 형성 공정을 실시하므로써 채널링 현상을 억제하고, 얕은 접합영역(Shallow Junction)을 형성하며, 소자의 신뢰성을 향상시킬 수 있도록 한 반도체 소자의 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a transistor in a semiconductor device, and in particular, implants tetravalent impurity ions into amorphous silicon at a portion where a source / drain region of a silicon substrate is to be formed, and then performs a source / drain region formation process of an LDD structure. Accordingly, the present invention relates to a method of fabricating a transistor of a semiconductor device, which can suppress channeling, form a shallow junction, and improve device reliability.

일반적으로 반도체 소자가 고집적화 및 소형화 되어감에 따라 게이트의 채널길이도 짧아진다. 0.5㎛ 이하의 짧은 채널을 갖는 반도체 소자를 제조함에 있어 터널링현상을 억제시키고, 구동능력을 높이기 위해서는 깊이가 얕으면서 저항이 낮은 접합부를 형성하여야 한다.In general, as semiconductor devices become highly integrated and miniaturized, the channel length of the gate becomes shorter. In manufacturing a semiconductor device having a short channel of 0.5 μm or less, in order to suppress tunneling and increase driving ability, a junction having a low depth and low resistance should be formed.

제1a 내지 제1c도는 종래의 반도체 소자의 트랜지스터 제조방법을 설명하기 위해 도시한 소자의 단면도이다.1A to 1C are cross-sectional views of a device illustrated to explain a transistor manufacturing method of a conventional semiconductor device.

제1a도는 실리콘기판(1)상에 게이트산화막(2)을 형성하고, 게이트산화막(2)상에 폴리실리콘층을 증착한 후, 게이트 전극 마스크(도시안됨)를 사용한 리소그라피 공정 및 폴리실리콘 식각공정으로 게이트전극(3)을 형성한 후, LDD 이온주입 마스크(도시안됨)를 사용한 리소그라피 공정 및 LDD 이온주입공정을 실시한 상태의 단면도이다.FIG. 1A shows a gate oxide film 2 formed on a silicon substrate 1, a polysilicon layer is deposited on the gate oxide film 2, and then a lithography process and a polysilicon etching process using a gate electrode mask (not shown). After forming the gate electrode 3, it is sectional drawing of the state which performed the lithography process and LDD ion implantation process using an LDD ion implantation mask (not shown).

상기 LDD 이온은 PMOS 트랜지스터를 제조할 경우에는 P-타입의 불순물이온을 주입하고, NMOS 트랜지스터를 제조할 경우에는 N-타입의 불순이온을 주입하게 된다.The LDD ions implant P-type impurity ions in the manufacture of PMOS transistors and the N − type impurity ions in the manufacture of NMOS transistors.

제1b도는 게이트전극(3)의 측벽에 산화막스페이서(4)를 형성하고, 게이트전극(3) 및 산화막스페이서(4)를 포함한 전체구조상에 희생산화막(5)을 형성한 후, 소오스/드레인 불순물 이온주입 마스크(도시안됨)를 사용한 리소그라피 공정 및 소오스/드래인 불순물 이온주입공정을 실시한 상태의 단면도이다.In FIG. 1B, an oxide spacer 4 is formed on the sidewall of the gate electrode 3, a sacrificial oxide film 5 is formed on the entire structure including the gate electrode 3 and the oxide spacer 4, and then source / drain impurities are formed. It is sectional drawing of the state which performed the lithography process using an ion implantation mask (not shown), and the source / drain impurity ion implantation process.

상기 소오스/드레인 불순물 이온은 PMOS 트랜지스터를 제조할 경우에는 P+타입의 불순물이온을 주입하게 된다.The source / drain impurity ions are implanted with P + type impurity ions when manufacturing a PMOS transistor.

제1c도는 희생산화막(5)을 제거하고, 열처리공정을 실시하여 상기 공정에서 주입된 LDD 이온 및 소오스/드레인 불순물 이온을 실리콘기판(1) 내부로 확산시켜 LDD 영역(6)과 소오스/드레인영역(7)를 형성한 상태의 단면도이다.FIG. 1C shows that the sacrificial oxide film 5 is removed and the heat treatment process is performed to diffuse the LDD ions and the source / drain impurity ions implanted in the process into the silicon substrate 1 so that the LDD region 6 and the source / drain region It is sectional drawing of the state which formed (7).

상기에서, PMOS 트랜지스터의 접합부를 형성하는 경우 불순물이온으로는 주로 붕소이온을 사용하는데, 이 붕소이온의 우수한 확산 특성으로 인하여 접합부의 깊이가 0.2 내지 0.3㎛ 정도가 되어 얕은 접합부를 형성할 수 없고, BF2이온을 사용할 경우 불소이온이 게이트산화막에 침투하여 게이트산화막의 막질을 열화시키는 문제가 있다. NMOS 트랜지스터의 접합부를 형성하는 경우에는 불순물이온으로 붕소보다 중량이 무거운 비소(As)나 인(P)이온을 주입하여 형성하기 때문에 얕은 접합부를 형성하기가 용이하지만 반도체 소자가 집적화 및 소형화 되어감에 따라 접합부 영역을 확보하는데 어려운 단점이 있다.In the above, when forming the junction portion of the PMOS transistor, boron ions are mainly used as impurity ions. Due to the excellent diffusion characteristics of the boron ions, the junction portion has a depth of about 0.2 to 0.3 μm, and thus, a shallow junction cannot be formed. In the case of using BF 2 ions, fluorine ions penetrate into the gate oxide film and deteriorate the film quality of the gate oxide film. In the case of forming the junction of an NMOS transistor, it is easy to form a shallow junction because an impurity ion is formed by injecting arsenic (As) or phosphorus (P) ion, which is heavier than boron, to form an integrated and miniaturized semiconductor device. Therefore, there is a disadvantage in that it is difficult to secure the junction region.

따라서 본 발명은 소오스/드레인영역이 형성될 부위의 실리콘기판에 4가의 불순물이온을 주입하여 그 부분을 비정질화 한 다음 LDD 구조의 소오스/드레인영역 형성공정을 실시하므로써, 상기한 단점을 해소할 수 있는 반도체 소자의 트랜지스터 제조방법을 제공하는데 그 목적이 있다.Therefore, the present invention can solve the above-mentioned disadvantages by injecting tetravalent impurity ions into the silicon substrate of the portion where the source / drain region is to be formed and then amorphizing the portion, and then performing the source / drain region forming process of LDD structure. It is an object of the present invention to provide a method for manufacturing a transistor of a semiconductor device.

상술한 목적을 달성하기 위한 본 발명은 실리콘기판상에 게이트전극을 형성하는 단계와, 상기 단계로부터 실리콘기판의 소오스/드레인영역이 형성될 부위를 불순물이온을 주입하여 비정질실리콘층으로 형성하는 단계와, 상기 단계로부터 LDD 이온주입 공정을 실시하는 단계와, 상기 단계로부터 게이트전극의 측벽에 산화막스페이서를 형성하고, 상기 게이트전극 및 산화막스페이서를 포함한 전체구조상에 소오스/드레인 불순물 이온주입 공정을 실시하는 단계와, 상기 단계로부터 열처리공정을 실시하여 LDD구조를 갖는 접합부를 형성하는 단계로 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is a step of forming a gate electrode on a silicon substrate, the step of forming the amorphous silicon layer by injecting impurity ions to the source / drain region of the silicon substrate to be formed from the step; Performing an LDD ion implantation process from the above step; forming an oxide spacer on the sidewall of the gate electrode; and performing a source / drain impurity ion implantation process on the entire structure including the gate electrode and the oxide spacer. And forming a junction having an LDD structure by performing a heat treatment process from the above step.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

제2a 내지 2e도는 본 발명에 따른 반도체 소자의 트랜지스터 제조방법을 설명하기 위해 도시한 소자의 단면도이다.2A through 2E are cross-sectional views of a device for explaining the method of manufacturing a transistor of the semiconductor device according to the present invention.

제2a도는 실리콘기판(1)상에 게이트산화막(2)을 형성하고, 게이트산화막(2)상에 폴리실리콘을 증착한 후, 게이트 전극용 마스크(도시안됨)를 사용한 리소그라피 공정 및 폴리실리콘 식각공정으로 게이트전극(3)을 형성한 상태의 단면도이다.2A shows a gate oxide film 2 formed on the silicon substrate 1, polysilicon is deposited on the gate oxide film 2, and then a lithography process and a polysilicon etching process using a mask (not shown) for the gate electrode. Is a cross-sectional view of the state in which the gate electrode 3 is formed.

제2b도는 상기 단계로부터 소오스/드레인영역이 형성될 부위의 실리콘기판(1)에 이온 주입공정을 통해 4가의 불순물을 주입하여 비정질 실리콘층(8)을 형성한 상태의 단면도이다.FIG. 2B is a cross-sectional view of the amorphous silicon layer 8 formed by implanting tetravalent impurities into the silicon substrate 1 at the portion where the source / drain regions are to be formed from the above step by an ion implantation process.

제2c도는 상기 단계에서 LDD 이온주입 마스크(도시안됨)를 사용한 리소그라피 공정 및 LDD 이온주입공정을 실시하여 비정질실리콘층(8)에 LDD영역(6)을 형성한 상태의 단면도이다.FIG. 2C is a cross-sectional view of a state in which the LDD region 6 is formed in the amorphous silicon layer 8 by performing a lithography process using an LDD ion implantation mask (not shown) and an LDD ion implantation process in the above steps.

상기에서 LDD 이온은 PMOS 트랜지스터를 제조할 경우에는 P-타입의 불순물이온을 주입하고, NMOS 트랜지스터를 제조할 경우에는 N-타입의 불순물이온을 주입하게 된다.In the above, LDD ions implant P - type impurity ions when manufacturing a PMOS transistor, and N - type impurity ions when implanting an NMOS transistor.

제2d도는 게이트전극(3)의 측벽에 산화막스페이서(4)를 형성하고, 게이트전극(3) 및 산화막스페이서(4)를 포함한 전체구조상에 소오스/드레인 불순물 이온주입 마스크(도시안됨)를 사용한 리소그라피 공정 및 소오스/드레인 불순물 이온주입공정을 실시하여 소오스/드레인영역(7)을 형성한 상태의 단면도이다.2d shows an oxide spacer 4 formed on the sidewall of the gate electrode 3 and a lithography using a source / drain impurity ion implantation mask (not shown) over the entire structure including the gate electrode 3 and the oxide spacer 4. A cross-sectional view of a state in which the source / drain regions 7 are formed by performing a step and a source / drain impurity ion implantation step.

상기에서 소오스/드레인 불순물 이온은 PMOS 트랜지스터를 제조할 경우에 P+타입의 불순물이온을 주입하고, NMOS 트랜지스터를 제조할 경우에는 N+타입의 불순물이온을 주입하게 된다.The source / drain impurity ions are implanted with P + type impurity ions when manufacturing a PMOS transistor, and implanted with N + type impurity ions when an NMOS transistor is manufactured.

제2e도는 열처리공정을 실시하여 LDD영역(6) 및 소오스/드레인영역(7)의 불순물을 확산시켜 트랜지스터의 접합부(9)를 형성한 것이 도시된다.FIG. 2E shows that the junction 9 of the transistor is formed by diffusing impurities in the LDD region 6 and the source / drain region 7 by performing a heat treatment process.

상술한 바와같이 본 발명은 소오스/드레인영역이 형성될 부위의 실리콘기판에 4가의 불순물이온을 주입하여 비정질화 한 다음 LDD구조의 소오스/드레인영역 형성공정을 실시하므로써, 반도체 소자의 터널링현상을 억제시키고, 얕은 접합영역(Shallow Junction) 형성이 가능하며, 소자의 신뢰성 향상에 탁월한 효과가 있다.As described above, the present invention suppresses the tunneling phenomenon of the semiconductor device by injecting a tetravalent impurity ion into the silicon substrate of the portion where the source / drain region is to be formed to be amorphous and then performing the source / drain region formation process of the LDD structure. In addition, it is possible to form a shallow junction and have an excellent effect on improving the reliability of the device.

Claims (4)

반도체 소자의 트랜지스터 제조방법에 있어서, 실리콘기판상에 게이트전극을 형성하는 단계와, 상기 단계로부터 실리콘기판의 소오스/드레인영역이 형성될 부위를 불순물이온을 주입하여 비정질실리콘층으로 형성하는 단계와, 상기 단계로부터 LDD 이온주입 공정을 실시하는 단계와, 상기 단계로부터 게이트전극의 측벽에 산화막스페이서를 형성하고, 상기 게이트전극 및 산화막스페이서를 포함한 전체구조상에 소오스/드레인 불순물 이온주입 공정을 실시하는 단계와, 상기 단계로부터 열처리공정을 실시하여 LDD구조를 갖는 접합부를 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.A method of manufacturing a transistor of a semiconductor device, comprising the steps of: forming a gate electrode on a silicon substrate; forming a amorphous silicon layer by implanting impurity ions into a portion where a source / drain region of the silicon substrate is to be formed; Performing an LDD ion implantation process from the above step, forming an oxide film spacer on the sidewall of the gate electrode, and performing a source / drain impurity ion implantation process on the entire structure including the gate electrode and the oxide film spacer; And forming a junction portion having an LDD structure by performing a heat treatment process from the above step. 제1항에 있어서, 상기 비정질실리콘층을 형성하기 위해 주입하는 불순물이온은 4가의 불순물이온인 것을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.The method of claim 1, wherein the impurity ions implanted to form the amorphous silicon layer are tetravalent impurity ions. 제1항에 있어서, 상기 LDD 이온은 PMOS 트랜지스터를 제조할 경우에 P-타입의 불순물 이온이고, NMOS 트랜지스터를 제조할 경우에 N-타입의 불순물 이온인 것을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.The method of claim 1, wherein the LDD ions are P - type impurity ions in the manufacture of a PMOS transistor, and N - type impurity ions in the manufacture of an NMOS transistor. 제1항에 있어서, 상기 소오스/드레인 불순물 이온은 PMOS 트랜지스터를 제조할 경우에 P+타입의 불순물 이온이고, NMOS 트랜지스터를 제조할 경우에 N+타입의 불순물 이온인 것을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.The semiconductor device transistor according to claim 1, wherein the source / drain impurity ions are P + type impurity ions when a PMOS transistor is manufactured, and N + type impurity ions when an NMOS transistor is manufactured. Manufacturing method.
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