CN1146627A - Method for making transistor of semiconductor device - Google Patents
Method for making transistor of semiconductor device Download PDFInfo
- Publication number
- CN1146627A CN1146627A CN96110002A CN96110002A CN1146627A CN 1146627 A CN1146627 A CN 1146627A CN 96110002 A CN96110002 A CN 96110002A CN 96110002 A CN96110002 A CN 96110002A CN 1146627 A CN1146627 A CN 1146627A
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- China
- Prior art keywords
- foreign ion
- making
- source
- ion
- leakage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 title claims description 20
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 claims abstract description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 22
- 238000010438 heat treatment Methods 0.000 claims description 7
- 238000002347 injection Methods 0.000 claims description 7
- 239000007924 injection Substances 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 abstract description 30
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- -1 LDD ion Chemical class 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The present invention relates to method of manufacturing transistor of semiconductor device comprises forming an amorphous Si layer by implanting tetravalent impurity ions in the Si substrate to form source/drain regions, thus suppressing the channel phenomenon to form shallow junction regions and hence improve the device reliability.
Description
The present invention relates to make the transistorized method of semiconductor device, be particularly related to the transistorized method of following manufacturing semiconductor device, formation technology by special source/drain region of injecting 4-valency foreign ion and carrying out subsequently, noncrystalline silicon area in partial silicon substrate forms source-drain area, this method may suppress the channelling phenomenon, form shallow junction, increase the reliability of device.
Usually, as the high integrated and further semiconductor device of miniaturization gradually, further shorten the channel length of grid.Making the situation of channel length, will form shallow junction and low-resistance, to suppress the channelling phenomenon and to increase driving force less than the semiconductor device of 0.5 μ m.
Figure 1A is the cutaway view of device to Fig. 1 C, and the transistorized conventional method of semiconductor device is made in expression.
Figure 1A is the cutaway view of the following situation of expression, forms gate oxidation films 2 on silicon substrate 1, forms polysilicon on gate oxidation films 2, after this, utilize gate electrode to make the mask (not shown), carry out photoetching process and corrosion polysilicon process, form gate electrode 3, carry out the LDD ion implantation technology at last.
About the LDD ion, when making the PMOS transistor, inject P
-The type foreign ion injects N when making nmos pass transistor
-The type foreign ion.
Figure 1B is the cutaway view of the following situation of expression, and the sidewall formation oxide-film separator 4 at gate electrode 3 forms the oxide-film 5 that will be removed on the total that comprises gate electrode 3 and oxide-film separator 4, carry out source/leakage foreign ion later on and inject.
For source/leakage foreign ion, when making the PMOS transistor, inject P
+The type foreign ion injects N when making nmos pass transistor
-The type foreign ion.
Fig. 1 C is that the cutaway view of the oxide-film 5 following situations that will be removed is removed in expression, and by heat treatment, the assorted daughter ion of source/leakage that diffusion LDD ion and above-mentioned technology are injected enters silicon substrate 1 inside, forms LDD district 6 and source/drain region 7.
As mentioned above, when forming the transistorized knot of PMOS, mainly utilize the boron ion as foreign ion, still, have following problems, because the boron ion has fast diffusion property, the knot source becomes about 0.2 to 0.3 μ m, thus can not form shallow junction, and utilizing BF
2The situation of ion is because fluorine ion pierces into gate oxidation films, and the result reduces the film quality of gate oxidation films.When forming the knot of nmos pass transistor, owing to inject than the heavy As of boron ion or P ion as foreign ion, though form shallow junction easily, but still existing problems, promptly when progressively increasing integrated level and miniaturization semiconductor device, then be difficult to guarantee to form shallow junction region.
Therefore, the purpose of this invention is to provide a kind of transistorized method of making semiconductor device, so that address the above problem, it adopts the noncrystalline part of silicon substrate, by injecting 4-valency foreign ion, carry out source/drain region then and form technology, form source/drain region thereon.
A kind ofly make the transistorized method of semiconductor device, it is characterized in that comprising the following steps, on silicon substrate, form gate electrode according to the present invention; By foreign ion being injected in the part that silicon substrate will form source/drain region, form noncrystalline silicon layer; Carry out the LDD ion implantation technology; Form the oxide-film separator on the gate electrode sidewall and comprising gate electrode and the total of oxide-film separator on carry out source/leakage impurity injection technology; By Technology for Heating Processing, be formed with the knot of LDD structure.
For understanding feature of the present invention and purpose more fully, will carry out detailed narration with reference to following accompanying drawing:
Figure 1A is the cutaway view that transistorized a kind of conventional method of semiconductor device is made in expression to Fig. 1 C.
Fig. 2 A is the cutaway view that transistorized a kind of method of semiconductor device of the present invention is made in expression to Fig. 2 E.
Describe the 1st embodiment of the present invention in detail below with reference to accompanying drawing.
Figure 1A is the aforesaid a kind of cutaway view of making the transistor method of semiconductor device of expression to Fig. 1 C.
Fig. 2 A is that expression is according to a kind of cutaway view of making the transistorized method of semiconductor device of the present invention to Fig. 2 E.
Fig. 2 A is the cutaway view of the following situation of expression, forms gate oxidation films 2 on silicon substrate 1, forms polysilicon on gate oxidation films 2, after, utilize gate electrode as the mask (not shown) by photoetching process and corrosion polysilicon process, form gate electrode 3.
Fig. 2 B is the cutaway view of the following situation of expression, forms noncrystalline silicon layer 8 on partial silicon substrate 1, at this place, inject 4-valency foreign ion, formation source/drain region by ion implantation technology.
Fig. 2 C is the cutaway view of the following situation of expression, by the LDD ion implantation technology, on noncrystalline silicon layer 8, forms LDD district 6.
Fig. 2 D is the cutaway view of the following situation of expression, at the sidewall formation oxide-film separator 4 of gate electrode, and by source/leakage impure ion injection technology, on the total that comprises grid 3 and oxide-film separator 4, formation source/drain region 7.
To source/leakage foreign ion, when making the PMOS transistor, inject P
+The type foreign ion when making nmos pass transistor, injects N
+The type foreign ion.
Fig. 2 E is the cutaway view of the following situation of expression, and by Technology for Heating Processing, the impurity in diffusion LDD district and source/drain region 7 forms transistorized knot 9.
As the 2nd embodiment, a kind of transistorized method of making semiconductor device comprises the steps, forms gate electrode on silicon substrate; To form noncrystalline silicon layer by foreign ion being injected in the part that silicon substrate will form source/drain region, carry out source/leakage foreign particle injection technology on the total of grid comprising; Form knot by Technology for Heating Processing.
For source/leakage foreign ion, when making the PMOS transistor, inject P
+The type foreign ion injects N when making nmos pass transistor
+The type foreign ion.
As the 3rd embodiment, a kind of transistorized method of making semiconductor device comprises the following steps: to form gate electrode on silicon substrate; By foreign ion being injected in the part of the silicon substrate that will form source/drain region, form amorphous silicon; Sidewall at gate electrode forms the oxide-film separator, carries out source/leakage impure ion injection technology on the total that comprises gate electrode and oxide-film separator; Form knot by Technology for Heating Processing.
For source/leakage foreign ion, when making the PMOS transistor, inject P
+Foreign ion when making nmos pass transistor, injects N
+The type foreign ion.
As mentioned above, the present invention has extraordinary effect, promptly will form on the noncrystalline partial silicon substrate in source/drain region, inject the foreign ion of 4-valency, after, carry out source/drain region and form technology, then suppress semi-conductive channelling phenomenon, may form shallow junction, and may improve the reliability of device.
Claims (10)
1. a transistorized method of making semiconductor device comprises the following steps,
On silicon substrate, form grid;
Part the substrate in foreign ion injection will formation source/drain region forms amorphous silicon layer;
Carry out the LDD ion implantation technology;
On described gate lateral wall, form the oxide-film separator,
Carrying out source/leakage impurity on the total that comprises described grid and oxide-film separator injects;
Heat-treat technology, form the interface of LDD structure.
2. according to the method for claim 1, it is characterized in that, inject the foreign ion that described foreign ion is the 4-valency for forming described amorphous silicon layer.
3. according to the method for claim 1, it is characterized in that described LDD ion is P when making the PMOS transistor
-The type foreign ion is N when making nmos pass transistor
-The type foreign ion.
4. according to the method for claim 1, it is characterized in that described source/leakage foreign ion is P when making the PMOS transistor
+The type foreign ion is N when making nmos pass transistor
+The type foreign ion.
5. a transistorized method of making semiconductor device comprises the following steps,
On silicon substrate, form grid;
Foreign ion is injected in the part that will form source/leakage on the silicon substrate;
Comprising injection source on the total of described grid/leakage impurity;
Utilize heat treatment to form knot.
6. according to the method for claim 5, it is characterized in that injecting the foreign ion that described foreign ion is 4 valencys for forming described amorphous silicon layer.
7. according to the method for claim 5, it is characterized in that described source/leakage foreign ion, is P when making the PMOS transistor
+The type foreign ion is N when making nmos pass transistor
+The type foreign ion.
8. a transistorized method of making semiconductor device comprises the following steps,
Form grid at silicon substrate;
Foreign ion is injected in the part of the substrate that will form source/drain region, to form amorphous silicon layer;
On the sidewall of described grid, form oxide-film separator, injection source/leakage foreign ion on the total that comprises described grid and oxide-film separator;
Utilize heat treatment to form knot.
9. according to the method for claim 8, it is characterized in that injecting the foreign ion that described foreign ion is the 4-valency for forming described amorphous silicon layer.
10. according to the method for claim, it is characterized in that described source/leakage foreign ion is P when making the PMOS transistor
+The type foreign ion is N when making nmos pass transistor
+The type foreign ion.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950011225A KR0146525B1 (en) | 1995-05-09 | 1995-05-09 | Method for manufacturing thin film transistor |
| KR11225/95 | 1995-05-09 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1146627A true CN1146627A (en) | 1997-04-02 |
| CN1050691C CN1050691C (en) | 2000-03-22 |
Family
ID=19413930
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96110002A Expired - Fee Related CN1050691C (en) | 1995-05-09 | 1996-05-09 | Method for making transistor of semiconductor device |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPH08306923A (en) |
| KR (1) | KR0146525B1 (en) |
| CN (1) | CN1050691C (en) |
| TW (1) | TW371783B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100442444C (en) * | 2003-10-17 | 2008-12-10 | Imec公司 | Method for providing a semiconductor substrate with a layer structure of activated dopants |
| CN102148245A (en) * | 2010-02-10 | 2011-08-10 | 上海宏力半导体制造有限公司 | Intrinsic MOS (metal oxide semiconductor) transistor and forming method thereof |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6333217B1 (en) | 1999-05-14 | 2001-12-25 | Matsushita Electric Industrial Co., Ltd. | Method of forming MOSFET with channel, extension and pocket implants |
| KR100429873B1 (en) * | 2001-07-19 | 2004-05-04 | 삼성전자주식회사 | MOS transistor and forming method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0795535B2 (en) * | 1986-12-19 | 1995-10-11 | 日本電信電話株式会社 | Method for manufacturing semiconductor device |
| JPH04158529A (en) * | 1990-10-23 | 1992-06-01 | Oki Electric Ind Co Ltd | Fabrication of semiconductor element |
| JP2683979B2 (en) * | 1991-04-22 | 1997-12-03 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
| JPH06302824A (en) * | 1993-02-16 | 1994-10-28 | Sanyo Electric Co Ltd | Thin-film transistor and its manufacture |
-
1995
- 1995-05-09 KR KR1019950011225A patent/KR0146525B1/en not_active IP Right Cessation
-
1996
- 1996-05-08 TW TW085105472A patent/TW371783B/en active
- 1996-05-08 JP JP8113675A patent/JPH08306923A/en active Pending
- 1996-05-09 CN CN96110002A patent/CN1050691C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100442444C (en) * | 2003-10-17 | 2008-12-10 | Imec公司 | Method for providing a semiconductor substrate with a layer structure of activated dopants |
| CN102148245A (en) * | 2010-02-10 | 2011-08-10 | 上海宏力半导体制造有限公司 | Intrinsic MOS (metal oxide semiconductor) transistor and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR960043050A (en) | 1996-12-21 |
| CN1050691C (en) | 2000-03-22 |
| JPH08306923A (en) | 1996-11-22 |
| KR0146525B1 (en) | 1998-11-02 |
| TW371783B (en) | 1999-10-11 |
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| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20000322 Termination date: 20100509 |